diff --git a/.claude/settings.local.json b/.claude/settings.local.json
index 6ea7866..4572f40 100644
--- a/.claude/settings.local.json
+++ b/.claude/settings.local.json
@@ -3,7 +3,20 @@
     "allow": [
       "Bash(pip install:*)",
       "Bash(python:*)",
-      "Bash(taskkill:*)"
+      "Bash(taskkill:*)",
+      "Bash(git add:*)",
+      "Bash(git commit:*)",
+      "Bash(ls:*)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance status)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance ls-files)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance check-ignore D:/Mirek/ZPrAE/Distance/tester.py D:/Mirek/ZPrAE/Distance/distance_algorithm.py)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance status:*)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance ls-files:*)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance add tester.py distance_algorithm.py)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance log --oneline -3)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance log --oneline -5)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance show --stat HEAD)",
+      "Bash(git -C D:/Mirek/ZPrAE/Distance show --stat 46a3283)"
     ]
   }
 }
diff --git a/ZDistA_komp.c b/ZDistA_komp.c
new file mode 100644
index 0000000..44a810b
--- /dev/null
+++ b/ZDistA_komp.c
@@ -0,0 +1,1994 @@
+/*
+ * ZDistA.c
+ *
+ *  Created on: 09-03-2017
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#include <math.h>
+
+
+#include "../tdefs.h"
+#include "../misc.h"
+#include "helper.h"
+#include "analog_in.h"
+#include "e_phi.h"
+
+#include "ZDistA_komp.h"
+
+#define RnaS (3.141593 / 180)
+#define filtr_P 5,5
+
+struct nast_pomoc
+{
+	float R1W_Zf1W_LE;
+	float R1W_Zf1W_LL;
+	float R1_Zf1_LE;
+	float R1_Zf1_LL;
+	float R2_Zf2_LE;
+	float R2_Zf2_LL;
+	float R3_Zf3_LE;
+	float R3_Zf3_LL;
+	float R4_Zf4_LE;
+	float R4_Zf4_LL;
+	float R5_Zf5_LE;
+	float R5_Zf5_LL;
+	float X1W_Zr1W_LE;
+	float X1W_Zr1W_LL;
+	float X1_Zr1_LE;
+	float X1_Zr1_LL;
+	float X2_Zr2_LE;
+	float X2_Zr2_LL;
+	float X3_Zr3_LE;
+	float X3_Zr3_LL;
+	float X4_Zr4_LE;
+	float X4_Zr4_LL;
+	float X5_Zr5_LE;
+	float X5_Zr5_LL;
+};
+
+static float KI0_I2_Re,KI0_I2_Im,M,KI0_I2;//,Z_Z1min_old,Zmf_Z1min_old;
+
+static int blok_do_szyn = 0;
+static int blok_do_linii = 0;
+static int blokada_od_spz=0;
+
+int ZDistA_komp_initlog(void *arguments, void *logic)
+{
+	struct ZDistA_komp_args *args = (struct ZDistA_komp_args *)arguments;
+	struct ZDistA_komp_logic *log = (struct ZDistA_komp_logic *)logic;
+	float locX1,locX2,locR1,locR2;
+	float sink,cosk;
+	u16 i;
+
+	if(set_bit_ptr_struct(args->io.bl_in,&log->stan_bl))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.bl_k_in,&log->Bl_K))
+		return -1;
+
+	if(set_float_ptr(args->io.i1_orta_float_in,&log->I1_orta))
+		return -1;
+	if(set_float_ptr(args->io.i1_ortb_float_in,&log->I1_ortb))
+		return -1;
+	if(set_float_ptr(args->io.i1_float_in,&log->I1))
+		return -1;
+	if(set_float_ptr(args->io.i2_orta_float_in,&log->I2_orta))
+		return -1;
+	if(set_float_ptr(args->io.i2_ortb_float_in,&log->I2_ortb))
+		return -1;
+	if(set_float_ptr(args->io.i2_float_in,&log->I2))
+		return -1;
+	if(set_float_ptr(args->io.i3_orta_float_in,&log->I3_orta))
+		return -1;
+	if(set_float_ptr(args->io.i3_ortb_float_in,&log->I3_ortb))
+		return -1;
+	if(set_float_ptr(args->io.i3_float_in,&log->I3))
+		return -1;
+
+	if(set_float_ptr(args->io.u1_orta_float_in,&log->U1_orta))
+		return -1;
+	if(set_float_ptr(args->io.u1_ortb_float_in,&log->U1_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u1_float_in,&log->U1))
+		return -1;
+	if(set_float_ptr(args->io.u2_orta_float_in,&log->U2_orta))
+		return -1;
+	if(set_float_ptr(args->io.u2_ortb_float_in,&log->U2_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u2_float_in,&log->U2))
+		return -1;
+	if(set_float_ptr(args->io.u3_orta_float_in,&log->U3_orta))
+		return -1;
+	if(set_float_ptr(args->io.u3_ortb_float_in,&log->U3_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u3_float_in,&log->U3))
+		return -1;
+
+	if(set_float_ptr(args->io.u12_orta_float_in,&log->U12_orta))
+		return -1;
+	if(set_float_ptr(args->io.u12_ortb_float_in,&log->U12_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u12_float_in,&log->U12))
+		return -1;
+	if(set_float_ptr(args->io.u23_orta_float_in,&log->U23_orta))
+		return -1;
+	if(set_float_ptr(args->io.u23_ortb_float_in,&log->U23_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u23_float_in,&log->U23))
+		return -1;
+	if(set_float_ptr(args->io.u31_orta_float_in,&log->U31_orta))
+		return -1;
+	if(set_float_ptr(args->io.u31_ortb_float_in,&log->U31_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u31_float_in,&log->U31))
+		return -1;
+
+	if(set_float_ptr(args->io.i1_zg_orta_float_in,&log->sI1_orta))
+		return -1;
+	if(set_float_ptr(args->io.i1_zg_ortb_float_in,&log->sI1_ortb))
+		return -1;
+	if(set_float_ptr(args->io.i1_zg_float_in,&log->sI1))
+		return -1;
+
+	if(set_float_ptr(args->io.i2_pr_orta_float_in,&log->sI2_orta))
+		return -1;
+	if(set_float_ptr(args->io.i2_pr_ortb_float_in,&log->sI2_ortb))
+		return -1;
+	if(set_float_ptr(args->io.i2_pr_float_in,&log->sI2))
+		return -1;
+
+	if(set_float_ptr(args->io.io_orta_float_in,&log->sI0_orta))
+		return -1;
+	if(set_float_ptr(args->io.io_ortb_float_in,&log->sI0_ortb))
+		return -1;
+	if(set_float_ptr(args->io.io_float_in,&log->sI0))
+		return -1;
+
+	if(set_float_ptr(args->io.u1_zg_orta_float_in,&log->sU1_orta))
+		return -1;
+	if(set_float_ptr(args->io.u1_zg_ortb_float_in,&log->sU1_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u1_zg_float_in,&log->sU1))
+		return -1;
+
+	if(set_float_ptr(args->io.u2_pr_orta_float_in,&log->sU2_orta))
+		return -1;
+	if(set_float_ptr(args->io.u2_pr_ortb_float_in,&log->sU2_ortb))
+		return -1;
+	if(set_float_ptr(args->io.u2_pr_float_in,&log->sU2))
+		return -1;
+
+	if(set_float_ptr(args->io.uo_orta_float_in,&log->sU0_orta))
+		return -1;
+	if(set_float_ptr(args->io.uo_ortb_float_in,&log->sU0_ortb))
+		return -1;
+	if(set_float_ptr(args->io.uo_float_in,&log->sU0))
+		return -1;
+
+	if(set_pointer_in_ptr(args->io.i_param_an_ptr_in,(u32 *)&log->param_I))
+		return -1;
+
+	if(set_pointer_in_ptr(args->io.u_param_an_ptr_in,(u32 *)&log->param_U))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.test_in,&log->test))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.deakt_in,&log->deakt))
+		return -1;
+
+	//kompensacja pradu linii rownoleglej
+	if(set_float_ptr(args->io.i_rown_orta_float_in,&log->I_row_orta))
+		return -1;
+	if(set_float_ptr(args->io.i_rown_ortb_float_in,&log->I_row_ortb))
+		return -1;
+	if(set_pointer_in_ptr(args->io.i_rown_an_ptr_in,(u32 *)&log->param_I_rown))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.wyl_in,&log->wyl))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P1W_L1E_out,&log->P1W_L1E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1W_L2E_out,&log->P1W_L2E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1W_L3E_out,&log->P1W_L3E))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P1W_L1L2_out,&log->P1W_L1L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1W_L2L3_out,&log->P1W_L2L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1W_L3L1_out,&log->P1W_L3L1))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P1_L1E_out,&log->P1_L1E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1_L2E_out,&log->P1_L2E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1_L3E_out,&log->P1_L3E))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P1_L1L2_out,&log->P1_L1L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1_L2L3_out,&log->P1_L2L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1_L3L1_out,&log->P1_L3L1))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P2_L1E_out,&log->P2_L1E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P2_L2E_out,&log->P2_L2E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P2_L3E_out,&log->P2_L3E))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P2_L1L2_out,&log->P2_L1L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P2_L2L3_out,&log->P2_L2L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P2_L3L1_out,&log->P2_L3L1))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P3_L1E_out,&log->P3_L1E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P3_L2E_out,&log->P3_L2E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P3_L3E_out,&log->P3_L3E))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P3_L1L2_out,&log->P3_L1L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P3_L2L3_out,&log->P3_L2L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P3_L3L1_out,&log->P3_L3L1))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P4_L1E_out,&log->P4_L1E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P4_L2E_out,&log->P4_L2E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P4_L3E_out,&log->P4_L3E))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P4_L1L2_out,&log->P4_L1L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P4_L2L3_out,&log->P4_L2L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P4_L3L1_out,&log->P4_L3L1))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P5_L1E_out,&log->P5_L1E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P5_L2E_out,&log->P5_L2E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P5_L3E_out,&log->P5_L3E))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P5_L1L2_out,&log->P5_L1L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P5_L2L3_out,&log->P5_L2L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P5_L3L1_out,&log->P5_L3L1))
+		return -1;
+
+	if(set_pointer_out_ptr(args->io.wy_ptr_out,(u32 *)&log->nast_.wyjscie))
+		return -1;
+
+	//debug
+	if(set_float_ptr(args->io.z1_float_out,&log->z[0]))
+		return -1;
+	if(set_float_ptr(args->io.z2_float_out,&log->z[1]))
+		return -1;
+	if(set_float_ptr(args->io.z3_float_out,&log->z[2]))
+		return -1;
+	if(set_float_ptr(args->io.z4_float_out,&log->z[3]))
+		return -1;
+	if(set_float_ptr(args->io.z5_float_out,&log->z[4]))
+		return -1;
+	if(set_float_ptr(args->io.z6_float_out,&log->z[5]))
+		return -1;
+
+	log->nast_.on_ = (args->params.bity & 0x0001)?1:0;
+	log->nast_.bl_ = (args->params.bity & 0x0002)?1:0;
+	log->nast_.Bl_L[1] = (args->params.bity & 0x0004)?1:0;
+	log->nast_.Bl_L[2] = (args->params.bity & 0x0008)?1:0;
+	log->nast_.Bl_L[3] = (args->params.bity & 0x0010)?1:0;
+	log->nast_.Bl_L[4] = (args->params.bity & 0x0020)?1:0;
+	log->nast_.Bl_L[5] = (args->params.bity & 0x0040)?1:0;
+	log->nast_.Bl_L[0] =  (args->params.bity & 0x0080)?1:0;
+
+	log->nast_.z6_kolo = (args->params.bity & 0x0100)?1:0;
+
+#define ZDISTA_POPRAWKA_1	(1) //(args->params.bity & 0x0200) // 150% imp
+#define ZDISTA_POPRAWKA_2	(0) //(args->params.bity & 0x0400) // PUSTY
+#define ZDISTA_POPRAWKA_3	(1) //(args->params.bity & 0x0800) // Michala P.
+#define ZDISTA_POPRAWKA_4	(0) //(args->params.bity & 0x1000) // Radka
+#define ZDISTA_POPRAWKA_5	(1) //(args->params.bity & 0x2000) // 150% imp miedzyfazowych - blokuj mfazowe petle
+#define ZDISTA_POPRAWKA_6	(0) //(args->params.bity & 0x4000) // 150% imp miedzyfazowych - blokuj fazowe petle
+#define ZDISTA_POPRAWKA_7	(0) //(args->params.bity & 0x8000) // KJ rodzaj zwarcia + energia
+#define ZDISTA_POPRAWKA_4C	(0) //(args->params.bity & 0x10000) // 4C Radka
+#define ZDISTA_POPRAWKA_8	(1) //(args->params.bity & 0x20000) // filtr wylacznikowy
+
+	//wyliczenie przekladni impedancyjnej
+	log->nast_.wyjscie.przekladnia = log->param_I->znam_wtor / log->param_U->znam_wtor;
+	log->nast_.wyjscie.Zdist_dw = &log->dw;
+	log->nast_.wyjscie.on = &log->nast_.on_;
+
+	//wyliczenie wektorow kompensacji ziemnozwarciowej
+	log->nast_.ReK1 = 3 * args->params.Kk1 * cos(RnaS * -args->params.Kk1_kat);
+	log->nast_.ImK1 = 3 * args->params.Kk1 * sin(RnaS * -args->params.Kk1_kat);
+	log->nast_.ReKr = 3 * args->params.KkC * cos(RnaS * -args->params.KkC_kat);
+	log->nast_.ImKr = 3 * args->params.KkC * sin(RnaS * -args->params.KkC_kat);
+
+	log->nast_.kp = args->params.kp;
+	log->nast_.kpp = 1/args->params.kp;
+	log->nast_.kpk = log->nast_.kpp * log->nast_.kpp;
+
+	log->nast_.kp_obc = args->params.kp_obc;
+	log->nast_.kpp_obc = 1 / log->nast_.kp_obc;
+
+	log->nast_.typ[0] = args->params.Typ0;
+	log->nast_.typ[1] = args->params.Typ1;
+	log->nast_.typ[2] = args->params.Typ2;
+	log->nast_.typ[3] = args->params.Typ3;
+	log->nast_.typ[4] = args->params.Typ4;
+	log->nast_.typ[5] = args->params.Typ5;
+
+	sink = sin(RnaS * args->params.fi1);
+	cosk = cos(RnaS * args->params.fi1);
+
+	log->nast_.tanfi2 = tan(RnaS * args->params.fi2);
+	log->nast_.tanfi1 = tan(RnaS * args->params.fi1);
+
+
+	struct nast_pomoc n_pomoc;
+
+	n_pomoc.R1W_Zf1W_LE = (float)args->params.R1W_Zf1W_LE;
+	n_pomoc.R1W_Zf1W_LL = (float)args->params.R1W_Zf1W_LL;
+	n_pomoc.R1_Zf1_LE = (float)args->params.R1_Zf1_LE;
+	n_pomoc.R1_Zf1_LL = (float)args->params.R1_Zf1_LL;
+	n_pomoc.R2_Zf2_LE = (float)args->params.R2_Zf2_LE;
+	n_pomoc.R2_Zf2_LL = (float)args->params.R2_Zf2_LL;
+	n_pomoc.R3_Zf3_LE = (float)args->params.R3_Zf3_LE;
+	n_pomoc.R3_Zf3_LL = (float)args->params.R3_Zf3_LL;
+	n_pomoc.R4_Zf4_LE = (float)args->params.R4_Zf4_LE;
+	n_pomoc.R4_Zf4_LL = (float)args->params.R4_Zf4_LL;
+	n_pomoc.R5_Zf5_LE = (float)args->params.R5_Zf5_LE;
+	n_pomoc.R5_Zf5_LL = (float)args->params.R5_Zf5_LL;
+	n_pomoc.X1W_Zr1W_LE = (float)args->params.X1W_Zr1W_LE;
+	n_pomoc.X1W_Zr1W_LL = (float)args->params.X1W_Zr1W_LL;
+	n_pomoc.X1_Zr1_LE = (float)args->params.X1_Zr1_LE;
+	n_pomoc.X1_Zr1_LL = (float)args->params.X1_Zr1_LL;
+	n_pomoc.X2_Zr2_LE = (float)args->params.X2_Zr2_LE;
+	n_pomoc.X2_Zr2_LL = (float)args->params.X2_Zr2_LL;
+	n_pomoc.X3_Zr3_LE = (float)args->params.X3_Zr3_LE;
+	n_pomoc.X3_Zr3_LL = (float)args->params.X3_Zr3_LL;
+	n_pomoc.X4_Zr4_LE = (float)args->params.X4_Zr4_LE;
+	n_pomoc.X4_Zr4_LL = (float)args->params.X4_Zr4_LL;
+	n_pomoc.X5_Zr5_LE = (float)args->params.X5_Zr5_LE;
+	n_pomoc.X5_Zr5_LL = (float)args->params.X5_Zr5_LL;
+
+
+	 //Impedancja konca pierwszej strefy
+	    //dopisalem 28.01.2026 KI0/I2
+	    M = _rcpsp((1+log->nast_.ImK1)* (1+log->nast_.ImK1) + (log->nast_.ReK1 * log->nast_.ReK1));
+	    KI0_I2_Re  = - log->nast_.ImK1 * M;
+	    KI0_I2_Im  = (1+log->nast_.ReK1) * M;
+	    KI0_I2 = sqrtf((KI0_I2_Re*KI0_I2_Re) + (KI0_I2_Im*KI0_I2_Im));
+
+	    float A,B;
+	    A = 1.0f + 3.0f * log->nast_.ReK1;
+	    B =  3.0f * log->nast_.ImK1;
+	    KI0_I2 = _rcpsp(sqrtf((A*A) + (B*B)));
+
+	    if(args->params.K0 <= 1)
+	    {
+	    	log->dw.modul_zf[0] = ((args->params.R1W_Zf1W_LE * args->params.R1W_Zf1W_LE) + (args->params.X1W_Zr1W_LE * args->params.X1W_Zr1W_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    	log->dw.modul_zmf[0] = ((args->params.R1W_Zf1W_LL * args->params.R1W_Zf1W_LL) + (args->params.X1W_Zr1W_LL * args->params.X1W_Zr1W_LL))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    }
+	    else
+	    {
+	    	log->dw.modul_zf[0]=9999.9f;
+	        log->dw.modul_zmf[0]=9999.9f;
+	    }
+
+	    if(args->params.K1 <= 1)
+	    {
+	    	log->dw.modul_zf[1] = ((args->params.R1_Zf1_LE * args->params.R1_Zf1_LE) + (args->params.X1_Zr1_LE * args->params.X1_Zr1_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    	log->dw.modul_zmf[1] = ((args->params.R1_Zf1_LL * args->params.R1_Zf1_LL) + (args->params.X1_Zr1_LL * args->params.X1_Zr1_LL))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    }
+	    else
+	    {
+	    	log->dw.modul_zf[1]=9999.9f;
+	        log->dw.modul_zmf[1]=9999.9f;
+	    }
+
+	    if(args->params.K2 <= 1)
+	    {
+	    	log->dw.modul_zf[2] = ((args->params.R2_Zf2_LE * args->params.R2_Zf2_LE) + (args->params.X2_Zr2_LE * args->params.X2_Zr2_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    	log->dw.modul_zmf[2] = ((args->params.R2_Zf2_LL * args->params.R2_Zf2_LL) + (args->params.X2_Zr2_LL * args->params.X2_Zr2_LL))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    }
+	    else
+	    {
+	    	log->dw.modul_zf[2]=9999.9f;
+	        log->dw.modul_zmf[2]=9999.9f;
+	    }
+
+	    if(args->params.K3 <= 1)
+	    {
+	    	log->dw.modul_zf[3] = ((args->params.R3_Zf3_LE * args->params.R3_Zf3_LE) + (args->params.X3_Zr3_LE * args->params.X3_Zr3_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    	log->dw.modul_zmf[3] = ((args->params.R3_Zf3_LL * args->params.R3_Zf3_LL) + (args->params.X3_Zr3_LL * args->params.X3_Zr3_LL))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    }
+	    else
+	    {
+	    	log->dw.modul_zf[3]=9999.9f;
+	        log->dw.modul_zmf[3]=9999.9f;
+	    }
+
+	    if(args->params.K4 <= 1)
+	    {
+	    	log->dw.modul_zf[4] = ((args->params.R4_Zf4_LE * args->params.R4_Zf4_LE) + (args->params.X4_Zr4_LE * args->params.X4_Zr4_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    	log->dw.modul_zmf[4] = ((args->params.R4_Zf4_LL * args->params.R4_Zf4_LL) + (args->params.X4_Zr4_LL * args->params.X4_Zr4_LL))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    }
+	    else
+	    {
+	    	log->dw.modul_zf[4]=9999.9f;
+	        log->dw.modul_zmf[4]=9999.9f;
+	    }
+
+	    if(args->params.K5 <= 1)
+	    {
+	    	log->dw.modul_zf[5] = ((args->params.R5_Zf5_LE * args->params.R5_Zf5_LE) + (args->params.X5_Zr5_LE * args->params.X5_Zr5_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    	log->dw.modul_zmf[5] = ((args->params.R5_Zf5_LL * args->params.R5_Zf5_LL) + (args->params.X5_Zr5_LL * args->params.X5_Zr5_LL))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	    }
+	    else
+	    {
+	    	log->dw.modul_zf[5]=9999.9f;
+	        log->dw.modul_zmf[5]=9999.9f;
+	    }
+
+	    log->dw.Z_min=9999.9f;
+	    log->dw.Z_min_mf=9999.9f;
+
+//	    Z_Z1min_old   = ((args->params.R1_Zf1_LE * args->params.R1_Zf1_LE) + (args->params.X1_Zr1_LE * args->params.X1_Zr1_LE))* (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	//    Zmf_Z1min_old = ((args->params.R1_Zf1_LL * args->params.R1_Zf1_LL) + (args->params.X1_Zr1_LL * args->params.X1_Zr1_LL)) * (log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia) *(0.15f*0.15f) ;
+	//----------------------------------------------------------------------------------------------
+
+
+	for (i=0;i<12;i++)
+	{
+		if (log->nast_.typ[i/2])
+		{
+			log->nast_.n_pol[i/2][i%2].Z = (*(float*)(&n_pomoc.R1W_Zf1W_LE + i) + *(float*)(&n_pomoc.X1W_Zr1W_LE + i)) * log->nast_.wyjscie.przekladnia / 2;
+			log->nast_.n_pol[i/2][i%2].Zp = log->nast_.n_pol[i/2][i%2].Z * args->params.kp;
+			log->nast_.n_pol[i/2][i%2].Z *= log->nast_.n_pol[i/2][i%2].Z;
+			log->nast_.n_pol[i/2][i%2].Zp *= log->nast_.n_pol[i/2][i%2].Zp;
+			locR1 = *(float*)(&n_pomoc.R1W_Zf1W_LE + i) * cosk;
+			locR2 = *(float*)(&n_pomoc.X1W_Zr1W_LE + i) * cosk;
+			locX1 = *(float*)(&n_pomoc.R1W_Zf1W_LE + i) * sink;
+			locX2 = *(float*)(&n_pomoc.X1W_Zr1W_LE + i) * sink;
+			log->nast_.n_pol[i/2][i%2].Rr = (locR1 - (locR1 + locR2 ) / 2) * log->nast_.wyjscie.przekladnia;
+			log->nast_.n_pol[i/2][i%2].Xr = (locX1 - (locX1 + locX2 ) / 2) * log->nast_.wyjscie.przekladnia;
+			locR1 = *(float*)(&n_pomoc.R1W_Zf1W_LE + i) * cosk * args->params.kp;
+			locR2 = *(float*)(&n_pomoc.X1W_Zr1W_LE + i) * cosk * args->params.kp;
+			locX1 = *(float*)(&n_pomoc.R1W_Zf1W_LE + i) * sink * args->params.kp;
+			locX2 = *(float*)(&n_pomoc.X1W_Zr1W_LE + i) * sink * args->params.kp;
+			log->nast_.n_pol[i/2][i%2].Rp = (locR1 - (locR1 + locR2 ) / 2) * log->nast_.wyjscie.przekladnia;
+			log->nast_.n_pol[i/2][i%2].Xp = (locX1 - (locX1 + locX2 ) / 2) * log->nast_.wyjscie.przekladnia;
+
+
+		} else {
+			log->nast_.n_pol[i/2][i%2].Rr = *(float *)(&n_pomoc.R1W_Zf1W_LE + i) * log->nast_.wyjscie.przekladnia;
+			log->nast_.n_pol[i/2][i%2].Xr = *(float *)(&n_pomoc.X1W_Zr1W_LE + i) * log->nast_.wyjscie.przekladnia;
+			log->nast_.n_pol[i/2][i%2].Rp = log->nast_.n_pol[i/2][i%2].Rr * args->params.kp;
+			log->nast_.n_pol[i/2][i%2].Xp = log->nast_.n_pol[i/2][i%2].Xr * args->params.kp;
+
+			log->nast_.n_pol[i/2][i%2].Rrtanfi1 = log->nast_.n_pol[i/2][i%2].Rr * log->nast_.tanfi1;
+			log->nast_.n_pol[i/2][i%2].Rptanfi1 = log->nast_.n_pol[i/2][i%2].Rp * log->nast_.tanfi1;
+
+		}
+	}
+
+
+	log->nast_.Xr1f = args->params.X1_Zr1_LE * (1 + log->nast_.tanfi2 / log->nast_.tanfi1) * log->nast_.wyjscie.przekladnia;
+	log->nast_.Xr1fp = log->nast_.Xr1f * args->params.kp;
+	log->nast_.Xr1Wf = args->params.X1W_Zr1W_LE * (1 + log->nast_.tanfi2 / log->nast_.tanfi1) * log->nast_.wyjscie.przekladnia;
+	log->nast_.Xr1Wfp = log->nast_.Xr1Wf * args->params.kp;
+	log->nast_.Igr = args->params.I_min * args->params.I_min;
+	log->nast_.Igrp = log->nast_.Igr * log->nast_.kpk;
+
+	log->nast_.Zgr = 0.01f * log->nast_.wyjscie.przekladnia * log->nast_.wyjscie.przekladnia;
+	log->nast_.kierunek[0] = args->params.K0;
+	log->nast_.kierunek[1] = args->params.K1;
+	log->nast_.kierunek[2] = args->params.K2;
+	log->nast_.kierunek[3] = args->params.K3;
+	log->nast_.kierunek[4] = args->params.K4;
+	log->nast_.kierunek[5] = args->params.K5;
+
+//szukanie Zmin w kier przod lub w tyl
+//	for (i=0;i<6;i++)
+//	{
+//		if (log->nast_.kierunek[i]==0)||(log->nast_.kierunek[i]==1)
+//		{//kierunek do linii lub bez kier
+//			
+//		}
+//	}
+
+
+//Z_ZminPrzod = sqrtf((args->params.R1_Zf1_LE * args->params.R1_Zf1_LE) + (args->params.X1_Zr1_LE * args->params.X1_Zr1_LE))*1.25f;
+//Z_ZminTyl = sqrtf((args->params.R3_Zf3_LE * args->params.R3_Zf3_LE) + (args->params.X3_Zr3_LE * args->params.X3_Zr3_LE))*1.25f;
+	
+	
+
+//A2
+
+	log->nast_.XKR = -tan(RnaS * args->params.fi4);
+	log->nast_.XKX = -tan(RnaS * (90 - args->params.fi3));
+	log->nast_.KL = tan(RnaS * args->params.fi5);
+	log->nast_.RLf = args->params.RLf;
+	log->nast_.RLr = - args->params.RLr;
+	log->nast_.Iogr = args->params.Iomin * args->params.Iomin * 0.11111f;
+	log->nast_.khio = args->params.Iokh * args->params. Iokh * 0.11111f;
+	log->nast_.Uomin = args->params.Uomin * args->params.Uomin * 0.11111f;
+
+	log->dw.log_ptr = log;
+	log->nast_.wyjscie.SOTF_zwrotnie = 0xFF;
+
+	log->l_nieustalony = 5;
+
+	log->nast_.ReKrown = args->params.Krown * cos(RnaS * -args->params.Krown_kat);
+	log->nast_.ImKrown = args->params.Krown * sin(RnaS * -args->params.Krown_kat);
+	
+	log->nast_.Krown_ignac =  (log->param_I_rown->znam_pierw / log->param_I->znam_wtor) /(log->param_I->znam_pierw/ log->param_I->znam_wtor);
+	
+	return 0;
+}
+
+void ZDistA_komp(void *arguments, void *logic)
+{
+	struct ZDistA_komp_logic *log = (struct ZDistA_komp_logic *)logic;
+	struct ZDistA_komp_args *args = (struct ZDistA_komp_args *)arguments;
+	float KIoorta,KIoortb,Iorta,Iortb,I,Uorta,Uortb;
+	u8 wk1,wk2,wk1p,wk2p;
+	u16 i,j;
+	float local,localp,local0,local0p;
+	float local1,local1p,local2,local2p,local3,local3p;
+	float KRownorta,KRownotrb;
+
+	log->dw.I1 = *log->I1;
+	log->dw.I2 = *log->I2;
+	log->dw.I3 = *log->I3;
+	log->dw.U1 = *log->U1;
+	log->dw.U2 = *log->U2;
+	log->dw.U3 = *log->U3;
+	
+	if(log->nast_.on_ && !check_struct(&log->deakt))   // jesli zabezpieczenie aktywne
+    {
+		int wydl_po_wyl = 0;
+		
+		//poprawka
+			u8 blok_szpilki=0;
+
+			if(ZDISTA_POPRAWKA_8)
+			{
+				if(*log->U1 < (0.15f*0.15f) && *log->U2 < (0.15f*0.15f) && *log->U3 < (0.15f*0.15f))
+				{
+					blok_szpilki=1;
+					if(*log->U1 > (0.01f*0.01f) && *log->U2 > (0.01f*0.01f) && *log->U3 > (0.01f*0.01f))
+					{
+						float phi,phi1,phi2,phi3;
+						blok_szpilki=2;
+						phi1=get_phase(*log->U1_ortb,*log->U1_orta);
+						phi2=get_phase(*log->U2_ortb,*log->U2_orta);
+						phi3=get_phase(*log->U3_ortb,*log->U3_orta);
+						phi=get_phase_diff(phi1,phi2);
+						phi1=get_phase_diff(phi2,phi3);
+						if(fabs(phi)<5 && fabs(phi1)<5)
+						{
+							blok_szpilki=3;
+						}
+					}
+				}
+			}
+
+		if (check_struct(&log->wyl) != 0 /*|| blok_szpilki==3*/)
+		{
+			wydl_po_wyl = 10;//10; //zmieniono 09.02.2026
+		}
+		else
+		{
+			wydl_po_wyl = 0;
+		}
+		
+		//wyliczenie impedancji petli zwarciowych
+		//--------------------------------------------------------------------------------
+		//wyliczenie K * 3Io dla strefy pierwszej
+		KIoorta = *log->sI0_orta * log->nast_.ReK1 -
+				*log->sI0_ortb * log->nast_.ImK1;
+		KIoortb = *log->sI0_orta * log->nast_.ImK1 +
+				*log->sI0_ortb * log->nast_.ReK1;
+		
+		//wspolczynnik 
+		KRownorta = *log->I_row_orta * log->nast_.ReKrown -
+				*log->I_row_ortb * log->nast_.ImKrown;
+
+		KRownotrb = *log->I_row_orta * log->nast_.ImKrown +
+				*log->I_row_ortb * log->nast_.ReKrown;
+		
+		KRownorta *= log->nast_.Krown_ignac;
+		KRownotrb *= log->nast_.Krown_ignac;
+		
+		//petla zwarciowa L1-E strefa pierwsza
+		// I = I1 -  k * 3 Io
+		Iorta = *log->I1_orta + KIoorta - KRownorta;
+		Iortb = *log->I1_ortb + KIoortb - KRownotrb;
+
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I1 - k * 3Io)
+		log->dw.Z.R[0] = (*log->U1_orta * Iorta +
+			*log->U1_ortb * Iortb) * I;
+		log->dw.Z.X[0] = (*log->U1_orta * Iortb -
+				*log->U1_ortb * Iorta) * I;
+		log->dw.Z.Z[0] = log->dw.Z.X[0] * log->dw.Z.X[0] + log->dw.Z.R[0] * log->dw.Z.R[0];
+
+//		log->dw.Z.E[0] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L2-E strefa pierwsza
+		// I = I2 -  k * 3 Io
+		Iorta = *log->I2_orta + KIoorta- KRownorta;
+		Iortb = *log->I2_ortb + KIoortb - KRownotrb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I2 - k * 3Io)
+		log->dw.Z.R[1] = (*log->U2_orta * Iorta +
+				*log->U2_ortb * Iortb) * I;
+		log->dw.Z.X[1] = (*log->U2_orta * Iortb -
+				*log->U2_ortb * Iorta) * I;
+		log->dw.Z.Z[1] = log->dw.Z.X[1] * log->dw.Z.X[1] + log->dw.Z.R[1] * log->dw.Z.R[1];
+
+//		log->dw.Z.E[1] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L3-E strefa pierwsza
+		// I = I3 -  k * 3 Io
+		Iorta = *log->I3_orta + KIoorta- KRownorta;
+		Iortb = *log->I3_ortb + KIoortb - KRownotrb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I3 - k * 3Io)
+		log->dw.Z.R[2] = (*log->U3_orta * Iorta +
+				*log->U3_ortb * Iortb) * I;
+		log->dw.Z.X[2] = (*log->U3_orta * Iortb -
+				*log->U3_ortb * Iorta) * I;
+		log->dw.Z.Z[2] = log->dw.Z.X[2] * log->dw.Z.X[2] + log->dw.Z.R[2] * log->dw.Z.R[2];
+
+//		log->dw.Z.E[2] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//wyliczenie K * 3Io dla pozostalych stref
+		KIoorta = *log->sI0_orta * log->nast_.ReKr -
+				*log->sI0_ortb * log->nast_.ImKr;
+		KIoortb = *log->sI0_orta * log->nast_.ImKr +
+				*log->sI0_ortb * log->nast_.ReKr;
+
+		//petla zwarciowa L1-E pozostale strefy
+		// I = I1 -  k * 3 Io
+		Iorta = *log->I1_orta + KIoorta;
+		Iortb = *log->I1_ortb + KIoortb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I1 - k * 3Io)
+		log->dw.Z.R[3] = (*log->U1_orta * Iorta +
+				*log->U1_ortb * Iortb) * I;
+		log->dw.Z.X[3] = (*log->U1_orta * Iortb -
+				*log->U1_ortb * Iorta) * I;
+		log->dw.Z.Z[3] = log->dw.Z.X[3] * log->dw.Z.X[3] + log->dw.Z.R[3] * log->dw.Z.R[3];
+
+//		log->dw.Z.E[3] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L2-E pozostale strefy
+		// I = I2 -  k * 3 Io
+		Iorta = *log->I2_orta + KIoorta;
+		Iortb = *log->I2_ortb + KIoortb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I2 - k * 3Io)
+		log->dw.Z.R[4] = (*log->U2_orta * Iorta +
+				*log->U2_ortb * Iortb) * I;
+		log->dw.Z.X[4] = (*log->U2_orta * Iortb -
+				*log->U2_ortb * Iorta) * I;
+		log->dw.Z.Z[4] = log->dw.Z.X[4] * log->dw.Z.X[4] + log->dw.Z.R[4] * log->dw.Z.R[4];
+
+//		log->dw.Z.E[4] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L3-E pozostale strefy
+		// I = I3 -  k * 3 Io
+		Iorta = *log->I3_orta + KIoorta;
+		Iortb = *log->I3_ortb + KIoortb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I3 - k * 3Io)
+		log->dw.Z.R[5] = (*log->U3_orta * Iorta +
+				*log->U3_ortb * Iortb) * I;
+		log->dw.Z.X[5] = (*log->U3_orta * Iortb -
+				*log->U3_ortb * Iorta) * I;
+		log->dw.Z.Z[5] = log->dw.Z.X[5] * log->dw.Z.X[5] + log->dw.Z.R[5] * log->dw.Z.R[5];
+
+//		log->dw.Z.E[5] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L1-L2 wszystkie strefy
+		// I = I1 -  I2
+		Iorta = *log->I1_orta - *log->I2_orta;
+		Iortb = *log->I1_ortb - *log->I2_ortb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I1 - I2)
+		log->dw.Z.R[6] = (*log->U12_orta * Iorta +
+				*log->U12_ortb * Iortb) * I;
+		log->dw.Z.X[6] = (*log->U12_orta * Iortb -
+				*log->U12_ortb * Iorta) * I;
+		log->dw.Z.Z[6] = log->dw.Z.X[6] * log->dw.Z.X[6] + log->dw.Z.R[6] * log->dw.Z.R[6];
+
+//		log->dw.Z.E[6] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L2-L3 wszystkie strefy
+		// I = I2 -  I3
+		Iorta = *log->I2_orta - *log->I3_orta;
+		Iortb = *log->I2_ortb - *log->I3_ortb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I1 - I2)
+		log->dw.Z.R[7] = (*log->U23_orta * Iorta +
+				*log->U23_ortb * Iortb) * I;
+		log->dw.Z.X[7] = (*log->U23_orta * Iortb -
+				*log->U23_ortb * Iorta) * I;
+		log->dw.Z.Z[7] = log->dw.Z.X[7] * log->dw.Z.X[7] + log->dw.Z.R[7] * log->dw.Z.R[7];
+
+//		log->dw.Z.E[7] = (Iorta*Iorta) + (Iortb*Iortb);
+
+		//petla zwarciowa L3-L1 wszystkie strefy
+		// I = I3 -  I1
+		Iorta = *log->I3_orta - *log->I1_orta;
+		Iortb = *log->I3_ortb - *log->I1_ortb;
+		I = _rcpsp(Iorta * Iorta + Iortb * Iortb);
+		// Z = U / (I1 - I2)
+		log->dw.Z.R[8] = (*log->U31_orta * Iorta +
+				*log->U31_ortb * Iortb) * I;
+		log->dw.Z.X[8] = (*log->U31_orta * Iortb -
+				*log->U31_ortb * Iorta) * I;
+		log->dw.Z.Z[8] = log->dw.Z.X[8] * log->dw.Z.X[8] + log->dw.Z.R[8] * log->dw.Z.R[8];
+
+//		log->dw.Z.E[8] = (Iorta*Iorta) + (Iortb*Iortb);
+		
+		*log->z[0]=log->dw.Z.R[0] /log->nast_.wyjscie.przekladnia; // L1-E s 0 1
+		*log->z[1]=log->dw.Z.X[0] /log->nast_.wyjscie.przekladnia; // L1-E s 0 1
+
+		*log->z[2]=log->dw.Z.R[1] /log->nast_.wyjscie.przekladnia; // L2-E s 0 1
+		*log->z[3]=log->dw.Z.X[1] /log->nast_.wyjscie.przekladnia; // L2-E s 0 1
+
+		*log->z[4]=log->dw.Z.R[6] /log->nast_.wyjscie.przekladnia; //L1L2
+		*log->z[5]=log->dw.Z.X[6] /log->nast_.wyjscie.przekladnia; //L1L2
+
+		//--------------------------------------------------------------------------------
+		//Kryterium impedancji petli miedzyfazowych: musi byc mniejsze niz 1,5 najsilnieszego zwarcia jednofaz.
+
+		// wybor najmniejszej impedancji faza -zero
+		// sa wyliczane dwie: dla stref 1 i 1W oraz dla 2,3,4,5
+		float Z_L1, Z_L2, Z_L3, Z_min;
+
+		if (log->dw.Z.Z[0] < log->dw.Z.Z[3]) // petla L1-E
+			Z_L1 = log->dw.Z.Z[0];
+		else
+			Z_L1 = log->dw.Z.Z[3];
+
+		if (log->dw.Z.Z[1] < log->dw.Z.Z[4]) // petla L2-E
+			Z_L2 = log->dw.Z.Z[1];
+		else
+			Z_L2 = log->dw.Z.Z[4];
+
+		if (log->dw.Z.Z[2] < log->dw.Z.Z[5]) // petla L3-E
+			Z_L3 = log->dw.Z.Z[2];
+		else
+			Z_L3 = log->dw.Z.Z[5];
+
+		u8 faza = 1;
+		//szukanie najmniejszej impedancji
+		if ((Z_L1 <= Z_L2) && (Z_L1 <= Z_L3))
+			faza = 1;
+		else if ((Z_L2 <= Z_L1) && (Z_L2 <= Z_L3))
+			faza = 2;
+		else
+			faza = 3;
+
+		//sprawdzenie krtyerium miedzy fazowych
+		//log->dw.Z.Z[6] - L1L2
+		//log->dw.Z.Z[7] - L2L3
+		//log->dw.Z.Z[8] - L3L1
+		//szukanie najmniejszej mfazowej
+		u8 mfaza = 1;
+
+		if ((log->dw.Z.Z[6]<log->dw.Z.Z[7])&&(log->dw.Z.Z[6]<log->dw.Z.Z[8]))
+			mfaza = 1;
+		else if ((log->dw.Z.Z[7]<log->dw.Z.Z[6])&&(log->dw.Z.Z[7]<log->dw.Z.Z[8]))
+			mfaza = 2;
+		else
+			mfaza = 3;
+		
+		
+		// kryteria sa dodane do kryteriow pradowych
+		u8 zezwol_L1L2 = 1;
+		u8 zezwol_L2L3 = 1;
+		u8 zezwol_L1L3 = 1;
+
+		#define kwadrat_15 2.25f // 1,5 do kwadratu
+		float Z_Z1min;
+		Z_Z1min=log->dw.Z_min;
+//		*log->z[0]=Z_Z1min_old;
+//		*log->z[1]=Z_Z1min;
+
+		switch (faza)
+		{
+			case 1:
+				Z_min=Z_L1<Z_Z1min?Z_Z1min:Z_L1;
+
+				if ((Z_min * kwadrat_15) < log->dw.Z.Z[6]) // L1_L2
+					zezwol_L1L2 = 0;
+				if ((Z_min * kwadrat_15) < log->dw.Z.Z[8]) // L1_L3
+					zezwol_L1L3 = 0;
+				break;
+			case 2:
+				Z_min=Z_L2<Z_Z1min?Z_Z1min:Z_L2;
+
+				if ((Z_min * kwadrat_15) < log->dw.Z.Z[6]) // L1_L2
+					zezwol_L1L2 = 0;
+				if ((Z_min * kwadrat_15) < log->dw.Z.Z[7]) // L2_L3
+					zezwol_L2L3 = 0;
+				break;
+			case 3:
+				Z_min=Z_L3<Z_Z1min?Z_Z1min:Z_L3;
+
+				if ((Z_min * kwadrat_15) < log->dw.Z.Z[8]) // L1_L3
+					zezwol_L1L3 = 0;
+				if ((Z_min * kwadrat_15) < log->dw.Z.Z[7]) // L2_L3
+					zezwol_L2L3 = 0;
+				break;
+			default:
+				break;
+		}
+//		*log->z[2]=(Z_min * kwadrat_15);
+	//	*log->z[3]=log->dw.Z.Z[8];
+		//*log->z[4]=faza;
+//		*log->z[2]=Z_Z1min;
+	//	*log->z[3]=Z_L1;
+
+		u8 zezwol_mL1L2 = 1;
+		u8 zezwol_mL2L3 = 1;
+		u8 zezwol_mL1L3 = 1;
+		float Zmf_Z1min;
+		Zmf_Z1min=log->dw.Z_min_mf;
+//		*log->z[2]=Zmf_Z1min_old;
+	//	*log->z[3]=Zmf_Z1min;
+
+		if (ZDISTA_POPRAWKA_5)
+		{
+			switch (mfaza)
+			{
+				case 1:
+					Z_min=log->dw.Z.Z[6]<Zmf_Z1min?Zmf_Z1min:log->dw.Z.Z[6];
+
+					if ((Z_min * kwadrat_15) <log->dw.Z.Z[7]) //L1L2*1.5 < L2L3
+						zezwol_mL2L3 = 0;
+					if ((Z_min * kwadrat_15) <log->dw.Z.Z[8]) //L1L2*1.5 < L3L1
+						zezwol_mL1L3 = 0;
+					break;
+				case 2:
+					Z_min=log->dw.Z.Z[7]<Zmf_Z1min?Zmf_Z1min:log->dw.Z.Z[7];
+
+					if ((Z_min * kwadrat_15) <log->dw.Z.Z[6]) //L2L3*1.5 < L1L2
+						zezwol_mL1L2 = 0;
+					if ((Z_min * kwadrat_15) <log->dw.Z.Z[8]) //L2L3*1.5 < L3L1
+						zezwol_mL1L3 = 0;
+					break;
+				case 3:
+					Z_min=log->dw.Z.Z[8]<Zmf_Z1min?Zmf_Z1min:log->dw.Z.Z[8];
+
+					if ((Z_min * kwadrat_15) <log->dw.Z.Z[6]) //L3L1*1.5 < L1L2
+						zezwol_mL1L2 = 0;
+					if ((Z_min * kwadrat_15) <log->dw.Z.Z[7]) //L3L1*1.5 < L2L3
+						zezwol_mL2L3 = 0;
+					break;
+				default:
+					break;
+			}
+    	}
+
+		u8 zezwol_L1 = 1;
+		u8 zezwol_L2 = 1;
+		u8 zezwol_L3 = 1;
+
+		if (ZDISTA_POPRAWKA_6)
+		switch (mfaza)
+		{
+			case 1:
+				Z_min=log->dw.Z.Z[6]<Z_Z1min?Z_min:log->dw.Z.Z[6];
+
+				if ((Z_min * kwadrat_15) <Z_L1) //L1L2*1.5 < L1
+					zezwol_L1 = 0;
+				if ((Z_min * kwadrat_15) <Z_L2) //L1L2*1.5 < L2
+					zezwol_L2 = 0;
+				break;
+			case 2:
+				Z_min=log->dw.Z.Z[7]<Z_Z1min?Z_min:log->dw.Z.Z[7];
+
+				if ((Z_min * kwadrat_15) <Z_L2) //L2L3*1.5 < L2
+					zezwol_L2 = 0;
+				if ((Z_min * kwadrat_15) <Z_L3) //L2L3*1.5 < L3
+					zezwol_L3 = 0;
+				break;
+			case 3:
+				Z_min=log->dw.Z.Z[8]<Z_Z1min?Z_Z1min:log->dw.Z.Z[8];
+
+				if ((Z_min * kwadrat_15) <Z_L1) //L3L1*1.5 < L1
+					zezwol_L1 = 0;
+				if ((Z_min * kwadrat_15) <Z_L3) //L3L1*1.5 < L3
+					zezwol_L3 = 0;
+				break;
+			default:
+				break;
+		}
+
+		float k0,k2,kdiff,typ_zw=0,near_end=0;
+#ifdef KRYT_ENERGII
+		if(ZDISTA_POPRAWKA_7) // kryterium KJ, uwzgledniajace Energie, impedancje i K0,K2
+		{
+			float Emax,Esecond,Eratio;
+			u8 Emax_idx, Esecond_idx;
+			float Zmin,Zsecond,Zratio;
+			u8 Zmin_idx, Zsecond_idx;
+
+			float sort_tbl_z[6] = { Z_L1,Z_L2,Z_L3,log->dw.Z.Z[6],log->dw.Z.Z[7],log->dw.Z.Z[8] }; // Impedancje
+			u8 sort_num_z[6] = { 0, 1, 2, 3, 4, 5 };
+
+			float sort_tbl_e[6] = {log->dw.Z.E[0]>log->dw.Z.E[3]?log->dw.Z.E[0]:log->dw.Z.E[3],
+								 log->dw.Z.E[1]>log->dw.Z.E[4]?log->dw.Z.E[1]:log->dw.Z.E[4],
+							     log->dw.Z.E[2]>log->dw.Z.E[5]?log->dw.Z.E[2]:log->dw.Z.E[5],
+							    		 log->dw.Z.E[6],log->dw.Z.E[7],log->dw.Z.E[8]};
+
+			u8 sort_num_e[6] = { 0, 1, 2, 3, 4, 5 };
+
+
+			for(i = 0; i < 5; i++)
+			{
+				for(j = 0; j < 5 - i; j++)
+				{
+					if(sort_tbl_z[j] > sort_tbl_z[j+1])
+					{
+						float tmp = sort_tbl_z[j];
+						u8 tmp2 = sort_num_z[j];
+
+						sort_num_z[j] = sort_num_z[j+1];
+						sort_num_z[j+1] = tmp2;
+			            sort_tbl_z[j] = sort_tbl_z[j+1];
+			            sort_tbl_z[j+1] = tmp;
+			        }
+
+					if(sort_tbl_e[j] > sort_tbl_e[j+1])
+					{
+						float tmp = sort_tbl_e[j];
+						u8 tmp2 = sort_num_e[j];
+
+						sort_num_e[j] = sort_num_e[j+1];
+						sort_num_e[j+1] = tmp2;
+			            sort_tbl_e[j] = sort_tbl_e[j+1];
+			            sort_tbl_e[j+1] = tmp;
+			        }
+
+				}
+		    }
+
+			Zmin = sort_tbl_z[0];
+			Zmin_idx = sort_num_z[0];
+			Zsecond = sort_tbl_z[1];
+			Zsecond_idx = sort_num_z[1];
+
+			if((Zmin * _rcpsp(Z_Z1_2)) < 0.5f)
+				near_end=1;
+
+			Emax = sort_tbl_e[5];
+			Emax_idx = sort_num_e[5];
+			Esecond = sort_tbl_e[4];
+			Esecond_idx = sort_num_e[4];
+
+			Zratio = _rcpsp(Zsecond) * Zmin;
+			Eratio = _rcpsp(Esecond) * Emax;
+
+			if(*log->sI1<0.00001)
+				*log->sI1=0.00001f;
+			if(*log->sI2<0.00001)
+				*log->sI2=0.00001f;
+
+			k2 = _rcpsp(*log->sI1);
+			k0 = *log->sI0 * k2; // |I0|/|I1|
+			k2 *= *log->sI2;	 // |I2|/|I1|
+			kdiff = *log->sI0 * _rcpsp(*log->sI2); // |I0|/|I2|
+
+//#define K0_MIN = 0.08;
+//#define K2_MIN = 0.12;
+//#define K_SMALL = 0.03;
+//energia dla wlasciwej petli >= 0.7...0.9 maksymalnej? Kluczowa w near-end, mniej znaczaca w far-end
+//mozna dodatkowo sprobowac porownania kata impedancji? max 40..60stopni roznicy?
+//wykryć near-end można przez Z<0.15 Zlinii oraz I1>5...10*Inom
+
+
+			if(k0>(0.2f*0.2f) && /*k2<0.12 dodać? &&*/ Eratio>2.0f && (Zratio < 0.25f/* || near_end*/)) // 1ph-G... moznaby blokować Pob_G gdy Zratio duży?
+			{
+				typ_zw=1; // blokowac miedzyfazowe?
+		//		zezwol_L1L2=0;
+		//		zezwol_L2L3=0;
+		//		zezwol_L1L3=0;
+			}
+			else if(k0<0.05f && k2>0.2f && Eratio>1.85f) // L-L [brak I0 za to pojawia się I2]
+			{
+				typ_zw=2; // blokowac fazowe?
+				zezwol_L1=0;
+				zezwol_L2=0;
+				zezwol_L3=0;
+			}
+			else if(k0>0.05f && k2>0.2f &&  (Eratio>0.9f && Eratio<1.1f)) // LLG kilka petli o podobnej Energii
+			{
+				zezwol_L1=0;
+				zezwol_L2=0;
+				zezwol_L3=0;
+				typ_zw=3;
+			}
+			else if(k0<0.02 && k2<0.02/* && (Eratio>0.9f && Eratio<1.1f)*/) // LLL
+			{
+				typ_zw=4; // blokowac fazowe?
+			}
+			else
+				typ_zw=0;
+
+			*log->z[0]=k0;
+			*log->z[1]=k2;
+			*log->z[2]=Zratio;
+			*log->z[3]=Eratio;
+			*log->z[4]=typ_zw;
+			//*log->z[5]=near_end;
+		}
+#endif
+		// kryterium kata I2 U2
+		float phi1,phi2,phi;
+
+		if(ZDISTA_POPRAWKA_3||ZDISTA_POPRAWKA_4)  // poprawka Michala, a Radka bierze z niej kierunek
+		{
+
+			if( (*log->I1 < (0.1f*0.1f) && *log->U1 < (0.25f * 0.25f))
+			||(*log->I2 < (0.1f*0.1f) && *log->U2 < (0.25f * 0.25f))
+			||(*log->I3 < (0.1f*0.1f) && *log->U3 < (0.25f * 0.25f)) )
+				blokada_od_spz=2;
+			else
+				if(blokada_od_spz)
+					blokada_od_spz--;
+
+			if(*log->sI2>(0.2f*0.2f) && *log->sU2>(0.02f*0.02f) && !blokada_od_spz) //przed zmiana 09.02
+			//if(*log->sI2>(0.1f*0.1f) && *log->sU2>(0.02f*0.02f))
+			{
+				//sprawdzenie kata I2 U2
+				phi1=get_phase(*log->sI2_ortb,*log->sI2_orta);
+				phi2=get_phase(*log->sU2_ortb,*log->sU2_orta);
+
+				phi=get_phase_diff(phi1,phi2);
+//				if(phi>5.0f && phi<175.0f) Przed zmianami 09.02.2026
+				if(phi>45.0f && phi<135.0f)
+					blok_do_szyn=wydl_po_wyl?7:2;
+				else
+					if(blok_do_szyn)
+						blok_do_szyn--;
+
+//				if(phi<-5.0f && phi>-175.0f) Przed zmianami 09.02.2026
+				if(phi<-45.0f && phi>-135.0f)
+					blok_do_linii=wydl_po_wyl?7:2;
+				else
+					if(blok_do_linii)
+						blok_do_linii--;
+			}
+			else
+			{
+				if(blok_do_linii)
+					blok_do_linii--;
+				if(blok_do_szyn)
+					blok_do_szyn--;
+			}
+		}
+
+
+
+
+
+		u8 blokady_michal=0;
+		blokady_michal|=blok_do_szyn?1:0;
+		blokady_michal|=blok_do_linii?2:0;
+		blokady_michal|=blokada_od_spz?3:0;
+		//*log->z[0]=blok_szpilki;
+	/*	*log->z[1]=*log->U1;
+		*log->z[2]=*log->sI2;
+		*log->z[3]=*log->sU2;
+*/
+
+		u8 zezwol_RL1L2 = 1;
+		u8 zezwol_RL2L3 = 1;
+		u8 zezwol_RL1L3 = 1;
+
+		if(ZDISTA_POPRAWKA_4)
+		{
+		//----------------------------------------------------------------------------------
+		        // Kryterium Radka
+
+		        u8 zezwol_Radka = 0;
+		        float I0_I1;
+		        float fiI0_I2;
+
+
+		        #define KRYT_I0_I1  	0x01
+		        #define KRYT_U0        	0x02
+		        #define KRYT_katI0I2    0x04
+		        #define KRYT_zakrI0I2   0x08
+
+		        // 1. |I0/I1|>0.2
+		        if ((*log->sI1 > 0.0005f) )
+		            {
+		                //I0/I1
+		                I0_I1 = *log->sI0 * _rcpsp(*log->sI1);
+						if(I0_I1>0.04f)
+							zezwol_Radka|=KRYT_I0_I1;
+		            }
+
+		        // Kryterium Radka
+		        // 2. |U0|>U0min
+		        if((*log->sU0 > log->nast_.Uomin))
+		        	zezwol_Radka|=KRYT_U0;
+
+	        
+				float phi1,phi2;
+				// Kryterium Radka
+		        // 4. Kąt (I0-I2) |fiI0_I2|
+				phi1=get_phase(*log->sI0_ortb,*log->sI0_orta);
+				phi2=get_phase(*log->sI2_ortb,*log->sI2_orta);
+				fiI0_I2=get_phase_diff(phi1,phi2);
+				
+				phi1=fiI0_I2;
+
+		        // sprawdzenie ktora faza L ma zwarcie
+		        switch (faza)
+		        {
+					case 1:
+						break;
+					case 2:
+						fiI0_I2 = fiI0_I2 - 120;
+
+						break;
+					case 3:
+						fiI0_I2 = fiI0_I2 + 120;
+
+						break;
+					default:
+						break;
+		        }
+
+		        float zakr_I0_I2;
+		        float A,B;
+
+		        if((fiI0_I2 < 30) && (fiI0_I2 > -30))
+		        	zezwol_Radka|=KRYT_katI0I2;
+		        //sprawdzanie zakresu |I0/I2|
+		        if ((*log->sI2 > 0.0005f) )
+		            zakr_I0_I2 = *log->sI0 * _rcpsp(*log->sI2);
+
+		        //if(Z_Z1<0.9f)
+				//jak sprawdzić że impedancja Z_L1/2/3 jest w przód lub w tył
+				///???
+
+					if(1/*blok_do_szyn*/)//zwarcie w przod
+					{
+						//ponizej chyba nie pasuje do wzoru Radka ze wzgledu na czesc wartosci w kwadracie
+			        	//A=1.0f/*25f*/ - ((1-KI0_I2)/Z_Z1) * sqrtf((faza==1?Z_L1:faza==2?Z_L2:Z_L3)/(log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia)); //f(Zw)
+						//if (A>0.9f)
+						//	A=0.9f;
+						A = KI0_I2;
+						//ponizej chyba nie pasuje do wzoru Radka ze wzgledu na czesc wartosci w kwadracie
+						if((zakr_I0_I2>(A * A)) && (zakr_I0_I2<(2.5f * 2.5f)))
+							zezwol_Radka|=KRYT_zakrI0I2;
+					}
+					else if(0/*blok_do_linii*/)//zwarcie w tyl
+					{
+						//ponizej chyba nie pasuje do wzoru Radka ze wzgledu na czesc wartosci w kwadracie
+			        	//B=1.0f/*25f*/ - ((1-KI0_I2)/Z_Z1) * sqrtf((faza==1?Z_L1:faza==2?Z_L2:Z_L3)/(log->nast_.wyjscie.przekladnia*log->nast_.wyjscie.przekladnia)) *(0.4f); //f(Zwt)
+						//if (KI0_I2>B)
+						//	B=KI0_I2;
+						//if(B>1.1f)
+						//	B=1.1f;
+						B = KI0_I2;
+
+				        //w tyl
+						//ponizej chyba nie pasuje do wzoru Radka ze wzgledu na czesc wartosci w kwadracie
+				        if((zakr_I0_I2>(B * B)) && (zakr_I0_I2<(1.1f * 1.1f)))
+				        	zezwol_Radka|=KRYT_zakrI0I2;
+
+					}
+
+		        if (zezwol_Radka==(KRYT_I0_I1|KRYT_U0|KRYT_katI0I2|KRYT_zakrI0I2))
+		            {
+		            //ZWARCIE_1F_ZABLOKUJ_2F; 
+					//Blokuj i
+		                zezwol_RL1L2 =0;
+		                zezwol_RL2L3 =0;
+		                zezwol_RL1L3 =0;
+		            }
+		        //--------------------------------------------------------------------------------
+				//*log->z[0]=zezwol_Radka;
+				//*log->z[1]=I0_I1;
+				//*log->z[2]=fiI0_I2;
+				//*log->z[3]=KI0_I2;
+				//*log->z[4]=A;
+    	}
+//Kryterium Radka B
+//Blokada fałszywych zwarć doziemnych podczas poprawnego zwarcia doziemnego
+/*		float fiI0_I2;
+		if((ZDISTA_POPRAWKA_4)&&(ZDISTA_POPRAWKA_5))
+		{
+				float phi3,phi4;
+				// Kryterium Radka
+		        // 4. Kąt (I0-I2) |fiI0_I2|
+				phi3=get_phase(*log->sI0_ortb,*log->sI0_orta);
+				phi4=get_phase(*log->sI2_ortb,*log->sI2_orta);
+				fiI0_I2=get_phase_diff(phi3,phi4);
+				//sprzwdzanie BRAK aktywnych pętli zwarć międzyfazowych LL
+				//????????????
+				//czy tylko w 1 strefie, czy we wszystkich trzeba sprawdzić zwarcia LL
+				
+				
+				
+				//sprawdzenie fi
+				// dla każdej fazy
+					if (((fabs(fiI0_I2)>30) && (fabs(fiI0_I2-120)<25)) ||(fabs(fiI0_I2+120)<25))
+							zezwol_L1 =0;
+					if (((fabs(fiI0_I2-120)>30) && (fabs(fiI0_I2)<25)) ||(fabs(fiI0_I2+120)<25))
+							zezwol_L2 =0;
+					if (((fabs(fiI0_I2+120)>30) && (fabs(fiI0_I2)<25)) ||(fabs(fiI0_I2-120)<25))
+							zezwol_L3 =0;
+				
+		}
+*/
+	       u8 zezwol_RCL1 = 1;
+	       u8 zezwol_RCL2 = 1;
+	       u8 zezwol_RCL3 = 1;
+
+
+	        if(ZDISTA_POPRAWKA_4C)
+	        {
+	        //----------------------------------------------------------------------------------
+	                //Blokada fałszywych zwarć doziemnych podczas zwarcia międzyfazowego
+	                // 1. |I0/I2|<0.25
+	        		float kdiff;
+	        		kdiff = *log->sI0 * _rcpsp(*log->sI2); // |I0|/|I2|
+	        		//*log->z[5]=sqrtf(kdiff);
+
+	                if ((*log->sI0)<(0.25f*0.25f * *log->sI2))
+	                        {
+	                        //2. |U2|/|U0| > 8
+	                            if ((*log->sU2)>(*log->sU0 * 8*8))
+	                            {
+	                            //3. I2>0.3
+	                                if (*log->sI2 > (0.3f*0.3f))
+	                                {
+	                                //4.|U0|<4
+	                                    if (*log->sU0 < (0.04f*0.04f))
+	                                    {
+	                                    //5. 3I0<3I0nast *1.2
+	                                        if (*log->sI0 < (log->nast_.Iogr * 1.2f *1.2f))
+	                                        {
+	                                            //blokada pobudzen zwarc doziemnych
+	                                            zezwol_RCL1 = 0;
+	                                            zezwol_RCL2 = 0;
+	                                            zezwol_RCL3 = 0;
+	                                        }
+
+	                                    }
+	                                }
+
+	                            }
+	                        }
+	        }
+
+		//--------------------------------------------------------------------------------
+
+		//Sprawdzenie wielkosci pradow fazowych
+
+		if (log->dw.I1 > log->nast_.Igr) log->dw.Igr[0] = 1;
+		if (log->dw.I1 < log->nast_.Igrp) log->dw.Igr[0] = 0;
+
+		if (log->dw.I2 > log->nast_.Igr) log->dw.Igr[1] = 1;
+		if (log->dw.I2 < log->nast_.Igrp) log->dw.Igr[1] = 0;
+
+		if (log->dw.I3 > log->nast_.Igr) log->dw.Igr[2] = 1;
+		if (log->dw.I3 < log->nast_.Igrp) log->dw.Igr[2] = 0;
+
+		//do kryteriow pradowych dodane jest kryterium impedancji ponizej 1,5 najmniejszej
+		log->dw.Igr[3] = log->dw.Igr[0] && log->dw.Igr[1] && (!ZDISTA_POPRAWKA_1 || zezwol_L1L2) && (!ZDISTA_POPRAWKA_7 || zezwol_L1L2) && (!ZDISTA_POPRAWKA_5 || zezwol_mL1L2) &&(!ZDISTA_POPRAWKA_4|| zezwol_RL1L2);
+		log->dw.Igr[4] = log->dw.Igr[1] && log->dw.Igr[2] && (!ZDISTA_POPRAWKA_1 || zezwol_L2L3) && (!ZDISTA_POPRAWKA_7 || zezwol_L2L3) && (!ZDISTA_POPRAWKA_5 || zezwol_mL2L3) &&(!ZDISTA_POPRAWKA_4|| zezwol_RL2L3);
+		log->dw.Igr[5] = log->dw.Igr[2] && log->dw.Igr[0] && (!ZDISTA_POPRAWKA_1 || zezwol_L1L3) && (!ZDISTA_POPRAWKA_7 || zezwol_L1L3) && (!ZDISTA_POPRAWKA_5 || zezwol_mL1L3) &&(!ZDISTA_POPRAWKA_4|| zezwol_RL1L3);
+
+		//do kryteriow pradowych dodane jest kryterium impedancji mfazowej ponizej 1,5 najmniejszej
+		log->dw.Igr[0] = log->dw.Igr[0] && (!ZDISTA_POPRAWKA_6 || zezwol_L1) && (!ZDISTA_POPRAWKA_7 || zezwol_L1) && (!ZDISTA_POPRAWKA_4C || zezwol_RCL1);
+		log->dw.Igr[1] = log->dw.Igr[1] && (!ZDISTA_POPRAWKA_6 || zezwol_L2) && (!ZDISTA_POPRAWKA_7 || zezwol_L2) && (!ZDISTA_POPRAWKA_4C || zezwol_RCL2);
+		log->dw.Igr[2] = log->dw.Igr[2] && (!ZDISTA_POPRAWKA_6 || zezwol_L3) && (!ZDISTA_POPRAWKA_7 || zezwol_L3) && (!ZDISTA_POPRAWKA_4C || zezwol_RCL3);
+
+		//dodatkowe kryterium blokady po pojawieniu sie pradu
+//		if ((log->dw.I1 < 0.1) && (log->dw.I2 < 0.1) && (log->dw.I3  < 0.1))
+		if ((log->dw.I1 < 0.01) && (log->dw.I2 < 0.01) && (log->dw.I3  < 0.01))
+		{	
+			log->l_nieustalony = 5;
+		}
+		else
+		{
+			if (log->l_nieustalony > 0)
+				log->l_nieustalony--;
+		}
+
+		//identyfikacja zwarc z udzialem ziemi
+		local = log->nast_.Iogr;
+		localp = local * log->nast_.kpk;
+		wk1p = ((*log->sI0 > local)
+			&& (*log->sU0 > log->nast_.Uomin))?1:0;
+
+		wk2p = ((*log->sI0 < localp)
+			|| (*log->sU0 < log->nast_.Uomin))?1:0;
+
+
+
+		if (log->dw.I1 > log->dw.I2) local = log->dw.I1;
+					else local = log->dw.I2;
+		if (log->dw.I3 > local) local = log->dw.I3;
+
+
+		local = local * log->nast_.khio;
+		localp = local * log->nast_.kpk;
+
+
+		wk1 = (wk1p &&
+			(*log->sI0 > local))?1:0;
+		wk2 = (wk2p ||
+			(*log->sI0 < localp))?1:0;
+
+
+		sprawdz_P(
+			&log->dw.Iogr,
+			wk1,
+			wk2,
+			&log->dw.liczpIo,
+			3,3
+			);
+
+
+		// impedancyjne kryterium kierunkowe i sprawdzenie obszaru obciazenia
+
+		local = log->nast_.XKR;
+		localp = local * log->nast_.kp;
+		local0 = log->nast_.XKX;
+		local0p = local0 * log->nast_.kpp;
+
+
+
+		local1 = log->nast_.RLf * log->nast_.wyjscie.przekladnia;
+		local1p = local1 * log->nast_.kpp_obc;
+		local2 = log->nast_.RLr * log->nast_.wyjscie.przekladnia;
+		local2p = local2 * log->nast_.kpp_obc;
+		local3 = log->nast_.KL;
+		local3p = local3 * log->nast_.kp_obc;
+
+		for(i=0;i<9;i++)
+		{
+
+			wk1 = log->dw.Z.X[i] > local * log->dw.Z.R[i];
+			wk1p = log->dw.Z.X[i] < localp * log->dw.Z.R[i];
+			wk2 = log->dw.Z.X[i] > local0 * log->dw.Z.R[i];
+			wk2p = log->dw.Z.X[i] < local0p * log->dw.Z.R[i];
+
+			for (j = 0; j < 6; j++)
+			{
+				int k = 0;
+				if (i < 3 )
+					k = i;
+				else
+					k = i - 3;
+			
+			sprawdz_P( //kierunek do przodu
+				&log->dw.XKp[j][i],
+				wk1 && wk2 && log->dw.P_sss[j][k],
+				wk1p || wk2p,
+				&log->dw.liczp11[j][i],
+				7+wydl_po_wyl,
+				3
+				);
+
+
+			sprawdz_P( //kierunek do tylu
+				&log->dw.XKm[j][i],
+				!wk1 && !wk2 && log->dw.P_sss[j][k],
+				!wk1p || !wk2p,
+				&log->dw.liczp12[j][i],
+				7+wydl_po_wyl,
+				3
+				);
+			}
+
+			sprawdz_P( // blokada od pradow obciażenia
+				&log->dw.BL_Load[i],
+				(log->dw.Z.R[i] > local1 || log->dw.Z.R[i] < local2) &&
+				fabs(log->dw.Z.X[i]) <  fabs(local3 * log->dw.Z.R[i]),
+				(log->dw.Z.R[i] < local1p && log->dw.Z.R[i] > local2p) ||
+				fabs(log->dw.Z.X[i]) >  fabs(local3p * log->dw.Z.R[i]),
+				&log->dw.liczp10[i],
+				filtr_P
+				);
+
+
+		}
+
+
+		//--------------------------------------------------------------------------------
+		// identyfikacja bardzo bliskich zwarc
+		if (log->nast_.z6_kolo != 0)
+		{	
+			log->dw.Zm[0] = log->dw.Z.Z[0] < log->nast_.Zgr || log->dw.U1 < (0.01f*0.01f) ; // przed 09.02.2026 bylo 0.005f
+			log->dw.Zm[1] = log->dw.Z.Z[1] < log->nast_.Zgr || log->dw.U2 < (0.01f*0.01f) ;
+			log->dw.Zm[2] = log->dw.Z.Z[2] < log->nast_.Zgr || log->dw.U3 < (0.01f*0.01f) ;
+			log->dw.Zm[3] = log->dw.Z.Z[3] < log->nast_.Zgr || log->dw.U1 < (0.01f*0.01f) ;
+			log->dw.Zm[4] = log->dw.Z.Z[4] < log->nast_.Zgr || log->dw.U2 < (0.01f*0.01f) ;
+			log->dw.Zm[5] = log->dw.Z.Z[5] < log->nast_.Zgr || log->dw.U3 < (0.01f*0.01f) ;
+			log->dw.Zm[6] = log->dw.Z.Z[6] < log->nast_.Zgr || *log->U12 < (0.01f*0.01f) ;
+			log->dw.Zm[7] = log->dw.Z.Z[7] < log->nast_.Zgr || *log->U23 < (0.01f*0.01f) ;
+			log->dw.Zm[8] = log->dw.Z.Z[8] < log->nast_.Zgr || *log->U31 < (0.01f*0.01f) ;
+
+		}
+		else
+		{
+			log->dw.Zm[0] = 0;
+			log->dw.Zm[1] = 0;
+			log->dw.Zm[2] = 0;
+			log->dw.Zm[3] = 0;
+			log->dw.Zm[4] = 0;
+			log->dw.Zm[5] = 0;
+			log->dw.Zm[6] = 0;
+			log->dw.Zm[7] = 0;
+			log->dw.Zm[8] = 0;
+			
+		}
+
+		//--------------------------------------------------------------------------------
+		//Wyliczenie wartosci rozruchowych dla charakterystyki poligonalnej
+
+		i = 0;
+		while(i<3)
+		{
+				log->dw.Z.absR[i] = fabs(log->dw.Z.R[i]);
+				log->dw.Z.absX[i] = fabs(log->dw.Z.X[i]);
+				log->dw.Z.XRtanfi1_noabs[i] = log->dw.Z.X[i] - log->dw.Z.R[i] * log->nast_.tanfi1;
+			//	log->dw.Z.XRtanfi1[i] = fabs(log->dw.Z.XRtanfi1_noabs[i]);
+				log->dw.Z.XRtanfi2[i] = log->dw.Z.X[i] + log->dw.Z.R[i] * log->nast_.tanfi2;
+				i++;
+		}
+
+		while(i<9)
+		{
+				log->dw.Z.absR[i] = fabs(log->dw.Z.R[i]);
+				log->dw.Z.absX[i] = fabs(log->dw.Z.X[i]);
+				log->dw.Z.XRtanfi1_noabs[i] = log->dw.Z.X[i] - log->dw.Z.R[i] * log->nast_.tanfi1;
+			//	log->dw.Z.XRtanfi1[i] = fabs(log->dw.Z.XRtanfi1_noabs[i]);
+				i++;
+		}
+
+
+		//-----------------------------------------------------------------------------
+		// sprawdzenie spelnienia warunku impedancji strefy
+		//-----------------------------------------------------------------------------
+		// sprawdzenie strefy 1 zwarcia jednofazowe z ziemia strefa 1W
+		int l_powt = 5;
+		if (log->nast_.kierunek[0] == 0)
+			l_powt = 10 + wydl_po_wyl;
+		else
+			l_powt = 5 + wydl_po_wyl;
+		
+		if(log->nast_.wyjscie.SOTF_zwrotnie == 0)
+			l_powt = 5 + wydl_po_wyl;
+
+		
+		for(i=0;i<3;i++)
+		{
+			if (log->nast_.typ[0])
+			{
+				Iorta = log->dw.Z.R[i] - log->nast_.n_pol[0][0].Rr;
+				Iortb = log->dw.Z.X[i] - log->nast_.n_pol[0][0].Xr;
+				I = Iorta * Iorta + Iortb * Iortb;
+				wk1 = I < log->nast_.n_pol[0][0].Z && log->dw.Igr[i];
+				Iorta = log->dw.Z.R[i] - log->nast_.n_pol[0][0].Rp;
+				Iortb = log->dw.Z.X[i] - log->nast_.n_pol[0][0].Xp;
+				I = Iorta * Iorta + Iortb * Iortb;
+				wk2 = I > log->nast_.n_pol[0][0].Zp || !log->dw.Igr[i];
+			} else {
+				wk1 = (/*log->dw.Z.absR[i] < log->nast_.n_pol[0][0].Rr ||*/
+					   ((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] > -log->nast_.n_pol[0][0].Rrtanfi1) && (log->dw.Z.R[i] > - log->nast_.n_pol[0][0].Rr)):((log->dw.Z.XRtanfi1_noabs[i] < log->nast_.n_pol[0][0].Rrtanfi1)&&(log->dw.Z.R[i] < log->nast_.n_pol[0][0].Rr)))        ) //here
+						&& log->dw.Z.XRtanfi2[i] < log->nast_.Xr1Wf
+						&& log->dw.Igr[i]
+						&& log->dw.Z.absX[i] < log->nast_.n_pol[0][0].Xr
+						&& log->l_nieustalony == 0;
+
+				wk2 = (
+						((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] < -log->nast_.n_pol[0][0].Rptanfi1) || (log->dw.Z.R[i] < - log->nast_.n_pol[0][0].Rp)):((log->dw.Z.XRtanfi1_noabs[i] > log->nast_.n_pol[0][0].Rptanfi1)||(log->dw.Z.R[i] > log->nast_.n_pol[0][0].Rp)))
+						/*&& log->dw.Z.absR[i] > log->nast_.n_pol[0][0].Rp*/)
+						|| !log->dw.Igr[i]
+						|| log->dw.Z.XRtanfi2[i] > log->nast_.Xr1Wfp
+						|| log->dw.Z.absX[i] > log->nast_.n_pol[0][0].Xp
+						|| log->l_nieustalony != 0;
+			}
+			sprawdz_P(
+				&log->dw.P_s[0][i],
+				wk1,
+				wk2,
+				&log->dw.liczps[0][i],
+				l_powt, 5
+				);
+			log->dw.Pbk[0][i] = log->dw.P_s[0][i] && log->dw.Iogr && !(log->nast_.Bl_L[0] && log->dw.BL_Load[i]); // uwzglednienie blokady od pradow obciażenia oraz kryterium zwarc z udzialem ziemi
+			log->dw.P_sss[0][i]= wk1;
+		}
+
+		// sprawdzenie strefy 1 zwarcia jednofazowe z ziemia strefa 1
+		if (log->nast_.kierunek[1] == 0)
+			l_powt = 10 + wydl_po_wyl;
+		else
+			l_powt = 5 + wydl_po_wyl;
+	
+		if (log->nast_.wyjscie.SOTF_zwrotnie == 1)
+			l_powt = 5 + wydl_po_wyl;
+			
+		for(i=0;i<3;i++)
+		{
+			if (log->nast_.typ[1])
+			{
+				Iorta = log->dw.Z.R[i] - log->nast_.n_pol[1][0].Rr;
+				Iortb = log->dw.Z.X[i] - log->nast_.n_pol[1][0].Xr;
+				I = Iorta * Iorta + Iortb * Iortb;
+				wk1 = I < log->nast_.n_pol[1][0].Z && log->dw.Igr[i];
+				Iorta = log->dw.Z.R[i] - log->nast_.n_pol[1][0].Rp;
+				Iortb = log->dw.Z.X[i] - log->nast_.n_pol[1][0].Xp;
+				I = Iorta * Iorta + Iortb * Iortb;
+				wk2 = I > log->nast_.n_pol[1][0].Zp || !log->dw.Igr[i];
+			} else {
+				wk1 =   (((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] > -log->nast_.n_pol[1][0].Rrtanfi1) && (log->dw.Z.R[i] > - log->nast_.n_pol[1][0].Rr)):((log->dw.Z.XRtanfi1_noabs[i] < log->nast_.n_pol[1][0].Rrtanfi1)&&(log->dw.Z.R[i] < log->nast_.n_pol[1][0].Rr)))        )
+
+//						(log->dw.Z.absR[i] < log->nast_.n_pol[1][0].Rr || log->dw.Z.XRtanfi1[i] < log->nast_.n_pol[1][0].Rrtanfi1)
+						&& log->dw.Z.XRtanfi2[i] < log->nast_.Xr1f
+						&& log->dw.Igr[i]
+						&& log->dw.Z.absX[i] < log->nast_.n_pol[1][0].Xr
+						&& log->l_nieustalony == 0;
+				wk2 =	((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] < -log->nast_.n_pol[1][0].Rptanfi1) || (log->dw.Z.R[i] < - log->nast_.n_pol[1][0].Rp)):((log->dw.Z.XRtanfi1_noabs[i] > log->nast_.n_pol[1][0].Rptanfi1)||(log->dw.Z.R[i] > log->nast_.n_pol[1][0].Rp)))
+
+						//(log->dw.Z.absR[i] > log->nast_.n_pol[1][0].Rp && log->dw.Z.XRtanfi1[i] > log->nast_.n_pol[1][0].Rptanfi1)
+						|| log->dw.Z.XRtanfi2[i] > log->nast_.Xr1fp
+						|| !log->dw.Igr[i]
+						|| log->dw.Z.absX[i] > log->nast_.n_pol[1][0].Xp
+						|| log->l_nieustalony != 0;
+			}
+			sprawdz_P(
+				&log->dw.P_s[1][i],
+				wk1,
+				wk2,
+				&log->dw.liczps[1][i],
+				l_powt, 5
+				);
+			log->dw.Pbk[1][i] = log->dw.P_s[1][i] && log->dw.Iogr && !(log->nast_.Bl_L[1] && log->dw.BL_Load[i]); // uwzglednienie blokady od pradow obciażenia oraz kryterium zwarc z udzialem ziemi
+			log->dw.P_sss[1][i]= wk1;
+		}
+
+
+		//sprawdzenie pozostalych stref zwarcie jednofazowe z ziemia
+		for(j=2;j<6;j++)
+		{
+			if (log->nast_.kierunek[j] == 0)
+				l_powt = 10 + wydl_po_wyl;
+			else
+				l_powt = 5 + wydl_po_wyl;
+			
+			if  (log->nast_.wyjscie.SOTF_zwrotnie == j)
+				l_powt = 5 + wydl_po_wyl;
+
+			for(i=3;i<6;i++)
+			{
+				if (log->nast_.typ[j])
+				{
+					Iorta = log->dw.Z.R[i] - log->nast_.n_pol[j][0].Rr;
+					Iortb = log->dw.Z.X[i] - log->nast_.n_pol[j][0].Xr;
+					I = Iorta * Iorta + Iortb * Iortb;
+					wk1 = I < log->nast_.n_pol[j][0].Z  && log->dw.Igr[i-3];
+					Iorta = log->dw.Z.R[i] - log->nast_.n_pol[j][0].Rp;
+					Iortb = log->dw.Z.X[i] - log->nast_.n_pol[j][0].Xp;
+					I = Iorta * Iorta + Iortb * Iortb;
+					wk2 = I > log->nast_.n_pol[j][0].Zp || !log->dw.Igr[i-3];
+				} else {
+					wk1 = //(log->dw.Z.absR[i] < log->nast_.n_pol[j][0].Rr || log->dw.Z.XRtanfi1[i] < log->nast_.n_pol[j][0].Rrtanfi1)
+						(((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] > -log->nast_.n_pol[j][0].Rrtanfi1) && (log->dw.Z.R[i] > - log->nast_.n_pol[j][0].Rr)):((log->dw.Z.XRtanfi1_noabs[i] < log->nast_.n_pol[j][0].Rrtanfi1)&&(log->dw.Z.R[i] < log->nast_.n_pol[j][0].Rr)))        )
+
+							&& log->dw.Igr[i-3]
+							&& log->dw.Z.absX[i] < log->nast_.n_pol[j][0].Xr
+							&& log->l_nieustalony == 0;
+					wk2 =// (log->dw.Z.absR[i] > log->nast_.n_pol[j][0].Rp && log->dw.Z.XRtanfi1[i] > log->nast_.n_pol[j][0].Rptanfi1)
+							((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] < -log->nast_.n_pol[j][0].Rptanfi1) || (log->dw.Z.R[i] < - log->nast_.n_pol[j][0].Rp)):((log->dw.Z.XRtanfi1_noabs[i] > log->nast_.n_pol[j][0].Rptanfi1)||(log->dw.Z.R[i] > log->nast_.n_pol[j][0].Rp)))
+
+							|| !log->dw.Igr[i-3]
+							|| log->dw.Z.absX[i] > log->nast_.n_pol[j][0].Xp
+							|| log->l_nieustalony != 0;
+				}
+				sprawdz_P(
+					&log->dw.P_s[j][i-3],
+					wk1,
+					wk2,
+					&log->dw.liczps[j][i-3],
+					l_powt, 5
+					);
+
+				log->dw.Pbk[j][i-3] = log->dw.P_s[j][i-3] && log->dw.Iogr && !(log->nast_.Bl_L[j] && log->dw.BL_Load[i]); // uwzglednienie blokady od pradow obciażenia oraz kryterium zwarc z udzialem ziemi
+				log->dw.P_sss[j][i-3]= wk1;
+			}
+
+		}
+
+		//sprawdzenie petli miedzyfazowych
+		for(j=0;j<6;j++)
+		{
+			if (log->nast_.kierunek[j] == 0)
+				l_powt = 10 + wydl_po_wyl;
+			else
+				l_powt = 5 + wydl_po_wyl;
+			
+			if  (log->nast_.wyjscie.SOTF_zwrotnie == j)
+				l_powt = 5 + wydl_po_wyl;
+			
+			for(i=6;i<9;i++)
+			{
+				if (log->nast_.typ[j])
+				{
+					Iorta = log->dw.Z.R[i] - log->nast_.n_pol[j][1].Rr;
+					Iortb = log->dw.Z.X[i] - log->nast_.n_pol[j][1].Xr;
+					I = Iorta * Iorta + Iortb * Iortb;
+					wk1 = (I < log->nast_.n_pol[j][1].Z && log->dw.Igr[i-3])?1:0;
+					Iorta = log->dw.Z.R[i] - log->nast_.n_pol[j][1].Rp;
+					Iortb = log->dw.Z.X[i] - log->nast_.n_pol[j][1].Xp;
+					I = Iorta * Iorta + Iortb * Iortb;
+					wk2 = (I > log->nast_.n_pol[j][1].Zp  || !log->dw.Igr[i-3])?1:0;
+				} else {
+						wk1 = //(log->dw.Z.absR[i] < log->nast_.n_pol[j][1].Rr || log->dw.Z.XRtanfi1[i] < log->nast_.n_pol[j][1].Rrtanfi1)
+								(  ((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] > -log->nast_.n_pol[j][1].Rrtanfi1) && (log->dw.Z.R[i] > - log->nast_.n_pol[j][1].Rr)):((log->dw.Z.XRtanfi1_noabs[i] < log->nast_.n_pol[j][1].Rrtanfi1)&&(log->dw.Z.R[i] < log->nast_.n_pol[j][1].Rr)))        )
+								&& log->dw.Igr[i-3]
+								&& log->dw.Z.absX[i] < log->nast_.n_pol[j][1].Xr
+								&& log->l_nieustalony == 0;
+						wk2 = //(log->dw.Z.absR[i] > log->nast_.n_pol[j][1].Rp  && log->dw.Z.XRtanfi1[i] > log->nast_.n_pol[j][1].Rptanfi1)
+								((log->dw.Z.X[i]>=0.0f)?((log->dw.Z.XRtanfi1_noabs[i] < -log->nast_.n_pol[j][1].Rptanfi1) || (log->dw.Z.R[i] < - log->nast_.n_pol[j][1].Rp)):((log->dw.Z.XRtanfi1_noabs[i] > log->nast_.n_pol[j][1].Rptanfi1)||(log->dw.Z.R[i] > log->nast_.n_pol[j][1].Rp)))
+
+								|| !log->dw.Igr[i-3]
+								|| log->dw.Z.absX[i] > log->nast_.n_pol[j][1].Xp
+								|| log->l_nieustalony != 0;
+				}
+				sprawdz_P(
+					&log->dw.P_s[j][i-3],
+					wk1,
+					wk2,
+					&log->dw.liczps[j][i-3],
+					l_powt, 5
+					);
+				log->dw.Pbk[j][i-3] = log->dw.P_s[j][i-3] && !(log->nast_.Bl_L[j] && log->dw.BL_Load[i]); // uwzglednienie blokady od pradow obciażenia oraz minimalnej wartosci pradu
+				log->dw.P_sss[j][i-3]= wk1;
+			}
+		}
+
+
+		//-----------------------------------------------------------------------------
+		// sprawdzenie dodatkowego kryterium kierunkowego
+
+//		*log->z[1]=0;
+		if (*log->sU1 < (0.05*0.05f) && *log->sU2 > 0.002f) // ok 4V // dodano zeby jednak uzywac skladowej przeciwnej gdy brak zgodnej (zalaczenie linii)
+		{
+//*log->z[1]=1;
+			// kryterium skladowych przeciwnych
+			//przesuniecia skladowych napiecia o 45 stopni
+			if (*log->sI2 > 0.0003f)
+			{
+//*log->z[1]=2;
+				Uorta = (*log->sU2_orta - *log->sU2_ortb) * 0.7071f; //
+				Uortb = (*log->sU2_orta + *log->sU2_ortb) * 0.7071f;
+				I = *log->sI2_orta * Uorta +
+					*log->sI2_ortb * Uortb;
+	
+				wk1 = I < 0;
+				sprawdz_P (
+					&log->dw.Kp,
+					wk1,
+					!wk1,
+					&log->dw.liczKdod,
+					3,3
+					);
+				log->dw.Km = !log->dw.Kp;
+			} else {
+				log->dw.Km = log->dw.Kp = 0;
+			}
+		} else {
+			// kryterium skladowych zgodnych
+			//przesuniecia skladowych napiecia o 45 stopni
+//*log->z[1]=3;
+
+			if ((*log->sI1 > 0.0001f) &&//przed poprawka 09.02.2026
+			//if ((*log->sI1 > (0.001f*0.001f)) &&
+					(*log->sU1 > 0.00001f) /*&& !blok_szpilki *//*&& !wydl_po_wyl*/)
+			{
+//*log->z[1]=4;
+				Uorta = (*log->sU1_orta - *log->sU1_ortb) * 0.7071f; //
+				Uortb = (*log->sU1_orta + *log->sU1_ortb) * 0.7071f;
+				I = *log->sI1_orta * Uorta +
+						*log->sI1_ortb * Uortb;
+				wk1 = I > 0;
+				sprawdz_P (
+					&log->dw.Kp,
+					wk1,
+					!wk1,
+					&log->dw.liczKdod,
+					3,3
+					);
+				log->dw.Km = !log->dw.Kp;
+			} else {
+				log->dw.Km = log->dw.Kp = 0;
+			}
+		}
+
+		//*log->z[0]=blok_do_szyn?65535:0;
+		//*log->z[1]=phi1;
+		//*log->z[2]=phi2;
+		//*log->z[3]=phi;
+
+		//-----------------------------------------------------------------------------
+		//Ustalenie pobudzen stref
+		//okreslenie warunkow kierunkowych
+		//zwarcie jednofazowe z ziemia strefa 1 i 1W
+
+//		u16 Zm_vect=0;
+	//	for(i=0;i<9;i++)
+		//	Zm_vect|=log->dw.Zm[i]?(1<<i):0;
+//Zm_vect=0;
+//		for(i=0;i<6;i++)
+	//		if(log->dw.P[i][1] || log->dw.P[i][3] || log->dw.P[i][4])
+		//		Zm_vect|=(1<<i);
+
+//		*log->z[4]=Zm_vect;
+//		Zm_vect=0;
+	//			for(i=0;i<6;i++)
+		//			if(log->dw.XKp[i][1] || log->dw.XKp[i][1+3] || log->dw.XKp[i][3+3] || log->dw.XKp[i][4+3])
+			//			Zm_vect|=(1<<i);
+
+	//			*log->z[5]=Zm_vect;
+
+		if (!check_struct(&log->Bl_K))//jeśli nie ma blokady kierunku
+		{
+			for(j=0;j<2;j++)
+			{
+			
+				switch(log->nast_.kierunek[j])
+				{
+					case 0: //bezkierunku
+						for(i=0;i<3;i++)
+						{
+							log->dw.P[j][i] = log->dw.Pbk[j][i];
+						}
+						break;
+					case 1: //do linii
+						if(blok_szpilki!=3)
+						for(i=0;i<3;i++)
+						{
+							if(ZDISTA_POPRAWKA_3)
+								log->dw.P[j][i] = log->dw.Pbk[j][i] && (log->dw.Zm[i]?log->dw.Kp:log->dw.XKp[j][i]) && !blok_do_linii;
+							else
+								log->dw.P[j][i] = log->dw.Pbk[j][i] && (log->dw.Zm[i]?log->dw.Kp:log->dw.XKp[j][i]);
+						}
+						break;
+					case 2: // do szyn
+						if(blok_szpilki!=3)
+						for(i=0;i<3;i++)
+						{
+							if(ZDISTA_POPRAWKA_3)
+								log->dw.P[j][i] = log->dw.Pbk[j][i] && (log->dw.Zm[i]?log->dw.Km:log->dw.XKm[j][i]) && !blok_do_szyn;
+							else
+								log->dw.P[j][i] = log->dw.Pbk[j][i] && (log->dw.Zm[i]?log->dw.Km:log->dw.XKm[j][i]);
+						}
+						break;
+				}
+			}
+
+			//zwarcie jednofazowe z ziemia - pozostale
+			for(j=2;j<6;j++)
+			{
+				switch(log->nast_.kierunek[j])
+				{
+					case 0: //bezkierunku
+						for(i=3;i<6;i++)
+						{
+							log->dw.P[j][i-3] = log->dw.Pbk[j][i-3];
+						}
+						break;
+					case 1: //do linii
+						if(blok_szpilki!=3)
+						for(i=3;i<6;i++)
+						{
+							if(ZDISTA_POPRAWKA_3)
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Kp:log->dw.XKp[j][i]) && !blok_do_linii;
+							else
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Kp:log->dw.XKp[j][i]);
+						}
+						break;
+					case 2: // do szyn
+						if(blok_szpilki!=3)
+						for(i=3;i<6;i++)
+						{
+							if(ZDISTA_POPRAWKA_3)
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Km : log->dw.XKm[j][i]) && !blok_do_szyn;
+							else
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Km : log->dw.XKm[j][i]);
+						}
+						break;
+				}
+			}
+
+			//zwarcie miedzyfazowe
+			for(j=0;j<6;j++)
+			{
+				switch(log->nast_.kierunek[j])
+				{
+					case 0: //bezkierunku
+						for(i=6;i<9;i++)
+						{
+							log->dw.P[j][i-3] = log->dw.Pbk[j][i-3];
+						}
+						break;
+					case 1: //do linii
+						if(blok_szpilki!=3)
+						for(i=6;i<9;i++)
+						{
+							if(ZDISTA_POPRAWKA_3)
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Kp:log->dw.XKp[j][i]) && !blok_do_linii;
+							else
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Kp:log->dw.XKp[j][i]);
+						}
+						break;
+					case 2: // do szyn
+						if(blok_szpilki!=3)
+						for(i=6;i<9;i++)
+						{
+							if(ZDISTA_POPRAWKA_3)
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Km:log->dw.XKm[j][i]) && !blok_do_szyn;
+							else
+								log->dw.P[j][i-3] = log->dw.Pbk[j][i-3] && (log->dw.Zm[i]?log->dw.Km:log->dw.XKm[j][i]);
+						}
+						break;
+				}
+			}
+		} else {
+			for(j=0;j<6;j++)
+			{
+				for(i=6;i<9;i++)
+				{
+					log->dw.P[j][i-3] = log->dw.Pbk[j][i-3]; //poprawiony strzal z boku?
+				}
+
+			}
+		}
+
+		//-----------------------------------------------------------------------------
+
+
+		//obsluga wejscia testu przekaznika
+		if (czy_test_R())
+		{
+			for(i=0;i<36;i++)
+			{
+				*(&log->dw.P[0][0] + i) = check_struct(&log->test)?1:0;
+			}
+		}
+        //
+
+        // realizacja blokady dzialania przekaznika
+		if((log->nast_.bl_ && check_struct(&log->stan_bl))/* | czy_start()*/)
+		{
+			for(i=0;i<36;i++)
+			{
+				*(&log->dw.P[0][0] + i)  = 0;
+			}
+		}
+				
+		check_and_set_struct(log->dw.P[0][0], &log->P1W_L1E);
+		check_and_set_struct(log->dw.P[0][1], &log->P1W_L2E);
+		check_and_set_struct(log->dw.P[0][2], &log->P1W_L3E);
+		check_and_set_struct(log->dw.P[0][3], &log->P1W_L1L2);
+		check_and_set_struct(log->dw.P[0][4], &log->P1W_L2L3);
+		check_and_set_struct(log->dw.P[0][5], &log->P1W_L3L1);
+		check_and_set_struct(log->dw.P[1][0], &log->P1_L1E);
+		check_and_set_struct(log->dw.P[1][1], &log->P1_L2E);
+		check_and_set_struct(log->dw.P[1][2], &log->P1_L3E);
+		check_and_set_struct(log->dw.P[1][3], &log->P1_L1L2);
+		check_and_set_struct(log->dw.P[1][4], &log->P1_L2L3);
+		check_and_set_struct(log->dw.P[1][5], &log->P1_L3L1);
+		check_and_set_struct(log->dw.P[2][0], &log->P2_L1E);
+		check_and_set_struct(log->dw.P[2][1], &log->P2_L2E);
+		check_and_set_struct(log->dw.P[2][2], &log->P2_L3E);
+		check_and_set_struct(log->dw.P[2][3], &log->P2_L1L2);
+		check_and_set_struct(log->dw.P[2][4], &log->P2_L2L3);
+		check_and_set_struct(log->dw.P[2][5], &log->P2_L3L1);
+		check_and_set_struct(log->dw.P[3][0], &log->P3_L1E);
+		check_and_set_struct(log->dw.P[3][1], &log->P3_L2E);
+		check_and_set_struct(log->dw.P[3][2], &log->P3_L3E);
+		check_and_set_struct(log->dw.P[3][3], &log->P3_L1L2);
+		check_and_set_struct(log->dw.P[3][4], &log->P3_L2L3);
+		check_and_set_struct(log->dw.P[3][5], &log->P3_L3L1);
+		check_and_set_struct(log->dw.P[4][0], &log->P4_L1E);
+		check_and_set_struct(log->dw.P[4][1], &log->P4_L2E);
+		check_and_set_struct(log->dw.P[4][2], &log->P4_L3E);
+		check_and_set_struct(log->dw.P[4][3], &log->P4_L1L2);
+		check_and_set_struct(log->dw.P[4][4], &log->P4_L2L3);
+		check_and_set_struct(log->dw.P[4][5], &log->P4_L3L1);
+		check_and_set_struct(log->dw.P[5][0], &log->P5_L1E);
+		check_and_set_struct(log->dw.P[5][1], &log->P5_L2E);
+		check_and_set_struct(log->dw.P[5][2], &log->P5_L3E);
+		check_and_set_struct(log->dw.P[5][3], &log->P5_L1L2);
+		check_and_set_struct(log->dw.P[5][4], &log->P5_L2L3);
+		check_and_set_struct(log->dw.P[5][5], &log->P5_L3L1);
+	
+		/*debug
+		check_and_set_struct(log->dw.Igr[0], &log->P5_L2E);
+		check_and_set_struct(log->dw.XKp[2][0], &log->P5_L3E);
+		check_and_set_struct(log->dw.Pbk[2][0], &log->P5_L1L2);	
+		check_and_set_struct(log->dw.Km, &log->P5_L2L3);
+		check_and_set_struct(log->dw.Kp, &log->P5_L3L1);
+		*/
+    }
+	else
+	{
+		/*for(i=0;i<36;i++)
+		{
+			//clear_struct((struct binary_io *)((u8 *)&log->P1W_L1E+(sizeof(struct binary_io)*i)));
+		}*/
+		clear_struct(&log->P1W_L1E);
+		clear_struct(&log->P1W_L2E);
+		clear_struct(&log->P1W_L3E);
+		clear_struct(&log->P1W_L1L2);
+		clear_struct(&log->P1W_L2L3);
+		clear_struct(&log->P1W_L3L1);
+		clear_struct(&log->P1_L1E);
+		clear_struct(&log->P1_L2E);
+		clear_struct(&log->P1_L3E);
+		clear_struct(&log->P1_L1L2);
+		clear_struct(&log->P1_L2L3);
+		clear_struct(&log->P1_L3L1);
+		clear_struct(&log->P2_L1E);
+		clear_struct(&log->P2_L2E);
+		clear_struct(&log->P2_L3E);
+		clear_struct(&log->P2_L1L2);
+		clear_struct(&log->P2_L2L3);
+		clear_struct(&log->P2_L3L1);
+		clear_struct(&log->P3_L1E);
+		clear_struct(&log->P3_L2E);
+		clear_struct(&log->P3_L3E);
+		clear_struct(&log->P3_L1L2);
+		clear_struct(&log->P3_L2L3);
+		clear_struct(&log->P3_L3L1);
+		clear_struct(&log->P4_L1E);
+		clear_struct(&log->P4_L2E);
+		clear_struct(&log->P4_L3E);
+		clear_struct(&log->P4_L1L2);
+		clear_struct(&log->P4_L2L3);
+		clear_struct(&log->P4_L3L1);
+		clear_struct(&log->P5_L1E);
+		clear_struct(&log->P5_L2E);
+		clear_struct(&log->P5_L3E);
+		clear_struct(&log->P5_L1L2);
+		clear_struct(&log->P5_L2L3);
+		clear_struct(&log->P5_L3L1);
+	}
+}
diff --git a/ZDistA_komp.h b/ZDistA_komp.h
new file mode 100644
index 0000000..a04201a
--- /dev/null
+++ b/ZDistA_komp.h
@@ -0,0 +1,465 @@
+/*
+ * ZDistA.h
+ *
+ *
+ *  Created on: 21-07-2023
+ *      Author: PS
+ */
+
+#ifndef ZDISTA_H_KOMP
+#define ZDISTA_H_KOMP
+
+//#include "pawel_usun_to.h"
+
+#include "../tdefs.h"
+#include "helper.h"
+#include "ZDistL.h"
+
+
+	struct impedancja_ZDistA_komp
+	{
+		float R[9];	// czesc rzeczywista impedancji
+		float X[9]; // czesc urojona impedancji
+		float Z[9]; //kwadrat impedancji
+		float absR[9]; // wartosc bezwzgledna impedancji czesc rzeczywista
+		float absX[9]; // wartosc bezwzgledna impedancji czesc urojona
+		float XRtanfi2[9]; // abs(X+R*tan(fi2))
+	//	float XRtanfi1[9]; // abs(X-R*tan(fi1))
+						//[0] petla L1-E strefa 1
+						//[1] petla L2-E strefa 1
+						//[2] petla L3-E strefa 1
+						//[3] petla L1-E strefa 2,3,4,5
+						//[4] petla L2-E strefa 2,3,4,5
+						//[5] petla L3-E strefa 2,3,4,5
+						//[6] petla L1-L2
+						//[7] petla L2-L3
+						//[8] petla L3-L1
+		float XRtanfi1_noabs[9];
+		//float E[9];
+	};
+
+	struct dane_wewnetrzne_ZDistA_komp
+	{
+		struct impedancja_ZDistA_komp Z;
+		u8 Km;
+		u8 Kp;
+		u8 Igr[6]; // przekroczenie wartosci granicznej pradu
+		u8 Iogr; // zwarcie z udzialem ziemi
+		u8 P_s[6][6];//pobudzenie kryterium impedacyjnego (obszar) [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1]
+		u8 P_sss[6][6];
+		u8 Pbk[6][6];//pobudzenie w strefie [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1] bezkierunkowe
+		u8 P[6][6];//pobudzenie w strefie [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1]
+		u8 BL_Load[9]; ///< impedancja w obszrze pradow roboczych
+		u8 XKp[6][9]; ///< impedancyjne kryterium kierunku "do przodu"
+		u8 XKm[6][9]; ///< impedancyjne kryterium kierunku "do tylu"
+		u8 Zm[9];///< impedancyjne kryterium bardzo bliskiego zwarcia
+		short liczp10[9]; /// licznik pobudzen
+		short liczp11[6][9]; /// licznik pobudzen
+		short liczp12[6][9]; /// licznik pobudzen
+						//[0] petla L1-E strefa 1
+						//[1] petla L2-E strefa 1
+						//[2] petla L3-E strefa 1
+						//[3] petla L1-E strefa 2,3,4,5
+						//[4] petla L2-E strefa 2,3,4,5
+						//[5] petla L3-E strefa 2,3,4,5
+						//[6] petla L1-L2
+						//[7] petla L2-L3
+						//[8] petla L3-L1
+		short liczps[6][6]; //liczniki pobudzen dla pobudzen stref [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1]
+		short liczpIo; //licznik pobudzen dla identyfikacji zwarc z udzialem ziemi
+		short liczKdod;
+		float U1;
+		float U2;
+		float U3;
+		float I1;
+		float I2;
+		float I3;
+		struct ZDistA_komp_logic *log_ptr;
+
+		//wyliczenie dl wektora
+		float modul_zf[6];
+		float modul_zmf[6];
+		float Z_min;
+		float Z_min_mf;
+	};
+
+	struct nast_w_poligon_komp
+	{
+		float Xr; // zasieg dla poligonu i srodek okregu dla kolowej wspolrzedna X
+		float Rr; // zasieg dla dla poligonu i srodek okregu dla kolowej wspolrzedna R
+		float Z; // srednica kola charakterystyki kolowej
+		float Xp; // zasieg dla poligonu i srodek okregu dla kolowej wspolrzedna X dla powrotu
+		float Rp; // zasieg dla dla poligonu i srodek okregu dla kolowej wspolrzedna R dla powrotu
+		float Zp; // srednica kola charakterystyki kolowej dla powrotu
+		float Rrtanfi1;// wartość rozruchowa prostej nachylonej kątem linii
+		float Rptanfi1;// wartość powrotowa prostej nachylonej kątem linii
+	};
+
+	struct Wyjscia_ZDistA_komp // struktura wyjsc przekaznika
+	{
+		struct dane_wewnetrzne_ZDistA_komp *Zdist_dw;
+		float przekladnia;
+		u8 *on;
+		u8 SOTF_zwrotnie;
+	};
+
+
+    struct Nastawy_przeliczone_ZDistA_komp
+    {
+		struct Wyjscia_ZDistA_komp wyjscie;
+		u8 on_;
+		u8 bl_;
+		u8 z6_kolo;
+		u8 Bl_L[6];
+		u8 typ[6];// typ charakterystyki 0 - poligonalna, 1- kolowa
+		float ReK1; // skladowa rzeczywista wspolczynnika kompensacji ziemnozwarciowej dla strefy 1
+		float ImK1;// skladowa urojona wspolczynnika kompensacji ziemnozwarciowej dla strefy 1
+		float ReKr;// skladowa rzeczywista wspolczynnika kompensacji ziemnozwarciowej dla stref 2,3,4,5
+		float ImKr;// skladowa urojona wspolczynnika kompensacji ziemnozwarciowej dla stref 2,3,4,5
+
+		struct nast_w_poligon_komp n_pol[6][2]; // nastawy stref dla charakterystyki poligonalnej [numer strefy][LE/LL]
+		float tanfi1; // tangens kata linii
+		float tanfi2; //tangens kata dodatkowej prostej dla charakterystyki poligonalnej strefa 1
+		float Xr1f; // wartosc rozruchowa dodatkowej prostej dla charakterystyki poligonalnej
+		float Xr1fp; // wartosc powrotowa dodatkowej prostej dla charakterystyki poligonalnej
+		float Xr1Wf; // wartosc rozruchowa dodatkowej prostej dla charakterystyki poligonalnej
+		float Xr1Wfp; // wartosc powrotowa dodatkowej prostej dla charakterystyki poligonalnej
+		float Igr; // wartosc kwadratu pradu granicznego warunku dzialania przekaznika
+		float Igrp; // wartosc kwadratu pradu granicznego warunku dzialania przekaznika (powrot)
+
+		float Zgr;// minimalna wartosc impedancji kryteriunkierunkowego w kwadracie
+		float kp;//współczynnik powrotu dla niedomiarówek
+		float kpp;//współczynnik powrotu dla nadmiarówek
+		float kpk; //kwadrat współczynnika powrotu
+		short kierunek[6];
+
+		//A2
+		float XKR; // wspolczynnik prostej R kierunku kryterium impedancyjnego
+		float XKX; // wspolczynnik prostej R kierunku kryterium impedancyjnego
+		float KL;//wspolczynnik prostej dla blokady od obszaru obciażenia
+		float RLf; // wartosc rozruchowa blokady Load do przodu
+		float RLr; // wartosc rozruchowa blokady Load do tylu
+		float Iogr; // wartosc graniczna skladowej zerowej identyfikacji zwarc z udzialem ziemi
+		float khio; // wspolczynnik stabilizacji dla przekaznika identyfikacji zwarc z udzialem ziemi
+		float Uomin; ///< minimalna wartość napięcia składowej zerowej
+		
+		float ReKrown; // skladowa rzeczywista wspolczynnika dla linii rownoleglej
+		float ImKrown;// skladowa urojona wspolczynnika dla linii rownoleglej
+		float Krown_ignac;
+		
+		float kp_obc; //wspolczynnik powrotu krzywych obciazenia
+		float kpp_obc; //kwadrat współczynnika powrotu krzywych obciazenia
+
+    };
+
+struct ZDistA_komp_logic
+{
+        struct binary_io stan_bl;
+		struct binary_io Bl_K;
+		float *I1_orta; ///< Skladowa ortogonalna a pradu faza L1
+		float *I1_ortb; ///< Skladowa ortogonalna b pradu faza L1
+		float *I1; ///< Prad mierzony faza 1
+		float *I2_orta; ///< Skladowa ortogonalna a pradu faza L2
+		float *I2_ortb; ///< Skladowa ortogonalna b pradu faza L2
+		float *I2; ///< Prad mierzony faza 2
+		float *I3_orta; ///< Skladowa ortogonalna a pradu faza L3
+		float *I3_ortb; ///< Skladowa ortogonalna b pradu faza L3
+		float *I3; ///< Prad mierzony faza 3
+		float *U1_orta; ///< Skladowa ortogonalna a napiecia faza L1
+		float *U1_ortb; ///< Skladowa ortogonalna b napiecia faza L1
+		float *U1; ///< Napiecie mierzone faza 1
+		float *U2_orta; ///< Skladowa ortogonalna a napiecia faza L2
+		float *U2_ortb; ///< Skladowa ortogonalna b napiecia faza L2
+		float *U2; ///< Napiecie mierzone faza 2
+		float *U3_orta; ///< Skladowa ortogonalna a napiecia faza L3
+		float *U3_ortb; ///< Skladowa ortogonalna b napiecia faza L3
+		float *U3; ///< Napiecie mierzone faza 3
+		float *U12_orta; ///< Skladowa ortogonalna a napiecia L1-L2
+		float *U12_ortb; ///< Skladowa ortogonalna b napiecia L1-L2
+		float *U12; ///< Napiecie mierzone L1-L2
+		float *U23_orta; ///< Skladowa ortogonalna a napiecia L2-L3
+		float *U23_ortb; ///< Skladowa ortogonalna b napiecia L2-L3
+		float *U23; ///< Napiecie mierzone L2-L3
+		float *U31_orta; ///< Skladowa ortogonalna a napiecia L3-L1
+		float *U31_ortb; ///< Skladowa ortogonalna b napiecia L3-L1
+		float *U31; ///< Napiecie mierzone L3-L1
+		float *sI1_orta; ///< Skladowa ortogonalna a skladowej zgodnej pradu
+		float *sI1_ortb; ///< Skladowa ortogonalna b skladowej zgodnej pradu
+		float *sI1; ///< Skladowa zgodna pradu
+		float *sI2_orta; ///< Skladowa ortogonalna a skladowej przeciwnej pradu
+		float *sI2_ortb; ///< Skladowa ortogonalna b skladowej przeciwnej pradu
+		float *sI2; ///< Skladowa przeciwna pradu
+		float *sI0_orta; ///< Skladowa ortogonalna a skladowej zerowej pradu
+		float *sI0_ortb; ///< Skladowa ortogonalna b skladowej zerowej pradu
+		float *sI0; ///< Skladowa zerowa pradu
+		float *sU1_orta; ///< Skladowa ortogonalna a skladowej zgodnej napiecia
+		float *sU1_ortb; ///< Skladowa ortogonalna b skladowej zgodnej napiecia
+		float *sU1; ///< Skladowa zgodna napiecia
+		float *sU2_orta; ///< Skladowa ortogonalna a skladowej przeciwnej napiecia
+		float *sU2_ortb; ///< Skladowa ortogonalna b skladowej przeciwnej napiecia
+		float *sU2; ///< Skladowa przeciwna napiecia
+		float *sU0_orta; ///< Skladowa ortogonalna a skladowej zerowej napiecia
+		float *sU0_ortb; ///< Skladowa ortogonalna b skladowej zerowej napiecia
+		float *sU0; ///< Skladowa zerowa napiecia
+		struct analog_in_params *param_I; ///< Parametry wejscia pradowego
+		struct analog_in_params *param_U; /// < Parametry kanalu napieciowego
+		struct binary_io test;
+		struct binary_io P1W_L1E; ///< Pobudzenie strefy 1W zwarcie L1-E
+		struct binary_io P1W_L2E; ///< Pobudzenie strefy 1W zwarcie L2-E
+		struct binary_io P1W_L3E; ///< Pobudzenie strefy 1W zwarcie L3-E
+		struct binary_io P1W_L1L2; ///< Pobudzenie strefy 1W zwarcie L1-L2
+		struct binary_io P1W_L2L3; ///< Pobudzenie strefy 1W zwarcie L2-L3
+		struct binary_io P1W_L3L1; ///< Pobudzenie strefy 1W zwarcie L3-L1
+		struct binary_io P1_L1E; ///< Pobudzenie strefy 1 zwarcie L1-E
+		struct binary_io P1_L2E; ///< Pobudzenie strefy 1 zwarcie L2-E
+		struct binary_io P1_L3E; ///< Pobudzenie strefy 1 zwarcie L3-E
+		struct binary_io P1_L1L2; ///< Pobudzenie strefy 1 zwarcie L1-L2
+		struct binary_io P1_L2L3; ///< Pobudzenie strefy 1 zwarcie L2-L3
+		struct binary_io P1_L3L1; ///< Pobudzenie strefy 1 zwarcie L3-L1
+		struct binary_io P2_L1E; ///< Pobudzenie strefy 2 zwarcie L1-E
+		struct binary_io P2_L2E; ///< Pobudzenie strefy 2 zwarcie L2-E
+		struct binary_io P2_L3E; ///< Pobudzenie strefy 2 zwarcie L3-E
+		struct binary_io P2_L1L2; ///< Pobudzenie strefy 2 zwarcie L1-L2
+		struct binary_io P2_L2L3; ///< Pobudzenie strefy 2 zwarcie L2-L3
+		struct binary_io P2_L3L1; ///< Pobudzenie strefy 2 zwarcie L3-L1
+		struct binary_io P3_L1E; ///< Pobudzenie strefy 3 zwarcie L1-E
+		struct binary_io P3_L2E; ///< Pobudzenie strefy 3 zwarcie L2-E
+		struct binary_io P3_L3E; ///< Pobudzenie strefy 3 zwarcie L3-E
+		struct binary_io P3_L1L2; ///< Pobudzenie strefy 3 zwarcie L1-L2
+		struct binary_io P3_L2L3; ///< Pobudzenie strefy 3 zwarcie L2-L3
+		struct binary_io P3_L3L1; ///< Pobudzenie strefy 3 zwarcie L3-L1
+		struct binary_io P4_L1E; ///< Pobudzenie strefy 4 zwarcie L1-E
+		struct binary_io P4_L2E; ///< Pobudzenie strefy 4 zwarcie L2-E
+		struct binary_io P4_L3E; ///< Pobudzenie strefy 4 zwarcie L3-E
+		struct binary_io P4_L1L2; ///< Pobudzenie strefy 4 zwarcie L1-L2
+		struct binary_io P4_L2L3; ///< Pobudzenie strefy 4 zwarcie L2-L3
+		struct binary_io P4_L3L1; ///< Pobudzenie strefy 4 zwarcie L3-L1
+		struct binary_io P5_L1E; ///< Pobudzenie strefy 5 zwarcie L1-E
+		struct binary_io P5_L2E; ///< Pobudzenie strefy 5 zwarcie L2-E
+		struct binary_io P5_L3E; ///< Pobudzenie strefy 5 zwarcie L3-E
+		struct binary_io P5_L1L2; ///< Pobudzenie strefy 5 zwarcie L1-L2
+		struct binary_io P5_L2L3; ///< Pobudzenie strefy 5 zwarcie L2-L3
+		struct binary_io P5_L3L1; ///< Pobudzenie strefy 5 zwarcie L3-L1
+		struct binary_io deakt; /// deaktywacja
+		struct binary_io wyl; ///wejscie zwrotne info o wylacenia
+		float *I_row_orta; ///< Skladowa ortogonalna a skladowej zgodnej napiecia
+		float *I_row_ortb; ///< Skladowa ortogonalna a skladowej zgodnej napiecia
+		struct analog_in_params *param_I_rown; ///< Parametry wejscia pradowego
+    	struct dane_wewnetrzne_ZDistA_komp dw;
+    	struct Nastawy_przeliczone_ZDistA_komp nast_;// struktura z parametrami
+
+		u8 l_nieustalony;
+
+    	float *z[6]; /// debug
+};
+
+struct ZDistA_komp_io
+{
+	u32 bl_in;
+	u32 bl_k_in;
+	u32 i1_orta_float_in;
+	u32 i1_ortb_float_in;
+	u32 i1_float_in;
+	u32 i2_orta_float_in;
+	u32 i2_ortb_float_in;
+	u32 i2_float_in;
+	u32 i3_orta_float_in;
+	u32 i3_ortb_float_in;
+	u32 i3_float_in;
+	u32 u1_orta_float_in;
+	u32 u1_ortb_float_in;
+	u32 u1_float_in;
+	u32 u2_orta_float_in;
+	u32 u2_ortb_float_in;
+	u32 u2_float_in;
+	u32 u3_orta_float_in;
+	u32 u3_ortb_float_in;
+	u32 u3_float_in;
+	u32 u12_orta_float_in;
+	u32 u12_ortb_float_in;
+	u32 u12_float_in;
+	u32 u23_orta_float_in;
+	u32 u23_ortb_float_in;
+	u32 u23_float_in;
+	u32 u31_orta_float_in;
+	u32 u31_ortb_float_in;
+	u32 u31_float_in;
+	u32 i1_zg_orta_float_in;
+	u32 i1_zg_ortb_float_in;
+	u32 i1_zg_float_in;
+	u32 i2_pr_orta_float_in;
+	u32 i2_pr_ortb_float_in;
+	u32 i2_pr_float_in;
+	u32 io_orta_float_in;
+	u32 io_ortb_float_in;
+	u32 io_float_in;
+	u32 u1_zg_orta_float_in;
+	u32 u1_zg_ortb_float_in;
+	u32 u1_zg_float_in;
+	u32 u2_pr_orta_float_in;
+	u32 u2_pr_ortb_float_in;
+	u32 u2_pr_float_in;
+	u32 uo_orta_float_in;
+	u32 uo_ortb_float_in;
+	u32 uo_float_in;
+	u32 i_param_an_ptr_in;
+	u32 u_param_an_ptr_in;
+	u32 test_in;
+	u32 deakt_in;
+	u32 wyl_in;
+
+  u32 i_rown_orta_float_in;
+  u32 i_rown_ortb_float_in;
+  u32 i_rown_an_ptr_in;
+  
+	u32 wy_ptr_out;	//zainicjowac
+	u32 P1W_L1E_out;
+	u32 P1W_L2E_out;
+	u32 P1W_L3E_out;
+	u32 P1W_L1L2_out;
+	u32 P1W_L2L3_out;
+	u32 P1W_L3L1_out;
+	u32 P1_L1E_out;
+	u32 P1_L2E_out;
+	u32 P1_L3E_out;
+	u32 P1_L1L2_out;
+	u32 P1_L2L3_out;
+	u32 P1_L3L1_out;
+	u32 P2_L1E_out;
+	u32 P2_L2E_out;
+	u32 P2_L3E_out;
+	u32 P2_L1L2_out;
+	u32 P2_L2L3_out;
+	u32 P2_L3L1_out;
+	u32 P3_L1E_out;
+	u32 P3_L2E_out;
+	u32 P3_L3E_out;
+	u32 P3_L1L2_out;
+	u32 P3_L2L3_out;
+	u32 P3_L3L1_out;
+	u32 P4_L1E_out;
+	u32 P4_L2E_out;
+	u32 P4_L3E_out;
+	u32 P4_L1L2_out;
+	u32 P4_L2L3_out;
+	u32 P4_L3L1_out;
+	u32 P5_L1E_out;
+	u32 P5_L2E_out;
+	u32 P5_L3E_out;
+	u32 P5_L1L2_out;
+	u32 P5_L2L3_out;
+	u32 P5_L3L1_out;
+
+	//debug
+	u32 z1_float_out;
+	u32 z2_float_out;
+	u32 z3_float_out;
+	u32 z4_float_out;
+	u32 z5_float_out;
+	u32 z6_float_out;
+	
+}__attribute__((__packed__));
+
+struct ZDistA_komp_params
+{
+	u32 bity; ///< nastawy bitowe;
+
+	long Typ1; ///< Typ charakterystyki strefa 1
+	long Typ2; ///< Typ charakterystyki strefa 2
+	long Typ3; ///< Typ charakterystyki strefa 3
+	long Typ4; ///< Typ charakterystyki strefa 4
+	long Typ5; ///< Typ charakterystyki strefa 5
+	long K1; ///< Kierunek dzialania strefa 1
+	long K2; ///< Kierunek dzialania strefa 2
+	long K3; ///< Kierunek dzialania strefa 3
+	long K4; ///< Kierunek dzialania strefa 4
+	long K5; ///< Kierunek dzialania strefa 5
+
+	double I_min; ///< Graniczna wartosc pradu
+	double Kk1;	///< Wspolczynnik kompensacji ziemnozwarciowej strefa 1
+	double Kk1_kat; ///< Kat wektora kompensacji ziemnozwarciowej strefa 1
+	double KkC; ///< Wspolczynnik kompensacji ziemnozwarciowej stref 2,3,4,5
+	double KkC_kat; ///< Kat wektora kompensacji ziemnozwarciowej stref 2,3,4,5
+	double fi1; ///< Kat linii
+	double fi2; ///< Kat nachylenia prostej korekcji strefy pierwszej dla zwarc jednofazowych z ziemia
+	double R1W_Zf1W_LE; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///<	Zasieg „do przodu” wydluzenie strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double R1W_Zf1W_LL; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do przodu” wyduzenie strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
+	double R1_Zf1_LE; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///<	Zasieg „do przodu” strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double R1_Zf1_LL; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do przodu” strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
+	double R2_Zf2_LE; ///< Zasieg rezystancyjny strefy 2 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///<	Zasieg „do przodu” strefy 2 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double R2_Zf2_LL; ///< Zasieg rezystancyjny strefy 2 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do przodu” strefy 2 charakterystyki kolowej zwarcie miedzyfazowe
+	double R3_Zf3_LE; ///< Zasieg rezystancyjny strefy 3 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///<	Zasieg „do przodu” strefy 3 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double R3_Zf3_LL; ///< Zasieg rezystancyjny strefy 3 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do przodu” strefy 3 charakterystyki kolowej zwarcie miedzyfazowe
+	double R4_Zf4_LE; ///< Zasieg rezystancyjny strefy 4 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///<	Zasieg „do przodu” strefy 4 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double R4_Zf4_LL; ///< Zasieg rezystancyjny strefy 4 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do przodu” strefy 4 charakterystyki kolowej zwarcie miedzyfazowe
+	double R5_Zf5_LE; ///< Zasieg rezystancyjny strefy 5 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///<	Zasieg „do przodu” strefy 5 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double R5_Zf5_LL; ///< Zasieg rezystancyjny strefy 5 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do przodu” strefy 5 charakterystyki kolowej zwarcie miedzyfazowe
+	double X1W_Zr1W_LE; ///< Zasieg reaktancyjny wydluzenie strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///< Zasieg „do tylu” wydluzenie strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double X1W_Zr1W_LL; ///<  Zasieg reaktancyjny wydluzenie strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do tylu” wydluzenie strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
+	double X1_Zr1_LE; ///< Zasieg reaktancyjny strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///< Zasieg „do tylu” strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double X1_Zr1_LL; ///<  Zasieg reaktancyjny strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do tylu” strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
+	double X2_Zr2_LE; ///< Zasieg reaktancyjny strefy 2 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///< Zasieg „do tylu” strefy 2 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double X2_Zr2_LL; ///<  Zasieg reaktancyjny strefy 2 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do tylu” strefy 2 charakterystyki kolowej zwarcie miedzyfazowe
+	double X3_Zr3_LE; ///< Zasieg reaktancyjny strefy 3 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///< Zasieg „do tylu” strefy 3 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double X3_Zr3_LL; ///<  Zasieg reaktancyjny strefy 3 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do tylu” strefy 3 charakterystyki kolowej zwarcie miedzyfazowe
+	double X4_Zr4_LE; ///< Zasieg reaktancyjny strefy 4 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///< Zasieg „do tylu” strefy 4 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double X4_Zr4_LL; ///<  Zasieg reaktancyjny strefy 4 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do tylu” strefy 4 charakterystyki kolowej zwarcie miedzyfazowe
+	double X5_Zr5_LE; ///< Zasieg reaktancyjny strefy 5 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
+						///< Zasieg „do tylu” strefy 5 charakterystyki kolowej zwarcie jednofazowe z ziemia
+	double X5_Zr5_LL; ///<  Zasieg reaktancyjny strefy 5 dla charakterystyki poligonalnej zwarcie miedzyfazowe
+						///< Zasieg „do tylu” strefy 5 charakterystyki kolowej zwarcie miedzyfazowe
+	double kp; ///< wspolczynnik powrotu
+//A2
+//	double U_min; ///< Minimalna wartosc napiecia
+	double fi3; ///< Kat kierunkowy od osi X impedancyjnego kryterium kierunku
+	double fi4; ///< Kat kierunkowy od osi R  impedancyjnego kryterium kierunku
+	double RLf; ///< Zasieg „ do przodu” kryterium blokady dzialania w zakresie pradow obciażenia
+	double RLr; ///< Zasieg „ do tylu” kryterium blokady dzialania w zakresie pradow obciażenia
+	double fi5; ///< Kat kierunkowy blokady dzialania w zakresie pradow obciażenia
+	double Iomin; ///< Minimalna wartosc rozruchowa pradu zerowego przekaznika identyfikacji zwarc z udzialem ziemi
+	double Iokh; ///< Wspolczynnik stabilizacji charakterystyki przekaznika identyfikacji zwarc z udzialem ziemi
+	double Uomin; ///< minimalna wartość napięcia składowej zerowej
+
+	long Typ0; ///< Typ charakterystyki strefa 1W
+	long K0; ///< Kierunek dzialania strefa 1W
+  
+  	double Krown;	///< Wspolczynnik kompensacji linii rown
+	double Krown_kat; ///< Kat wektora kompensacji lnii rown
+	
+	double kp_obc; ///< Współczynnik powrotu dla blokady od prądu obciążenia
+
+}__attribute__((__packed__));
+
+struct ZDistA_komp_args
+{
+	struct ZDistA_komp_io io;
+	struct ZDistA_komp_params params;
+//	u16 crc;
+}__attribute__((__packed__));
+
+extern void ZDistA_komp(void *args, void *logic);
+extern int ZDistA_komp_initlog(void *arguments, void *logic);
+
+#endif /* ZDISTA_H_KOMP */
diff --git a/ZDistL_komp.c b/ZDistL_komp.c
new file mode 100644
index 0000000..b192f93
--- /dev/null
+++ b/ZDistL_komp.c
@@ -0,0 +1,1589 @@
+/*
+ * ZDistL.c
+ *
+ *  Created on: 07-03-2017
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#include <math.h>
+
+#include "../tdefs.h"
+#include "../misc.h"
+#include "helper.h"
+
+#include "ZDistL_komp.h"
+#include "ZDistA_komp.h"
+
+
+struct ZDistL_nast_komp
+{
+	double ts0LE;///< Czas wyłączenia strefy 1W zwarcia jednofazowe z ziemią
+	double ts0LL;///< Czas wyłączenia strefy 1W zwarcia miedzyfazowe
+	double ts1LE;///< Czas wyłączenia strefy 1 zwarcia jednofazowe z ziemią
+	double ts1LL;///< Czas wyłączenia strefy 1 zwarcia miedzyfazowe
+	double ts2LE;///< Czas wyłączenia strefy 2 zwarcia jednofazowe z ziemią
+	double ts2LL;///< Czas wyłączenia strefy 2 zwarcia miedzyfazowe
+	double ts3LE;///< Czas wyłączenia strefy 3 zwarcia jednofazowe z ziemią
+	double ts3LL;///< Czas wyłączenia strefy 3 zwarcia miedzyfazowe
+	double ts4LE;///< Czas wyłączenia strefy 4 zwarcia jednofazowe z ziemią
+	double ts4LL;///< Czas wyłączenia strefy 4 zwarcia miedzyfazowe
+	double ts5LE;///< Czas wyłączenia strefy 5 zwarcia jednofazowe z ziemią
+	double ts5LL;///< Czas wyłączenia strefy 5 zwarcia miedzyfazowe
+
+	long Stf0; ///< Sposób działania strefy 1W
+	long Stf1; ///< Sposób działania strefy 1
+	long Stf2; ///< Sposób działania strefy 2
+	long Stf3; ///< Sposób działania strefy 3
+	long Stf4; ///< Sposób działania strefy 4
+	long Stf5; ///< Sposób działania strefy 5
+};
+
+int ZDistL_initlog_komp(void *arguments, void *logic)
+{
+	struct ZDistL_args_komp *args = (struct ZDistL_args_komp *)arguments;
+	struct ZDistL_logic_komp *log = (struct ZDistL_logic_komp *)logic;
+	struct ZDistL_nast_komp znast;
+
+	if(set_bit_ptr_struct(args->io.stan_bl_in,&log->stan_bl))
+		return -1;
+	if(set_pointer_in_ptr(args->io.we_zdist_ptr_in,(u32 *)&log->WE_Zdist))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Bl_PS_in,&log->Bl_PS))
+		return -1;	
+	if(set_bit_ptr_struct(args->io.lacze_OK_in,&log->lacze_OK))
+		return -1;
+	if(set_bit_ptr_struct(args->io.lacze_odb_in,&log->lacze_odb))
+		return -1;
+	if(set_bit_ptr_struct(args->io.W_ON_in,&log->W_ON))
+		return -1;
+	if(set_bit_ptr_struct(args->io.zgoda_1f_in,&log->zgoda_1f))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z_in,&log->Z))
+		return -1;
+	if(set_bit_ptr_struct(args->io.test_in,&log->test))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blok_1_in,&log->blok_1))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blok_1W_in,&log->blok_1W))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blok_2_in,&log->blok_2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blok_3_in,&log->blok_3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blok_4_in,&log->blok_4))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blok_5_in,&log->blok_5))
+		return -1;
+	if(set_bit_ptr_struct(args->io.deakt_in,&log->deakt))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.P_out,&log->P))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1W_out,&log->P1W))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P1_out,&log->P1))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P2_out,&log->P2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P3_out,&log->P3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P4_out,&log->P4))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P5_out,&log->P5))
+		return -1;
+	if(set_bit_ptr_struct(args->io.R_out,&log->R))
+		return -1;
+	if(set_bit_ptr_struct(args->io.S_out,&log->S))
+		return -1;
+	if(set_bit_ptr_struct(args->io.T_out,&log->T))
+		return -1;
+	if(set_bit_ptr_struct(args->io.E_out,&log->E))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z1W_out,&log->Z1W))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z1_out,&log->Z1))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z2_out,&log->Z2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z3_out,&log->Z3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z4_out,&log->Z4))
+		return -1;
+	if(set_bit_ptr_struct(args->io.Z5_out,&log->Z5))
+		return -1;
+	if(set_bit_ptr_struct(args->io.W_out,&log->W))
+		return -1;
+	if(set_bit_ptr_struct(args->io.W1_out,&log->W1))
+		return -1;
+	if(set_bit_ptr_struct(args->io.W2_out,&log->W2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.W3_out,&log->W3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.bl_LRC_out,&log->bl_LRC))
+		return -1;	
+	if(set_bit_ptr_struct(args->io.log_odbl_out,&log->log_odbl))
+		return -1;
+	if(set_bit_ptr_struct(args->io.lacze_nad_out,&log->lacze_nad))
+		return -1;
+	if(set_bit_ptr_struct(args->io.zzw_akt_out,&log->zzw_akt))
+		return -1;
+	if(set_bit_ptr_struct(args->io.blk_lacz_out,&log->blk_lacz))
+		return -1;
+	if(set_bit_ptr_struct(args->io.zadz_echa_out,&log->zadz_echa))
+		return -1;	
+	if(set_bit_ptr_struct(args->io.zezw_lacz_out,&log->zezw_lacz))
+		return -1;
+	if(set_bit_ptr_struct(args->io.skr_czas_lacz_out,&log->skr_czas_lacz))
+		return -1;
+	if(set_bit_ptr_struct(args->io.wyl_lacz_out,&log->wyl_lacz))
+		return -1;	
+	if(set_bit_ptr_struct(args->io.blok_lacz_out,&log->blok_lacz))
+		return -1;
+	if(set_bit_ptr_struct(args->io.wydl_czas_lacz_out,&log->wydl_czas_lacz))
+		return -1;	
+	if(set_bit_ptr_struct(args->io.z_zwarcie_out,&log->z_zwarcie))
+		return -1;				
+
+	if(set_bit_ptr_struct(args->io.P_L1_out,&log->P_L1))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P_L2_out,&log->P_L2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P_L3_out,&log->P_L3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.P_E_out,&log->P_E))
+		return -1;
+	
+	if(set_bit_ptr_struct(args->io.WS1_out,&log->WS1))
+		return -1;
+	if(set_bit_ptr_struct(args->io.WS1W_out,&log->WS1W))
+		return -1;
+	if(set_bit_ptr_struct(args->io.WS2_out,&log->WS2))
+		return -1;
+	if(set_bit_ptr_struct(args->io.WS3_out,&log->WS3))
+		return -1;
+	if(set_bit_ptr_struct(args->io.WS4_out,&log->WS4))
+		return -1;
+	if(set_bit_ptr_struct(args->io.WS5_out,&log->WS5))
+		return -1;
+
+	if(set_bit_ptr_struct(args->io.W_1f_out,&log->W_1f))
+		return -1;
+	
+	log->nast_.echo_on = (args->params.bity & 0x0001)?1:0;
+	log->nast_.wyl_od_echa = (args->params.bity & 0x0002)?1:0;
+	log->nast_.log_odbl_on = (args->params.bity & 0x0004)?1:0;
+	log->nast_.LCR_on = (args->params.bity & 0x0008)?1:0;
+	log->nast_.Bl_PS[1] = (args->params.bity & 0x0010)?1:0;
+	log->nast_.Bl_PS[2] = (args->params.bity & 0x0020)?1:0;
+	log->nast_.Bl_PS[3] = (args->params.bity & 0x0040)?1:0;
+	log->nast_.Bl_PS[4] = (args->params.bity & 0x0080)?1:0;
+	log->nast_.Bl_PS[5] = (args->params.bity & 0x0100)?1:0;
+	log->nast_.ZZw_ON = (args->params.bity & 0x0200)?1:0;
+	log->nast_.bl_ = (args->params.bity & 0x0400)?1:0;
+	log->nast_.LRC_s[0] = (args->params.bity & 0x0800)?1:0;
+	log->nast_.LRC_s[1] = (args->params.bity & 0x1000)?1:0;
+	log->nast_.LRC_s[2] = (args->params.bity & 0x2000)?1:0;
+	log->nast_.LRC_s[3] = (args->params.bity & 0x4000)?1:0;
+	log->nast_.LRC_s[4] = (args->params.bity & 0x8000)?1:0;
+	log->nast_.LRC_s[5] = (args->params.bity & 0x10000)?1:0;
+	log->nast_.lacze_on = (args->params.bity & 0x20000)?1:0;
+	log->nast_.zgoda_1faz_s[0] = (args->params.bity & 0x40000)?1:0;
+	log->nast_.zgoda_1faz_s[1] = (args->params.bity & 0x80000)?1:0;
+	log->nast_.zgoda_1faz_s[2] = (args->params.bity & 0x100000)?1:0;
+	log->nast_.zgoda_1faz_s[3] = (args->params.bity & 0x200000)?1:0;
+	log->nast_.zgoda_1faz_s[4] = (args->params.bity & 0x400000)?1:0;
+	log->nast_.zgoda_1faz_s[5] = (args->params.bity & 0x800000)?1:0;
+	log->nast_.Bl_PS[0] = (args->params.bity & 0x1000000)?1:0;	
+	log->nast_.rozwij = (args->params.bity & 0x2000000)?1:0;
+	log->nast_.kryt_IU_ZZW =  (args->params.bity & 0x4000000)?1:0;
+	
+#define POPRAWKA_1 (0)//	(args->params.bity & 0x08000000)
+#define POPRAWKA_2 (0)//	(args->params.bity & 0x10000000)
+#define POPRAWKA_3 (0)//	(args->params.bity & 0x20000000)
+#define POPRAWKA_4 (1)//	(args->params.bity & 0x40000000)
+#define POPRAWKA_5 (0)//	(args->params.bity & 0x80000000)
+
+	log->nast_.ZdistA = log->WE_Zdist;
+
+	unsigned short i;
+
+	znast.ts0LE=args->params.ts1LE;///< Czas wyłączenia strefy 1W zwarcia jednofazowe z ziemią
+	znast.ts0LL=args->params.ts1LL;///< Czas wyłączenia strefy 1W zwarcia miedzyfazowe
+	znast.ts1LE=args->params.ts1LE;///< Czas wyłączenia strefy 1 zwarcia jednofazowe z ziemią
+	znast.ts1LL=args->params.ts1LL;///< Czas wyłączenia strefy 1 zwarcia miedzyfazowe
+	znast.ts2LE=args->params.ts2LE;///< Czas wyłączenia strefy 2 zwarcia jednofazowe z ziemią
+	znast.ts2LL=args->params.ts2LL;///< Czas wyłączenia strefy 2 zwarcia miedzyfazowe
+	znast.ts3LE=args->params.ts3LE;///< Czas wyłączenia strefy 3 zwarcia jednofazowe z ziemią
+	znast.ts3LL=args->params.ts3LL;///< Czas wyłączenia strefy 3 zwarcia miedzyfazowe
+	znast.ts4LE=args->params.ts4LE;///< Czas wyłączenia strefy 4 zwarcia jednofazowe z ziemią
+	znast.ts4LL=args->params.ts4LL;///< Czas wyłączenia strefy 4 zwarcia miedzyfazowe
+	znast.ts5LE=args->params.ts5LE;///< Czas wyłączenia strefy 5 zwarcia jednofazowe z ziemią
+	znast.ts5LL=args->params.ts5LL;///< Czas wyłączenia strefy 5 zwarcia miedzyfazowe
+	
+	znast.Stf0=args->params.Stf0;
+	znast.Stf1=args->params.Stf1;
+	znast.Stf2=args->params.Stf2;
+	znast.Stf3=args->params.Stf3;
+	znast.Stf4=args->params.Stf4;
+	znast.Stf5=args->params.Stf5;
+	
+	log->nast_.tryb_lacza = (enum _tryb_lacza)args->params.tryb_lacza;
+	log->nast_.tryb_zezw = (enum _tryb_zezwalajacy)args->params.tryb_zezw;
+	log->nast_.tryb_blok = (enum _tryb_blokujacy)args->params.tryb_blokujacy;
+	
+	log->nast_.ktora_strefa = args->params.strefa_dzial;
+	log->nast_.ktora_strefa_nad = args->params.strefa_nad;
+	log->nast_.strefa_pradu_wstecznego = args->params.lrc_strefa;
+	
+	log->dw.blok_lacza[0] = 0;		
+	log->dw.blok_lacza[1] = 0;
+	log->dw.blok_lacza[2] = 0;
+	log->dw.blok_lacza[3] = 0;
+	log->dw.blok_lacza[4] = 0;
+	log->dw.blok_lacza[5] = 0;
+
+	log->dw.wydl_czas = 0;
+	log->dw.wylacz_od_lacza = 0;
+	log->dw.wylacz_od_echa = 0;
+	log->dw.wylacz_od_lacza_suma = 0;
+	
+	log->dw.wy_bl_LRC = 0;
+	log->dw.wy_log_odbl = 0;
+	log->dw.wy_lacze_nad = 0;
+	
+	log->dw.wy_blk_lacz = 0;
+	
+	log->dw.wy_zadz_echa = 0;
+	log->dw.wy_zezw_lacz = 0;
+	log->dw.wy_skr_czas_lacz = 0; 
+	log->dw.wy_wyl_lacz = 0;  
+	log->dw.wy_blok_lacz = 0;
+	log->dw.wy_wydl_czas_lacz = 0;
+	
+	log->dw.dodaj_rozw[0] = 0;
+	log->dw.dodaj_rozw[1] = 0;
+	log->dw.dodaj_rozw[2] = 0;
+	log->dw.dodaj_rozw[3] = 0;
+	log->dw.dodaj_rozw[4] = 0;
+	log->dw.dodaj_rozw[5] = 0;
+
+	log->dw.ZZwP = 0;
+	
+	if (log->nast_.tryb_lacza == ZEZWALAJACY && log->nast_.tryb_zezw == ZGODA)
+	{
+		log->dw.blok_lacza[log->nast_.ktora_strefa] = 1;	
+	}	
+	
+		if (args->params.ts0LE < 0.01)
+		{
+			log->nast_.Zbz[0][0] = 1; 	
+			log->nast_.t_stf[0][0] = 0;
+		
+		}
+		else
+		{		
+			log->nast_.Zbz[0][0] = 0; 	
+			log->nast_.t_stf[0][0] = (int16_t)(100 * (args->params.ts0LE - 0.01f));
+      
+			if (log->nast_.t_stf[0][0] < 0) log->nast_.t_stf[0][0] = 0;   
+		}
+				
+		if (args->params.ts0LL < 0.01)
+		{
+			log->nast_.Zbz[0][1] = 1; 	
+			log->nast_.t_stf[0][1] = 0;
+		}
+		else
+		{		
+			log->nast_.Zbz[0][1] = 0;
+			log->nast_.t_stf[0][1] = (int16_t)(100 * (args->params.ts0LL - 0.01f));
+
+			if (log->nast_.t_stf[0][1] < 0) log->nast_.t_stf[0][1] = 0; 
+		}
+		
+					
+		if (args->params.ts1LE < 0.01)
+		{
+			log->nast_.Zbz[1][0] = 1; 	
+			log->nast_.t_stf[1][0] = 0;		
+		}
+		else
+		{
+			log->nast_.Zbz[1][0] = 0; 	
+			log->nast_.t_stf[1][0] = (int16_t)(100 * (args->params.ts1LE - 0.01f));
+
+			if (log->nast_.t_stf[1][0] < 0) log->nast_.t_stf[1][0] = 0; 
+		}
+
+		if (args->params.ts1LL < 0.01)
+		{
+			log->nast_.Zbz[1][1] = 1; 	
+			log->nast_.t_stf[1][1] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[1][1] = 0;
+			log->nast_.t_stf[1][1] = (int16_t)(100 * (args->params.ts1LL - 0.01f));
+
+			if (log->nast_.t_stf[1][1] < 0) log->nast_.t_stf[1][1] = 0; 		
+		}
+		
+		
+		if (args->params.ts2LE < 0.01)
+		{
+			log->nast_.Zbz[2][0] = 1; 	
+			log->nast_.t_stf[2][0] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[2][0] = 0;
+			log->nast_.t_stf[2][0] = (int16_t)(100 * (args->params.ts2LE - 0.01f));
+
+			if (log->nast_.t_stf[2][0] < 0) log->nast_.t_stf[2][0] = 0; 
+		}
+
+		if (args->params.ts2LL < 0.01)
+		{
+			log->nast_.Zbz[2][1] = 1; 	
+			log->nast_.t_stf[2][1] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[2][1] = 0;
+			log->nast_.t_stf[2][1] = (int16_t)(100 * (args->params.ts2LL - 0.01f));
+
+			if (log->nast_.t_stf[2][1] < 0) log->nast_.t_stf[2][1] = 0; 
+		}
+
+		if (args->params.ts3LE < 0.01)
+		{
+			log->nast_.Zbz[3][0] = 1; 	
+			log->nast_.t_stf[3][0] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[3][0] = 0;
+			log->nast_.t_stf[3][0] = (int16_t)(100 * (args->params.ts3LE - 0.01f));
+
+			if (log->nast_.t_stf[3][0] < 0) log->nast_.t_stf[3][0] = 0; 
+		}
+
+		if (args->params.ts3LL < 0.01)
+		{
+			log->nast_.Zbz[3][1] = 1; 	
+			log->nast_.t_stf[3][1] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[3][1] = 0;
+			log->nast_.t_stf[3][1] = (int16_t)(100 * (args->params.ts3LL - 0.01f));
+
+			if (log->nast_.t_stf[3][1] < 0) log->nast_.t_stf[3][1] = 0; 
+		}
+
+		if (args->params.ts4LE < 0.01)
+		{
+			log->nast_.Zbz[4][0] = 1; 	
+			log->nast_.t_stf[4][0] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[4][0] = 0;
+			log->nast_.t_stf[4][0] = (int16_t)(100 * (args->params.ts4LE - 0.01f));
+
+			if (log->nast_.t_stf[4][0] < 0) log->nast_.t_stf[4][0] = 0; 
+		}
+
+		if (args->params.ts4LL < 0.01)
+		{
+			log->nast_.Zbz[4][1] = 1; 	
+			log->nast_.t_stf[4][1] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[4][1] = 0;
+			log->nast_.t_stf[4][1] = (int16_t)(100 * (args->params.ts4LL - 0.01f));
+
+			if (log->nast_.t_stf[4][1] < 0) log->nast_.t_stf[4][1] = 0; 
+		}
+
+
+		if (args->params.ts5LE < 0.01)
+		{
+			log->nast_.Zbz[5][0] = 1; 	
+			log->nast_.t_stf[5][0] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[5][0] = 0;
+			log->nast_.t_stf[5][0] = (int16_t)(100 * (args->params.ts5LE - 0.01f));
+
+			if (log->nast_.t_stf[5][0] < 0) log->nast_.t_stf[5][0] = 0; 
+		}
+
+		if (args->params.ts5LL < 0.01)
+		{
+			log->nast_.Zbz[5][1] = 1; 	
+			log->nast_.t_stf[5][1] = 0;
+		}
+		else
+		{
+			log->nast_.Zbz[5][1] = 0;
+			log->nast_.t_stf[5][1] = (int16_t)(100 * (args->params.ts5LL - 0.01f));
+
+			if (log->nast_.t_stf[5][1] < 0) log->nast_.t_stf[5][1] = 0; 
+		}
+	
+	
+	log->nast_.ZZw_st = args->params.ZZw_st;
+
+	switch(log->nast_.ZZw_st)
+	{
+		case 0:
+			log->PZZw=log->P1W;
+			log->ZZZw=log->Z1W;
+			break;
+		case 1:
+			log->PZZw=log->P1;
+			log->ZZZw=log->Z1;
+			break;
+		case 2:
+			log->PZZw=log->P2;
+			log->ZZZw=log->Z2;
+			break;
+		case 3:
+			log->PZZw=log->P3;
+			log->ZZZw=log->Z3;
+			break;
+		case 4:
+			log->PZZw=log->P4;
+			log->ZZZw=log->Z4;
+			break;
+		case 5:
+			log->PZZw=log->P5;
+			log->ZZZw=log->Z5;
+			break;
+		default:
+			log->PZZw=log->P1W;
+			log->ZZZw=log->Z1W;
+			break;
+	}
+
+	long *temp_e = &znast.Stf0;
+
+	for (i=0;i<6;i++)
+	{
+
+		//ustawienie bitow sposobu dzialania stref
+		switch (*(temp_e))
+		{
+			case 0:
+				log->nast_.Stf_ON[i] = 0;
+				log->nast_.Stf_W[i] = 0;
+				break;
+			case 1:
+				log->nast_.Stf_ON[i] = 1;
+				log->nast_.Stf_W[i] = 0;
+				break;
+			case 2:
+				log->nast_.Stf_ON[i] = 1;
+				log->nast_.Stf_W[i] = 1;
+				break;
+			default:
+				break;
+		}
+		temp_e++;
+
+		//--------------------------
+	}
+	
+	log->nast_.ZZw_ta = (short)(100 * (args->params.ZZw_ta + 0.005f));
+	log->nast_.ZZw_to = (short)(100 * (args->params.ZZw_to + 0.005f));
+
+	log->nast_.ZZw_Ir = args->params.ZZw_Ir * args->params.ZZw_Ir;
+	log->nast_.ZZw_Ur = args->params.ZZw_Ur * args->params.ZZw_Ur;
+
+	log->nast_.Uecho_pob = args->params.U_echa * args->params.U_echa;
+	log->nast_.Uecho_odp = 1.02 * 1.02 * log->nast_.Uecho_pob;
+
+	log->nast_.t_LRC = (int16_t)(100 * (args->params.t_LRC + 0.005f));
+	log->nast_.t_lacze_nad = (int16_t)(100 * (args->params.t_lacze_nad + 0.005f));
+	log->nast_.t_pod_odbl = (int16_t)(100 * (args->params.t_pod_odbl + 0.005f));
+	
+	log->nast_.ts_plus = (int16_t)(100 * (args->params.ts_plus - 0.01f));
+	if (log->nast_.ts_plus < 0) log->nast_.ts_plus = 0;
+		
+	log->nast_.czas_wyl_echa =  (int16_t)(100 * (args->params.czas_wyl_echa + 0.005f));;
+	log->nast_.max_t_nadawania =  (int16_t)(100 * (args->params.max_t_nadawania + 0.005f));
+
+	for (i = 0; i < 6; i++)
+	{
+		log->dw.Pf[i][0] = 0;
+		log->dw.Pf[i][1] = 0;
+		log->dw.Zf[i][0] = 0;
+		log->dw.Zf[i][1] = 0;
+		
+		log->dw.Pzf[i] = 0;
+		log->dw.Z[i] = 0;
+		log->dw.Ws[i] = 0;
+		
+		log->dw.blok_LRC[i] = 0;
+    
+    log->dw.liczt_eldz[i][0] = 0;
+    log->dw.liczt_eldz[i][1] = 0;
+    
+    log->dw.liczts_rozwij[i] = 0;
+    log->dw.Zf_rozwij[i] = 0;
+    log->dw.liczt_eldz_rozwij[i] = 0;
+    //liczts_rozwij
+    
+	}
+	log->dw.lacze_odb_old = 0;
+	log->dw.skrocil_strefa = 0; 
+	log->dw.skrocil_echo = 0; 
+
+	 for (i = 0; i < 6; i++)
+	 {
+		log->P_L1_lub_L2[i] = 0;
+		log->P_L2_lub_L3[i] = 0;
+		log->P_L3_lub_L1[i] = 0;
+	 }
+//
+
+	for (i=0;i<6;i++)
+	{
+		if(log->nast_.Stf_ON[i])
+		{
+			log->WE_Zdist->Zdist_dw->Z_min = log->WE_Zdist->Zdist_dw->modul_zf[i]<log->WE_Zdist->Zdist_dw->Z_min?log->WE_Zdist->Zdist_dw->modul_zf[i]:log->WE_Zdist->Zdist_dw->Z_min;
+			log->WE_Zdist->Zdist_dw->Z_min_mf = log->WE_Zdist->Zdist_dw->modul_zmf[i]<log->WE_Zdist->Zdist_dw->Z_min_mf?log->WE_Zdist->Zdist_dw->modul_zmf[i]:log->WE_Zdist->Zdist_dw->Z_min_mf;
+		}
+	}
+
+	return 0;
+}
+
+/**
+Funkcja okraślania petli zwarciwej przy wyłaczeniu
+\param nr_strefy - numer strefy wyłaczającej
+*/
+void wybiornik_f_komp(struct ZDistL_logic_komp *log,unsigned short nr_strefy)
+{
+	log->dw.R = log->pobudzenia[nr_strefy][0]
+		|| log->pobudzenia[nr_strefy][3]
+		|| log->pobudzenia[nr_strefy][5];
+
+	log->dw.S = log->pobudzenia[nr_strefy][1]
+		|| log->pobudzenia[nr_strefy][3]
+		|| log->pobudzenia[nr_strefy][4];
+
+	log->dw.T = log->pobudzenia[nr_strefy][2]
+		|| log->pobudzenia[nr_strefy][4]
+		|| log->pobudzenia[nr_strefy][5];
+
+	log->dw.E = log->nast_.ZdistA->Zdist_dw->Iogr;
+
+	log->dw.jedfaz = (log->dw.R && !(log->dw.S||log->dw.T))
+				|| (log->dw.S && !(log->dw.T||log->dw.R))
+				|| (log->dw.T && !(log->dw.R||log->dw.S))
+				|| (!log->dw.R && !log->dw.S && !log->dw.T); //zeby po wyl 1 fazowym nie robil na krotko 3 faz
+}
+
+/**
+Funkcja okraślania petli zwarciwej przy wyłaczeniu - działanie bezkierunkowe
+\param nr_strefy - numer strefy wyłaczającej
+*/
+
+void wybiornik_fbk_komp(struct ZDistL_logic_komp *log, unsigned short nr_strefy)
+{
+	log->dw.Rbk = log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][0]
+		|| log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][3]
+		|| log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][5];
+
+	log->dw.Sbk = log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][1]
+		|| log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][3]
+		|| log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][4];
+
+	log->dw.Tbk = log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][2]
+		|| log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][4]
+		|| log->nast_.ZdistA->Zdist_dw->Pbk[nr_strefy][5];
+
+	log->dw.E = log->nast_.ZdistA->Zdist_dw->Iogr;
+}
+
+
+void
+wylacz_P_komp(struct ZDistL_logic_komp *log, u8 zgoda_1f)
+{
+int i;
+
+	for(i=0;i<6;i++)
+	{
+		if (log->dw.Ws[i])
+		{
+			wybiornik_f_komp(log,i);
+	
+			if(log->dw.jedfaz && zgoda_1f && log->nast_.zgoda_1faz_s[i])
+			{
+				if(log->dw.R)
+          			log->dw.W1 = 1;
+        		if(log->dw.S)
+         			log->dw.W2 = 1;
+        		if(log->dw.T)
+          			log->dw.W3 = 1;
+			
+				log->dw.wyl_1f = 1;
+			} 
+			else
+			{
+				log->dw.W1 = log->dw.W2 = log->dw.W3 = log->dw.W = 1;				
+			}						
+		}		
+	}
+	
+	if (log->dw.wylacz_od_lacza_suma == 1)
+	{
+		log->dw.W1 = log->dw.W2 = log->dw.W3 = log->dw.W = 1;			
+	}
+}
+
+
+void ZDistL_komp(void *arguments, void *logic)
+{
+	struct ZDistL_logic_komp *log = (struct ZDistL_logic_komp *)logic;
+	struct ZDistL_args_komp *args = (struct ZDistL_args_komp *)arguments;
+	
+	u16 i,j;
+	log->dw.P = 0;
+	log->dw.Zz = 0;
+
+	u8 temp_Bl,temp_Zezwolenie, pob_zab_echo;
+
+	u8 we_stan_bl =  check_struct(&log->stan_bl)?1:0;
+	u8 we_Bl_PS =  check_struct(&log->Bl_PS)?1:0;
+	u8 we_lacze_OK = check_struct(&log->lacze_OK)?1:0;
+	u8 we_lacze_odb = check_struct(&log->lacze_odb)?1:0;
+	u8 we_zgoda_1f = check_struct(&log->zgoda_1f)?1:0;
+	u8 we_test = check_struct(&log->test)?1:0;
+	u8 we_Z =  check_struct(&log->Z)?1:0;
+	u8 b_blok[6];
+	
+	b_blok[0] = check_struct(&log->blok_1W)?1:0;;
+	b_blok[1] = check_struct(&log->blok_1)?1:0;;
+	b_blok[2] = check_struct(&log->blok_2)?1:0;;
+	b_blok[3] = check_struct(&log->blok_3)?1:0;;
+	b_blok[4] = check_struct(&log->blok_4)?1:0;;
+	b_blok[5] = check_struct(&log->blok_5)?1:0;;
+
+//	u8 poprawka_pawla[6] = {0,0,0,0,0,0};
+
+	if (*log->nast_.ZdistA->on && !(check_struct(&log->deakt)))
+	{
+		//**************\/********* Poprawka na bledne wylaczenie 3 fazowe przy zwarciu 1 fazowym ************\/***************************
+
+		#define L1 0
+		#define L2 1
+		#define L3 2
+		#define L1L2 3
+		#define L2L3 4
+		#define L3L1 5
+		#define faz_0_85 0.24f
+		u8 UL1, UL2, UL3;
+
+		#define st_075kw 0.5625f
+		#define st_133kw 1.7689f
+		u8 IL1L2, IL2L3, IL3L1;
+
+		//kryteria podanpięciowe
+		if (log->nast_.ZdistA->Zdist_dw->U1 < faz_0_85)
+			UL1 = 1;
+		else
+			UL1 = 0;
+
+		if (log->nast_.ZdistA->Zdist_dw->U2 < faz_0_85)
+			UL2 = 1;
+		else
+			UL2 = 0;
+
+		if (log->nast_.ZdistA->Zdist_dw->U3 < faz_0_85)
+			UL3 = 1;
+		else
+			UL3 = 0;
+
+		//kryteria prądowe
+		if (log->nast_.ZdistA->Zdist_dw->I1 > 0.1) //zeby nie dzielic przez 0
+		{
+			float k  = log->nast_.ZdistA->Zdist_dw->I2/ log->nast_.ZdistA->Zdist_dw->I1;
+				if ((k > st_075kw) && (k < st_133kw))
+					IL1L2 = 1;
+				else
+					IL1L2 = 0;
+		}
+		else
+			IL1L2 = 0;
+
+		if (log->nast_.ZdistA->Zdist_dw->I2 > 0.1) //zeby nie dzielic przez 0
+		{
+			float k  = log->nast_.ZdistA->Zdist_dw->I3/ log->nast_.ZdistA->Zdist_dw->I2;
+				if ((k > st_075kw) && (k < st_133kw))
+					IL2L3 = 1;
+				else
+					IL2L3 = 0;
+		}
+		else
+			IL2L3 = 0;
+
+		if (log->nast_.ZdistA->Zdist_dw->I3 > 0.1) //zeby nie dzielic przez 0
+		{
+			float k  = log->nast_.ZdistA->Zdist_dw->I1/ log->nast_.ZdistA->Zdist_dw->I3;
+				if ((k > st_075kw) && (k < st_133kw))
+					IL3L1 = 1;
+				else
+					IL3L1 = 0;
+		}
+		else
+			IL3L1 = 0;
+
+
+		//kryteria pobudzenia doziemnego jednofazowego w opoznieniem odpadu
+		for (i=0; i<6; i++)
+		{
+
+			if((log->nast_.ZdistA->Zdist_dw->P[i][L1]) || (log->nast_.ZdistA->Zdist_dw->P[i][L2]))
+			{
+				log->P_L1_lub_L2[i] = 3;
+			}
+			else
+			{
+				if (log->P_L1_lub_L2[i] > 0)
+					log->P_L1_lub_L2[i]--;
+
+			}
+
+			if ((log->nast_.ZdistA->Zdist_dw->P[i][L2]) || (log->nast_.ZdistA->Zdist_dw->P[i][L3]))
+			{
+				log->P_L2_lub_L3[i] = 3;
+			}
+			else
+			{
+				if (log->P_L2_lub_L3[i] > 0)
+					log->P_L2_lub_L3[i]--;
+			}
+
+			if ((log->nast_.ZdistA->Zdist_dw->P[i][L3]) || (log->nast_.ZdistA->Zdist_dw->P[i][L1]))
+			{
+				log->P_L3_lub_L1[i] = 3;
+			}
+			else
+			{
+				if (log->P_L3_lub_L1[i] > 0)
+					log->P_L3_lub_L1[i]--;
+			}
+
+			for (j=0; j<3; j++)
+			{
+				log->pobudzenia[i][j] = log->nast_.ZdistA->Zdist_dw->P[i][j];
+			}
+
+			//blokowanie pobudzen miedzyfazowych gdy strefa moze wylaczyc 1-fazowo a napiecia nie przysiadly
+
+			if (((/*we_zgoda_1f && */log->nast_.zgoda_1faz_s[i]) && (log->nast_.ZdistA->Zdist_dw->P[i][L1L2]) && (log->P_L1_lub_L2[i] > 0) && !POPRAWKA_2)
+			|| (POPRAWKA_2 && ((log->nast_.ZdistA->Zdist_dw->P[i][L1L2]) && ((log->nast_.ZdistA->Zdist_dw->P[1][L1]) || (log->nast_.ZdistA->Zdist_dw->P[1][L2]))  && (log->P_L1_lub_L2[i] > 0)))
+			)
+			{
+				if ((UL1 && UL2) || (IL1L2))
+					log->pobudzenia[i][L1L2] = 1;
+				else
+				{
+
+	//				poprawka_pawla[i]=1;
+					log->pobudzenia[i][L1L2] = POPRAWKA_4?0:1;
+				}
+			}
+			else
+				log->pobudzenia[i][L1L2] = log->nast_.ZdistA->Zdist_dw->P[i][L1L2];
+
+
+			if (((/*we_zgoda_1f && */log->nast_.zgoda_1faz_s[i]) && (log->nast_.ZdistA->Zdist_dw->P[i][L2L3]) && (log->P_L2_lub_L3[i] > 0) && !POPRAWKA_2)
+			|| (POPRAWKA_2 && ((log->nast_.ZdistA->Zdist_dw->P[i][L2L3]) && ((log->nast_.ZdistA->Zdist_dw->P[1][L2]) || (log->nast_.ZdistA->Zdist_dw->P[1][L3]))  && (log->P_L2_lub_L3[i] > 0))))
+			{
+				if ((UL2 && UL3) || (IL2L3))
+					log->pobudzenia[i][L2L3] = 1;
+				else
+				{
+//					poprawka_pawla[i]=1;
+					log->pobudzenia[i][L2L3] = POPRAWKA_4?0:1;
+				}
+			}
+			else
+				log->pobudzenia[i][L2L3] = log->nast_.ZdistA->Zdist_dw->P[i][L2L3];
+
+			if (((/*we_zgoda_1f && */log->nast_.zgoda_1faz_s[i]) && (log->nast_.ZdistA->Zdist_dw->P[i][L3L1]) && (log->P_L3_lub_L1[i] > 0) && !POPRAWKA_2)
+			|| (POPRAWKA_2 && ((log->nast_.ZdistA->Zdist_dw->P[i][L3L1]) && ((log->nast_.ZdistA->Zdist_dw->P[1][L3]) || (log->nast_.ZdistA->Zdist_dw->P[1][L1]))  && (log->P_L3_lub_L1[i] > 0))))
+			{
+				if ((UL3 && UL1) || (IL3L1))
+					log->pobudzenia[i][L3L1] = 1;
+				else
+				{
+	//				poprawka_pawla[i]=1;
+					log->pobudzenia[i][L3L1] = POPRAWKA_4?0:1;
+				}
+			}
+			else
+				log->pobudzenia[i][L3L1] = log->nast_.ZdistA->Zdist_dw->P[i][L3L1];
+
+		}
+		//*************/\******** Poprawka na bledne wylaczenie 3 fazowe przy zwarciu 1 fazowym ***************/\***********************
+	
+	//Lacze
+	
+	if ((log->nast_.tryb_lacza == BLOKUJACY) && (log->nast_.tryb_blok == BLOKUJ_PRZEKAZNIK) && (we_lacze_odb == 1) && (we_lacze_OK))
+	{
+		log->dw.wy_blk_lacz = 1;		
+	}
+	else
+	{
+		log->dw.wy_blk_lacz = 0;
+	}
+	
+	
+	if (log->nast_.tryb_lacza == ZEZWALAJACY) 
+	{
+
+			 if (log->nast_.tryb_zezw == ZGODA )
+			 {		 
+				 if (((we_lacze_odb == 1)&& (we_lacze_OK)) || (log->dw.logika_dblokowania))
+				 {
+				 	log->dw.blok_lacza[log->nast_.ktora_strefa] = 0;
+				 	log->dw.wy_zezw_lacz = 1;	
+				 }
+				 else
+				 {
+					 log->dw.blok_lacza[log->nast_.ktora_strefa] = 1;
+					 log->dw.wy_zezw_lacz = 0;		
+				 }		 
+			 }
+			 else if (log->nast_.tryb_zezw == SKROC_CZAS)
+			 {
+			 	 if ((we_lacze_odb == 1)&& (we_lacze_OK))
+			 	 {
+					log->dw.liczts[log->nast_.ktora_strefa][0] = 0;		 	
+				 	log->dw.liczts[log->nast_.ktora_strefa][1] = 0;	
+				 	log->dw.wy_skr_czas_lacz = 1;
+			 	 }
+			 	 else
+			 	 {
+			 	 	log->dw.wy_skr_czas_lacz = 0;
+			 	 }	 	
+			 }
+			 else if (log->nast_.tryb_zezw == WYLACZ)
+			 {
+				if ((we_lacze_odb == 1)&& (we_lacze_OK) && !we_stan_bl)
+			 	{
+			 		log->dw.wylacz_od_lacza = 1;
+			 		log->dw.wy_wyl_lacz = 1;		 	
+			 	}
+			 	else
+			 	{
+			 		log->dw.wylacz_od_lacza = 0;
+			 		log->dw.wy_wyl_lacz = 0;	
+			 	}
+			 
+		 	}
+	}
+	else if (log->nast_.tryb_lacza == BLOKUJACY)//tryb blokujący
+	{
+		 	if (log->nast_.tryb_blok == BLOKUJ)
+		 	{
+			 	 if ((we_lacze_odb == 1)&& (we_lacze_OK))
+				 {
+				 	log->dw.blok_lacza[log->nast_.ktora_strefa] = 1;
+				 	log->dw.wy_blok_lacz = 1;	
+				 }
+				 else
+				 {
+					log-> dw.blok_lacza[log->nast_.ktora_strefa] = 0;
+					log->dw.wy_blok_lacz = 0;		
+				 }
+		 	}
+		 	else if (log->nast_.tryb_blok == WYDLUZ_CZAS)
+		 	{
+		 		if ((we_lacze_odb == 1)&& (we_lacze_OK))
+				{
+					log->dw.wy_wydl_czas_lacz = 1;
+				}
+				else
+				{
+					log->dw.wy_wydl_czas_lacz = 0;	
+				}	
+		 		
+		 		//funkcja wykonywana jest w kodzie ponizej
+		 	}
+		 	else if (log->nast_.tryb_blok == BLOKUJ_PRZEKAZNIK)
+		 	{
+		 		
+		 	}	 			 	
+	}
+	else //tryb wylaczony
+	{
+			log->dw.blok_lacza[0] = 0;		
+			log->dw.blok_lacza[1] = 0;
+			log->dw.blok_lacza[2] = 0;
+			log->dw.blok_lacza[3] = 0;
+			log->dw.blok_lacza[4] = 0;
+			log->dw.blok_lacza[5] = 0;	
+	}
+	//-------------------------------------------------------------------------
+	
+	//logika pradu wstecznego
+
+	if ((log->dw.Pzf[log->nast_.strefa_pradu_wstecznego] == 1) && (log->nast_.LCR_on))
+	{
+		log->dw.blokada_pradu_wstecznego = 1;
+		log->dw.t_pod_blok_wst = log->nast_.t_LRC;
+		log->dw.wy_bl_LRC = 1;
+	}
+	
+	if (log->dw.blokada_pradu_wstecznego == 1)
+	{
+		for (i = 0; i < 6; i++)
+		{
+			if (log->nast_.LRC_s[i] == 1)
+				log->dw.blok_LRC[i] = 1;				
+		}		
+	}	
+	else
+	{
+		for (i = 0; i < 6; i++)
+			log->dw.blok_LRC[i] = 0;				
+	}
+		
+	//-------------------------------------------------------------------------
+	//logika słabego zasialnia - echa
+
+	pob_zab_echo = 0;
+		
+	u8 U_echo_pob_b = log->nast_.ZdistA->Zdist_dw->U1 < log->nast_.Uecho_pob ||
+		log->nast_.ZdistA->Zdist_dw->U2 <log->nast_.Uecho_pob ||
+		log->nast_.ZdistA->Zdist_dw->U3 <log->nast_.Uecho_pob;
+		
+	u8 U_echo_odp_b = log->nast_.ZdistA->Zdist_dw->U1 > log->nast_.Uecho_odp &&
+		log->nast_.ZdistA->Zdist_dw->U2 > log->nast_.Uecho_odp &&
+		log->nast_.ZdistA->Zdist_dw->U3 > log->nast_.Uecho_odp;	
+	
+	sprawdz_P(&log->dw.pob_echo, U_echo_pob_b, U_echo_odp_b, &log->dw.licznik_Uecho, 3, 3);
+			
+	for (i=0;i<6;i++)
+	{
+		if (log->dw.Pzf[i] != 0)
+			pob_zab_echo = 1;
+	}
+	
+	if (log->nast_.echo_on && !we_stan_bl)
+	{	
+		if (!pob_zab_echo && log->dw.pob_echo && (we_lacze_odb == 1) && (we_lacze_OK == 1))
+		{
+			if ((log->nast_.wyl_od_echa) && (log->dw.wylacz_od_echa == 0))       //poprawka hazardu
+			{
+				log->dw.wylacz_od_echa = 1;	
+				log->dw.t_wyl_od_echa = log->nast_.czas_wyl_echa;
+			}
+			// i odbij echo
+			if (log->dw.skrocil_echo == 0)
+			{
+			log->dw.lacze_nad = 1;
+			log->dw.t_lacze_nad = log->nast_.t_lacze_nad;
+			log->dw.wy_lacze_nad = 1;
+			}
+		}
+	
+		if (log->dw.wylacz_od_echa)
+		{
+			log->dw.wy_zadz_echa = 1;
+		}
+		else
+		{
+			log->dw.wy_zadz_echa = 0;
+		}
+	
+		if (we_lacze_odb == 0)
+			log->dw.skrocil_echo = 0;
+	
+	}
+
+	log->dw.wylacz_od_lacza_suma = log->dw.wylacz_od_lacza || log->dw.wylacz_od_echa;
+	//-------------------------------------------------------------------------
+	//logika odblokowania
+
+	if ((log->nast_.log_odbl_on) && (log->nast_.tryb_lacza == ZEZWALAJACY) && (log->nast_.tryb_zezw == ZGODA))
+	{
+		if ((log->dw.kopia_lacze_ok == 1) && (we_lacze_OK == 0)) //urwanie lacza ok
+		{
+			log->dw.wy_log_odbl = 1;
+			log->dw.logika_dblokowania = 1;
+			log->dw.t_log_odblokowania = log->nast_.t_pod_odbl;
+		}
+	}
+	
+	log->dw.kopia_lacze_ok = we_lacze_OK;
+
+
+		temp_Bl = (we_stan_bl & log->nast_.bl_);
+
+		for (i=0;i<6;i++)
+		{
+			if (log->nast_.Stf_ON[i]) //jesli strefa wlaczona
+			{
+				temp_Zezwolenie = !(temp_Bl  | (log->nast_.Bl_PS[i] & we_Bl_PS));
+
+				if (b_blok[i] == 1)
+					temp_Zezwolenie = 0;
+
+				//obsluga wejscia testu przekaznika	
+				if (czy_test_R()) 
+				{
+					log->dw.Pf[i][0] = log->dw.Pf[i][1] = temp_Zezwolenie & we_test;
+				}
+				else
+				{
+					//ustawienie pobudzen
+					log->dw.Pf[i][0] = (log->pobudzenia[i][0] |
+												log->pobudzenia[i][1] |
+																log->pobudzenia[i][2])
+																	& temp_Zezwolenie;
+					log->dw.Pf[i][1] = (log->pobudzenia[i][3] |
+												log->pobudzenia[i][4] |
+																log->pobudzenia[i][5])
+																	& temp_Zezwolenie;
+				}
+				log->dw.Pzf[i] = log->dw.Pf[i][0] | log->dw.Pf[i][1];
+
+				//ustawienie zadzialan jesli bezzwloczny
+			
+
+                
+				 if ((log->nast_.tryb_lacza == BLOKUJACY) &&  (log->nast_.tryb_blok == WYDLUZ_CZAS) && (log->nast_.ktora_strefa == i))                                      
+				 {
+					 if ((log->dw.Pzf[log->nast_.ktora_strefa] == 1) && (log->dw.wydl_czas == 0) && ( we_lacze_odb == 1) && (we_lacze_OK))
+					 {
+               			log->dw.wydl_czas = 1;		 			
+		 				log->dw.liczts[log->nast_.ktora_strefa][0] += log->nast_.ts_plus;
+		 				log->dw.liczts[log->nast_.ktora_strefa][1] += log->nast_.ts_plus; 
+						log->nast_.Zbz[log->nast_.ktora_strefa][0] = 0;
+						log->nast_.Zbz[log->nast_.ktora_strefa][1] = 0;
+						log->dw.dodaj_rozw[log->nast_.ktora_strefa] = log->nast_.ts_plus;
+					 }
+
+					if  (log->dw.Pzf[log->nast_.ktora_strefa] == 0)
+			 		{
+			 			log->dw.wydl_czas = 0;		 			
+
+						if (log->nast_.t_stf[log->nast_.ktora_strefa][0] < 0.01)
+							log->nast_.Zbz[log->nast_.ktora_strefa][0] = 1;
+						
+						if (log->nast_.t_stf[log->nast_.ktora_strefa][1] < 0.01)
+							log->nast_.Zbz[log->nast_.ktora_strefa][1] = 1;
+			 		}	 	
+				 }
+
+  
+        	if (log->nast_.Zbz[i][0])
+    			{
+    				if (log->dw.Pf[i][0] != 0)            
+              log->dw.Zf[i][0] = 1;
+    			
+          
+          }
+    			if (log->nast_.Zbz[i][1])
+    			{
+    				if (log->dw.Pf[i][1] != 0)
+            log->dw.Zf[i][1] = 1;
+    			}
+
+      
+      
+      	//ustawienie zadzialania strefy
+				log->dw.Z[i] = log->dw.Zf[i][0] | log->dw.Zf[i][1];
+			
+
+			} else {
+				log->dw.Pzf[i] = 0;
+				log->dw.Z[i] = 0;
+			}
+
+			log->dw.P |= log->dw.Pzf[i];
+			log->dw.Zz |= log->dw.Z[i]; //zadzialanie zabezpieczenia
+		}
+
+		//lacze nadawanie
+			if (log->nast_.lacze_on == 0)
+			{
+				log->dw.wy_lacze_nad = 0;
+			}
+			else
+			{
+				if (log->dw.skrocil_strefa == 0)
+				{
+					if ((log->dw.Pzf[log->nast_.ktora_strefa_nad] == 1) && !log->dw.blokada_pradu_wstecznego)
+					{
+						log->dw.lacze_nad = 1;
+						log->dw.t_lacze_nad = log->nast_.t_lacze_nad;
+						log->dw.wy_lacze_nad = 1;
+					}
+				}
+
+				if (log->dw.Pzf[log->nast_.ktora_strefa_nad] == 0)
+				{
+					log->dw.skrocil_strefa = 0; //kasowanie flagi skrocil czas gdy zanikl odpad
+				}
+			}
+
+			//-------------------------------------------------------------------------
+
+		log->dw.lacze_odb_old = we_lacze_odb && we_lacze_OK; //jesli jest jedae ale nie ok to zero
+
+		//-------------------------------------------------------------------------------------------------------
+		//automatyka załaczenia na zwarcie
+
+		if (we_Z && log->nast_.ZZw_ON) {
+			log->dw.ZZw |= 1; 
+		}
+		if (log->dw.ZZw && log->nast_.ZZw_ON) //jeseli jest właczony i jest spełnione kryterium załączenia na zwarcie
+		{
+			wybiornik_fbk_komp(log, log->nast_.ZZw_st);
+
+			log->dw.bl_WSPZ = 1;
+
+			if (log->dw.Rbk | log->dw.Sbk | log->dw.Tbk)
+			{
+				if (!temp_Bl)
+				{
+					log->dw.W1 = log->dw.W2 = log->dw.W3 = log->dw.W = 1;			
+					log->dw.ZZwP = 1;
+				}
+			} else log->dw.ZZwP = 0;
+
+		} else {
+			log->dw.Rbk = log->dw.Sbk = log->dw.Tbk = 0;
+			log->dw.ZZwP = 0;
+		}
+		
+		//-------------------------------------------------------------------------------------------------------
+
+		for(i=0;i<6;i++) 
+		{
+			log->dw.Ws[i] = log->dw.Z[i] && log->nast_.Stf_W[i] && !log->dw.blok_lacza[i] && !log->dw.blok_LRC[i];
+		}
+					
+		wylacz_P_komp(log, we_zgoda_1f);
+			
+		//-------------------------------------------------------------------------------------------------------
+
+
+		if (log->dw.ZZw && log->nast_.ZZw_ON)
+			log->nast_.ZdistA->SOTF_zwrotnie = log->nast_.ZZw_st;
+		else
+			log->nast_.ZdistA->SOTF_zwrotnie = 0xFF;
+
+
+
+		u8 pob_L1 = 0;
+		u8 pob_L2 = 0;
+		u8 pob_L3 = 0;
+		u8 pob_E = 0;
+		
+		u8 bylo_pob = 0;
+
+		u8 nr_strefy[6]={1,0,2,3,4,5}; // renumeracja -> 1,1w,2,3,4,5
+
+		for (i = 0; i < 6; i++)
+		{
+			if ((log->nast_.Stf_ON[nr_strefy[i]] != 0) && (b_blok[nr_strefy[i]] == 0))
+			{			
+				if (log->pobudzenia[nr_strefy[i]][0] || log->pobudzenia[nr_strefy[i]][3] || log->pobudzenia[nr_strefy[i]][5])
+				{
+					if(!bylo_pob)// || log->dw.Z[nr_strefy[i]] /*|| poprawka_pawla[nr_strefy[i]]*/)
+						pob_L1 = 1;
+				}		
+				if (log->pobudzenia[nr_strefy[i]][1] || log->pobudzenia[nr_strefy[i]][3] || log->pobudzenia[nr_strefy[i]][4])
+				{
+					if(!bylo_pob) //|| log->dw.Z[nr_strefy[i]]/* || poprawka_pawla[nr_strefy[i]]*/)
+						pob_L2 = 1;
+				}			
+				if (log->pobudzenia[nr_strefy[i]][2] || log->pobudzenia[nr_strefy[i]][4] || log->pobudzenia[nr_strefy[i]][5])
+				{
+					if(!bylo_pob) // || log->dw.Z[nr_strefy[i]]/* || poprawka_pawla[nr_strefy[i]]*/)
+						pob_L3 = 1;
+				}			
+				if (log->pobudzenia[nr_strefy[i]][0] || log->pobudzenia[nr_strefy[i]][1] || log->pobudzenia[nr_strefy[i]][2])
+				{
+//					if(!bylo_pob || log->dw.Z[nr_strefy[i]]/* || poprawka_pawla[nr_strefy[i]]*/)
+						pob_E = 1;
+				}
+			}
+
+			if(POPRAWKA_1)
+			{
+
+				if((pob_L1||pob_L2||pob_L3)/*&&poprawka_pawla[nr_strefy[i]]*/)
+				{
+					bylo_pob=1;
+					break;
+				}
+			}
+		}
+
+		//wyprowadzenie wyjść
+		check_and_set_struct(log->dw.P,&log->P);
+		check_and_set_struct(log->dw.Pzf[0],&log->P1W);
+		check_and_set_struct(log->dw.Pzf[1],&log->P1);
+		check_and_set_struct(log->dw.Pzf[2],&log->P2);
+		check_and_set_struct(log->dw.Pzf[3],&log->P3);
+		check_and_set_struct(log->dw.Pzf[4],&log->P4);
+		check_and_set_struct(log->dw.Pzf[5],&log->P5);
+
+		check_and_set_struct(log->dw.Z[0],&log->Z1W);
+		check_and_set_struct(log->dw.Z[1],&log->Z1);
+		check_and_set_struct(log->dw.Z[2],&log->Z2);
+		check_and_set_struct(log->dw.Z[3],&log->Z3);
+		check_and_set_struct(log->dw.Z[4],&log->Z4);
+		check_and_set_struct(log->dw.Z[5],&log->Z5);
+
+		check_and_set_struct(log->dw.R || log->dw.Rbk,&log->R);
+		check_and_set_struct(log->dw.S || log->dw.Sbk,&log->S);
+		check_and_set_struct(log->dw.T || log->dw.Tbk,&log->T);
+		check_and_set_struct(log->dw.E,&log->E);
+
+		check_and_set_struct(log->dw.W,&log->W);
+		check_and_set_struct(log->dw.W1,&log->W1);
+		check_and_set_struct(log->dw.W2,&log->W2);
+		check_and_set_struct(log->dw.W3,&log->W3);
+	
+		if(log->dw.ZZwP)
+		{
+			set_struct(&log->ZZZw);
+			set_struct(&log->PZZw);
+		}
+
+		check_and_set_struct(log->dw.wy_bl_LRC, &log->bl_LRC);
+		check_and_set_struct(log->dw.wy_log_odbl,&log->log_odbl);
+		check_and_set_struct(log->dw.wy_lacze_nad,&log->lacze_nad);
+		check_and_set_struct(log->dw.ZZw,&log->zzw_akt);
+		check_and_set_struct(log->dw.wy_blk_lacz,&log->blk_lacz);
+		
+		check_and_set_struct(log->dw.wy_zadz_echa,&log->zadz_echa);
+		check_and_set_struct(log->dw.wy_zezw_lacz,&log->zezw_lacz);
+		check_and_set_struct(log->dw.wy_skr_czas_lacz,&log->skr_czas_lacz);
+		check_and_set_struct(log->dw.wy_wyl_lacz,&log->wyl_lacz);
+		check_and_set_struct(log->dw.wy_blok_lacz,&log->blok_lacz);
+		check_and_set_struct(log->dw.wy_wydl_czas_lacz,&log->wydl_czas_lacz);
+		check_and_set_struct(log->dw.ZZwP,&log->z_zwarcie);
+
+		if(POPRAWKA_3)
+		{
+			sprawdz_P(&log->pob1_flt,pob_L1, !pob_L1, &log->pob1_flt_cnt, 6, 4);
+			sprawdz_P(&log->pob2_flt,pob_L2, !pob_L2, &log->pob2_flt_cnt, 6, 4);
+			sprawdz_P(&log->pob3_flt,pob_L3, !pob_L3, &log->pob3_flt_cnt, 6, 4);
+			sprawdz_P(&log->pob4_flt,pob_E, !pob_E, &log->pob4_flt_cnt, 6, 4);
+			check_and_set_struct(log->pob1_flt, &log->P_L1);
+			check_and_set_struct(log->pob2_flt, &log->P_L2);
+			check_and_set_struct(log->pob3_flt, &log->P_L3);
+			check_and_set_struct(log->pob4_flt, &log->P_E);
+		}
+		else
+		{
+			check_and_set_struct(pob_L1, &log->P_L1);
+			check_and_set_struct(pob_L2, &log->P_L2);
+			check_and_set_struct(pob_L3, &log->P_L3);
+			check_and_set_struct(pob_E, &log->P_E);
+		}
+		
+		check_and_set_struct(log->dw.Ws[0],&log->WS1W);
+		check_and_set_struct(log->dw.Ws[1],&log->WS1);
+		check_and_set_struct(log->dw.Ws[2],&log->WS2);
+		check_and_set_struct(log->dw.Ws[3],&log->WS3);
+		check_and_set_struct(log->dw.Ws[4],&log->WS4);
+		check_and_set_struct(log->dw.Ws[5],&log->WS5);
+		
+		check_and_set_struct(log->dw.wyl_1f,&log->W_1f);
+	} 
+	else 
+	{
+		clear_struct(&log->P);
+		clear_struct(&log->P1W);
+		clear_struct(&log->P1);
+		clear_struct(&log->P2);
+		clear_struct(&log->P3);
+		clear_struct(&log->P4);
+		clear_struct(&log->P5);
+		clear_struct(&log->Z1W);
+		clear_struct(&log->Z1);
+		clear_struct(&log->Z2);
+		clear_struct(&log->Z3);
+		clear_struct(&log->Z4);
+		clear_struct(&log->Z5);
+		clear_struct(&log->R);
+		clear_struct(&log->S);
+		clear_struct(&log->T);
+		clear_struct(&log->E);
+		clear_struct(&log->W);
+		clear_struct(&log->W1);
+		clear_struct(&log->W2);
+		clear_struct(&log->W3);
+
+		clear_struct(&log->PZZw);
+		clear_struct(&log->ZZZw);
+		clear_struct(&log->bl_LRC);
+		clear_struct(&log->log_odbl);
+		clear_struct(&log->lacze_nad);
+		clear_struct(&log->blk_lacz);
+		
+		clear_struct(&log->zadz_echa);
+		clear_struct(&log->zezw_lacz);	
+		clear_struct(&log->skr_czas_lacz);	
+		clear_struct(&log->wyl_lacz);
+		clear_struct(&log->blok_lacz);
+		clear_struct(&log->wydl_czas_lacz);	
+		clear_struct(&log->z_zwarcie);
+		
+		clear_struct(&log->P_L1);
+		clear_struct(&log->P_L2);
+		clear_struct(&log->P_L3);
+		clear_struct(&log->P_E);
+		
+		clear_struct(&log->WS1);
+		clear_struct(&log->WS1W);
+		clear_struct(&log->WS2);
+		clear_struct(&log->WS3);
+		clear_struct(&log->WS4);
+		clear_struct(&log->WS5);
+		
+		clear_struct(&log->W_1f);
+	}
+
+}
+
+void ZDistL_100hz_komp(void *arguments, void *logic)
+{
+struct ZDistL_logic_komp *log = (struct ZDistL_logic_komp *)logic;
+
+u16 i;
+u8 tempbool = 0;
+
+u8 we_W_ON =  check_struct(&log->W_ON)?1:0;
+u8 we_Z =  check_struct(&log->Z)?1:0;
+	
+	if (*log->nast_.ZdistA->on)
+	{
+		//lacze nad
+		if (log->dw.lacze_nad == 1)
+		{
+			if (--log->dw.t_lacze_nad == 0)
+			{
+				log->dw.wy_lacze_nad = 0;
+				log->dw.lacze_nad = 0;
+			}
+		}
+		//logika pradu wstecznego
+		if (log->dw.blokada_pradu_wstecznego == 1)
+		{
+			if (--log->dw.t_pod_blok_wst == 0)
+			{
+				log->dw.wy_bl_LRC = 0;
+				log->dw.blokada_pradu_wstecznego = 0;
+			}
+		}
+		
+		//logika odblokowania
+		if (log->dw.logika_dblokowania == 1)
+		{
+			if (--log->dw.t_log_odblokowania == 0)
+			{
+				log->dw.logika_dblokowania = 0;
+				log->dw.wy_log_odbl = 0;
+			}			
+		}
+	
+		//echo
+		if (log->dw.wylacz_od_echa == 1)
+		{
+			if (--log->dw.t_wyl_od_echa == 0)
+				log->dw.wylacz_od_echa = 0;				
+		}
+		
+		//urwanie imp nadawania
+		if (log->dw.lacze_nad == 1)
+		{
+			if (++log->dw.trwanie_nad > log->nast_.max_t_nadawania)
+			{
+			log->dw.wy_lacze_nad = 0;
+			log->dw.lacze_nad = 0;
+			log->dw.skrocil_strefa = 1;
+			log->dw.skrocil_echo = 1;	
+			}
+		}
+		else
+		{
+			log->dw.trwanie_nad = 0;	
+		}
+				
+		//wczytanie danych o stanie wyłącznika
+		log->dw.W_ON = we_W_ON;
+		
+    if (we_W_ON)
+         log->dw.W_OFF = 2;
+    else
+      if (log->dw.W_OFF > 0)
+        log->dw.W_OFF--;
+    
+		for (i=0;i<6;i++)
+		{
+
+			//realizacja przekaznikow czasowych
+			if (log->nast_.Stf_ON[i]) //jesli strefa wlaczona
+			{
+
+				if (log->dw.Pf[i][0]) 
+				{
+					if(!log->nast_.Zbz[i][0]) // jesli nie bezzwloczny
+					{
+						if (!log->dw.liczts[i][0])
+						{
+							log->dw.Zf[i][0] = 1;
+							log->dw.liczts[i][0]++;
+						}
+						log->dw.liczts[i][0]--;
+					}
+         			 log->dw.liczt_eldz[i][0] = 2;
+				} 
+				else//wylaczenie zadzialania (odpad)
+				{
+           			if (log->dw.liczt_eldz[i][0] > 0)
+              			log->dw.liczt_eldz[i][0]--;
+            		else
+            		{
+             			 log->dw.liczts[i][0] = log->nast_.t_stf[i][0];
+              			log->dw.Zf[i][0] = 0;
+           			 }       
+        		}
+				if (log->dw.Pf[i][1]) 
+				{
+					if(!log->nast_.Zbz[i][1]) // jesli nie bezzwloczny
+					{
+						if (!log->dw.liczts[i][1])
+						{
+							log->dw.Zf[i][1] = 1;
+							log->dw.liczts[i][1]++;
+						}
+						log->dw.liczts[i][1]--;
+          			}
+          			log->dw.liczt_eldz[i][1] = 2;
+				} 
+				else//wylaczenie zadzialania (odpad)
+				{
+           	 	if (log->dw.liczt_eldz[i][1] > 0)
+            	  log->dw.liczt_eldz[i][1]--;
+           		 else
+				{
+              		log->dw.liczts[i][1] = log->nast_.t_stf[i][1];
+              		log->dw.Zf[i][1] = 0;
+            	}              
+			}				
+		}
+			//-----------------------------------------------------------
+		
+		
+		if ((log->dw.Pf[i][0]) || (log->dw.Pf[i][1]))
+		{
+			log->dw.liczts_rozwij[i]++;
+			log->dw.liczt_eldz_rozwij[i] = 2;	
+			if ((log->dw.Pf[i][0]) && (log->dw.liczts_rozwij[i] > (log->nast_.t_stf[i][0] + log->dw.dodaj_rozw[i])))
+			{
+				log->dw.Zf_rozwij[i] = 1;					
+			}
+			
+			if ((log->dw.Pf[i][1]) && (log->dw.liczts_rozwij[i] > (log->nast_.t_stf[i][1]+ log->dw.dodaj_rozw[i])))
+			{
+				log->dw.Zf_rozwij[i] = 1;
+			}
+		}
+		else
+		{
+			if (log->dw.liczt_eldz_rozwij[i] > 0)
+            	log->dw.liczt_eldz_rozwij[i]--;
+           	else
+			{
+				log->dw.dodaj_rozw[i] = 0;
+				log->dw.Zf_rozwij[i] = 0;
+				log->dw.liczts_rozwij[i] = 0;
+			}
+		}
+		
+		if (log->nast_.rozwij)
+		{
+			log->dw.Zf[i][1] |= log->dw.Zf_rozwij[i];
+			log->dw.Zf[i][0] |= log->dw.Zf_rozwij[i];
+		}	
+		
+		
+		}
+
+		//odpad wylaczen
+	
+		for(i=0;i<6;i++)
+		{
+			tempbool |= log->dw.Ws[i];
+		}
+		tempbool |= log->dw.wylacz_od_lacza_suma;
+		
+		if (!tempbool) 
+		{
+			log->dw.W = log->dw.W1 = log->dw.W2 = log->dw.W3 = log->dw.R = log->dw.S = log->dw.T = log->dw.E = 0;
+			log->dw.wyl_1f = 0;	
+		}
+		//automatyka załaczenia na zwarcie - identyfikacja stanu załączenia na zwarcie
+
+		if (log->nast_.ZZw_ON)
+		{
+			//właczenie od otwarcia wyłącznika
+			if (log->nast_.kryt_IU_ZZW |= 0)
+			{
+			tempbool = 	(log->nast_.ZdistA->Zdist_dw->I1< log->nast_.ZZw_Ir) & 
+				(log->nast_.ZdistA->Zdist_dw->I2 < log->nast_.ZZw_Ir) & 
+				(log->nast_.ZdistA->Zdist_dw->I3 < log->nast_.ZZw_Ir) & 
+				(log->nast_.ZdistA->Zdist_dw->U1 < log->nast_.ZZw_Ur) & 
+				(log->nast_.ZdistA->Zdist_dw->U2 < log->nast_.ZZw_Ur) & 
+				(log->nast_.ZdistA->Zdist_dw->U3 < log->nast_.ZZw_Ur);
+
+			sprawdz_P_100(&log->dw.ZZw_PIU,tempbool,!tempbool,&log->dw.licznik_PIU,log->nast_.ZZw_to,2);
+			}
+			else
+			{
+				log->dw.ZZw_PIU = 0;
+			}
+			
+			log->dw.ZZw_start = log->dw.ZZw_PIU | //włączenie ZZw jeśli brak napięcia i prądu
+							we_Z | //włączenie ZZw jeśli aktywny sygnał zamknięcia wyłącznika
+								(log->dw.W_OFF == 0); //włączenie ZZw jeśli otwarte styki
+	
+			log->dw.ZZw |= log->dw.ZZw_start; 
+			if(log->dw.ZZw_start)
+			{
+				log->dw.licznik_ZZwa = 0;
+			} 
+			else 
+			{
+				log->dw.licznik_ZZwa++;
+				if(log->dw.licznik_ZZwa > log->nast_.ZZw_ta)
+				{
+					if (!log->dw.ZZwP) log->dw.ZZw = 0;
+					log->dw.licznik_ZZwa--;
+				}
+			}
+		}
+		else
+		{
+			log->dw.ZZw = 0;
+		}
+	}
+
+}
diff --git a/ZDistL_komp.h b/ZDistL_komp.h
new file mode 100644
index 0000000..1680e9c
--- /dev/null
+++ b/ZDistL_komp.h
@@ -0,0 +1,413 @@
+/*
+ * ZDistL.h
+ *
+ *
+ *  Created on: 29-11-2016
+ *      Author: KJ
+ */
+
+#ifndef ZDISTL_H_KOMP_
+#define ZDISTL_H_KOMP_
+//#include "pawel_usun_to.h"
+
+#include "../tdefs.h"
+#include "helper.h"
+#include "ZDistL.h"
+
+
+struct Wyjscie1_zdistl_komp
+{
+	u8 dbl_Com[7]; ///deblokowanie działania stref w zależności od stanu łącza
+	u8 PSPZ;//pobudzenie SPZ
+};
+
+struct dane_wewnetrzne_ZDistL_komp
+{
+       u8 blok_lacza[6];
+        u8 wydl_czas;       
+        u8 wylacz_od_lacza;
+        u8 wylacz_od_echa;
+        u8 wylacz_od_lacza_suma;
+        //lacze nad       
+        u16 t_lacze_nad;
+        u8 lacze_nad;
+        
+        u16 trwanie_nad;
+        u8 skrocil_strefa;
+        u8 skrocil_echo;
+        
+        
+        //logika pradu wstecznego       
+        u8 blokada_pradu_wstecznego;
+        u16 t_pod_blok_wst;
+        u8 kopia_lacze_ok;
+        u8 lacze_odb_old;
+        
+        
+        //logika odblokowania
+        u8 logika_dblokowania;
+        u16 t_log_odblokowania;
+             
+        u8 blok_LRC[6];
+        
+
+        u16 t_wyl_od_echa;
+               
+        float RL1Em; ///< Rezystancja pętli zwarciowej fazy L1 z ziemia (rejestracja)
+        float XL1Em; ///< Rezaktancja pętli zwarciowej fazy L1 z ziemia (rejestracja)
+        float RL2Em; ///< Rezystancja pętli zwarciowej fazy L2 z ziemia (rejestracja)
+        float XL2Em; ///< Rezaktancja pętli zwarciowej fazy L2 z ziemia (rejestracja)
+        float RL3Em; ///< Rezystancja pętli zwarciowej fazy L3 z ziemia (rejestracja)
+        float XL3Em; ///< Rezaktancja pętli zwarciowej fazy L3 z ziemia (rejestracja)
+        float RL1L2m; ///< Rezystancja pętli zwarciowej fazy L1 z L2 (rejestracja)
+        float XL1L2m; ///< Rezaktancja pętli zwarciowej fazy L1 z L2 (rejestracja)
+        float RL2L3m; ///< Rezystancja pętli zwarciowej fazy L2 z L3 (rejestracja)
+        float XL2L3m; ///< Rezaktancja pętli zwarciowej fazy L2 z L3 (rejestracja)
+        float RL3L1m; ///< Rezystancja pętli zwarciowej fazy L3 z L1 (rejestracja)
+        float XL3L1m; ///< Rezaktancja pętli zwarciowej fazy L3 z L1 (rejestracja)
+		short liczts[6][2]; ///<licznik czasu czas opoznienia dzialania strefy
+    
+    	short liczt_eldz[6][2]; ///<licznik czasu czas opoznienia dzialania strefy
+
+		short licznik_ZZwa;///< licznik do automatyki załączenia na zwarcie
+		short licznik_PIU;///< licznik pobudzeń sprawdzania obecności napiecia i prądu
+		
+		short licznik_Uecho;
+		
+		//Wyjscia_rejestratora Rej; ///< dane ostatniego zaklocenia
+		//Time czas_; // moment wystapienia zaklocenia (rejestr tymczasowy - przed zapisem)
+		u32 dl_; // dlugosc czasu trwania zaklocenia (rejestr tymczasowy - przed zapisem)
+		u8 wsk_rej; // nowy zapis rejestracji parametrow zaklocenia (spelnienie kryterium identyfikacji)
+		u8 Pf[6][2]; // pobudzenia stref P[nr strefy][fazowe,miedzyfazowe]
+		u8 Pzf[6]; //pobudzenie stref
+		u8 P;// pobudzenie zbiorcze
+		u8 Zf[6][2]; // zadzialanie strefy
+		u8 Z[6]; // zadzialanie strefy
+		u8 Ws[6]; // wyłaczenie od strefy 
+		u8 Zz; // Zadzialanie sygnal zbiorczy
+		u8 W; // wylaczenie sygnal zbiorczy
+		u8 W1; // wylaczenie faza L1
+		u8 W2; // wylaczenie faza L2
+		u8 W3; // wylaczenie faza L3
+		u8 R;//zwarcie z udziałem fazy L1
+		u8 S;//zwarcie z udziałem fazy L2
+		u8 T;//zwarcie z udziałem fazy L3
+		u8 Rbk;//zwarcie z udziałem fazy L1(bezkierunkowo)
+		u8 Sbk;//zwarcie z udziałem fazy L2(bezkierunkowo)
+		u8 Tbk;//zwarcie z udziałem fazy L3(bezkierunkowo)
+		u8 E;//zwarcie z udziałem ziemi
+		u8 jedfaz;//zwarcie jednofazowe
+		u8 W_ON;//wyłącznik zamkniety
+		u8 W1_ON;//wyłącznik zamkniety faza L1
+		u8 W2_ON;//wyłącznik zamkniety faza L2
+		u8 W3_ON;//wyłącznik zamkniety faza L3
+		u8 W_OFF;//wyłącznik otwarty
+		u8 W1_OFF;//wyłącznik otwarty faza L1
+		u8 W2_OFF;//wyłącznik otwarty faza L2
+		u8 W3_OFF;//wyłącznik otwarty faza L3
+		u8 ZZw; //aktywna automatyka załączenia na zwarcie
+		u8 ZZw_start; //spełnienie warunków uruchomienia automatyki załączenia na zwarcie
+		u8 ZZw_PIU; //pobudzenie kryterium napięcie/prąd zamknięcia wyłącznika
+		u8 pob_echo;
+		u8 bl_WSPZ;//zezwolenie na wyłącz od SPZ
+		u8 R1;
+		u8 S1;
+		u8 T1;
+		u8 ZZwP;//wyłączenie od automatyki załączenia na zwarcie
+		u8 wy_blk_lacz;
+		
+		u8 wy_bl_LRC;
+		u8 wy_log_odbl;
+        u8 wy_lacze_nad;
+        
+        u8 wy_zadz_echa;
+		u8 wy_zezw_lacz; 
+		u8 wy_skr_czas_lacz; 
+		u8 wy_wyl_lacz; 
+		u8 wy_blok_lacz; 
+		u8 wy_wydl_czas_lacz; 
+		
+		u8 wyl_1f;
+		
+		u8 Zf_rozwij[6];
+		short liczts_rozwij[6];
+		short liczt_eldz_rozwij[6];
+		short dodaj_rozw[6];
+
+};
+
+struct Nastawy_przeliczone_ZDistL_komp
+{
+	struct Wyjscie1_zdistl_komp wy;
+
+	struct Wyjscia_ZDistA_komp *ZdistA;
+		
+	u16 ZZw_st; ///< strefa współpracy z automatyką załączenia na zwarcie
+	u16 adr_PZZw;///< adres zmiennej pobudzenia strefy współpracujacej z automatyką ZZw
+	u16 adr_ZZZw;///< adres zmiennej zadziałania strefy współpracujacej z automatyką ZZw
+
+	u8 echo_on;
+	u8 wyl_od_echa;
+	u8 log_odbl_on;
+	u8 LCR_on;
+	u8 lacze_on;	
+	u8 LRC_s[6];
+	u8 zgoda_1faz_s[6];
+
+	u8 Bl_PS[6];
+	u8 ZZw_ON; ///< włączenie automatyki załączenia na zwarcie
+	u8 bl_; ///< wartosc nastawy aktywnosci blokady dzialania 1- blokada aktywna
+	
+	u8 rozwij;
+	u8 kryt_IU_ZZW;
+	
+	enum _tryb_zezwalajacy tryb_zezw;
+    enum _tryb_blokujacy tryb_blok;
+    enum _tryb_lacza tryb_lacza;
+		
+	u8 ktora_strefa;
+	u8 ktora_strefa_nad;
+    u8 strefa_pradu_wstecznego;
+				
+	short t_stf[6][2]; ///< czas dzialania strefy
+	float ZZw_ta;///< Czas działania funkcji po zamknięciu wyłącznika
+	float ZZw_Ir;///< Prąd identyfikacji otwarcia wyłącznika
+	float ZZw_Ur;///< Napięcie identyfikacji otwarcia wyłacznika
+	short ZZw_to;///< Czas identyfikacji otwarcia wyłącznika
+
+	short t_LRC;///< Czas podtrzymania w logice odwroconego pradu
+	short t_pod_odbl;///< Czas podtrzymania odblokowania w logice odblokowania
+	short t_lacze_nad;///< Czas przerwy beznapięciowej dla wyłączenia jednofazowego
+	short ts_plus;
+
+	short max_t_nadawania;
+	short czas_wyl_echa;
+
+	float Uecho_pob;
+	float Uecho_odp;
+		
+	u8 Zbz[6][2]; ///< zadziałanie bezzwloczne strefy
+	u8 Stf_ON[6]; ///< wlaczenie/odstawienie strefy
+	u8 Stf_W[6]; ///< działanie na wylaczenie/sygnalizacje strefy
+
+};
+
+struct ZDistL_logic_komp
+{
+ 
+    struct binary_io stan_bl;
+    struct Wyjscia_ZDistA_komp *WE_Zdist;
+	struct binary_io Bl_PS;
+	struct binary_io lacze_OK;
+	struct binary_io lacze_odb;
+	struct binary_io W_ON;
+	struct binary_io zgoda_1f;
+	struct binary_io Z;
+	struct binary_io test;
+	struct binary_io blok_1;
+	struct binary_io blok_1W;
+	struct binary_io blok_2;
+	struct binary_io blok_3;
+	struct binary_io blok_4;
+	struct binary_io blok_5;
+		
+    struct binary_io P;
+	struct binary_io P1W;
+	struct binary_io P1;
+	struct binary_io P2;
+	struct binary_io P3;
+	struct binary_io P4;
+	struct binary_io P5;
+	struct binary_io R;
+	struct binary_io S;
+	struct binary_io T;
+	struct binary_io E;
+	struct binary_io Z1W;
+	struct binary_io Z1;
+	struct binary_io Z2;
+	struct binary_io Z3;
+	struct binary_io Z4;
+	struct binary_io Z5;	
+	struct binary_io W;
+	struct binary_io W1;
+	struct binary_io W2;
+	struct binary_io W3;
+	struct binary_io bl_LRC;
+	struct binary_io log_odbl;
+	struct binary_io lacze_nad;
+	struct binary_io zzw_akt;
+	struct binary_io blk_lacz;
+	
+	struct binary_io deakt;
+
+	//nowe
+	struct binary_io zadz_echa;
+	struct binary_io zezw_lacz;
+	struct binary_io skr_czas_lacz;
+	struct binary_io wyl_lacz;
+	struct binary_io blok_lacz;
+	struct binary_io wydl_czas_lacz;
+	struct binary_io z_zwarcie;
+	
+	struct binary_io PZZw;
+	struct binary_io ZZZw;
+	
+	struct binary_io P_L1; ///< Pobudzenie sfazy L1
+	struct binary_io P_L2; ///< Pobudzenie sfazy L1
+	struct binary_io P_L3; ///< Pobudzenie sfazy L1
+	struct binary_io P_E; ///< Pobudzenie sfazy L1
+	
+	struct binary_io WS1W;
+	struct binary_io WS1;
+	struct binary_io WS2;
+	struct binary_io WS3;
+	struct binary_io WS4;
+	struct binary_io WS5;
+	
+	struct binary_io W_1f;	
+	
+	struct Nastawy_przeliczone_ZDistL_komp nast_;
+	struct dane_wewnetrzne_ZDistL_komp dw;
+	u8 pobudzenia[6][6];
+	u8 P_L1_lub_L2[6];
+	u8 P_L2_lub_L3[6];
+	u8 P_L3_lub_L1[6];
+
+	u8 pob1_flt;
+	short pob1_flt_cnt;
+	u8 pob2_flt;
+	short pob2_flt_cnt;
+	u8 pob3_flt;
+	short pob3_flt_cnt;
+	u8 pob4_flt;
+	short pob4_flt_cnt;
+
+};
+
+struct ZDistL_io_komp
+{
+	u32	stan_bl_in;
+	u32	 we_zdist_ptr_in;
+	u32	Bl_PS_in;
+	u32	lacze_OK_in;
+	u32	lacze_odb_in;
+	u32	W_ON_in;
+	u32	zgoda_1f_in;
+	u32	Z_in;
+	u32	test_in;
+	u32 blok_1_in;
+	u32 blok_1W_in;
+	u32 blok_2_in;
+	u32 blok_3_in;
+	u32 blok_4_in;
+	u32 blok_5_in;
+	u32 deakt_in;
+
+	u32	P_out;
+	u32	P1W_out;
+	u32	P1_out;
+	u32	P2_out;
+	u32	P3_out;
+	u32	P4_out;
+	u32	P5_out;
+	u32	R_out;
+	u32	S_out;
+	u32	T_out;
+	u32	E_out;
+	u32	Z1W_out;
+	u32	Z1_out;
+	u32	Z2_out;
+	u32	Z3_out;
+	u32	Z4_out;
+	u32	Z5_out;
+	u32	W_out;
+	u32	W1_out;
+	u32	W2_out;
+	u32	W3_out;
+	u32	bl_LRC_out;
+	u32	log_odbl_out;
+	u32	lacze_nad_out;
+	u32	zzw_akt_out;
+	u32 blk_lacz_out;
+	
+	//nowe
+	u32 zadz_echa_out;
+	u32 zezw_lacz_out;
+	u32 skr_czas_lacz_out;
+	u32 wyl_lacz_out;
+	u32 blok_lacz_out;
+	u32 wydl_czas_lacz_out;
+	u32 z_zwarcie_out;	
+	
+	u32 P_L1_out;
+	u32 P_L2_out;
+	u32 P_L3_out;
+	u32 P_E_out;
+	
+	u32	WS1W_out;
+	u32	WS1_out;
+	u32	WS2_out;
+	u32	WS3_out;
+	u32	WS4_out;
+	u32	WS5_out;
+	
+	u32 W_1f_out;
+	
+}__attribute__((__packed__));
+
+struct ZDistL_params_komp
+{
+	long bity; ///< nastawy bitowe;
+	long Stf1; ///< Sposób działania strefy 1
+	long Stf2; ///< Sposób działania strefy 2
+	long Stf3; ///< Sposób działania strefy 3
+	long Stf4; ///< Sposób działania strefy 4
+	long Stf5; ///< Sposób działania strefy 5
+	long tryb_lacza; ///< tryb lacza
+	long ZZw_st; ///< strefa współpracy z automatyką załączenia na zwarcie
+	long tryb_zezw; ///<tryb zezwalajacy
+	long tryb_blokujacy; ///<tryb blokujacy
+	long strefa_nad;///<wybor strefy do nadawania
+	long strefa_dzial; //<działanie na strefę
+	long lrc_strefa; //<strefa logiku prądu wstecznego
+
+	double ts1LE;///< Czas wyłączenia strefy 1 zwarcia jednofazowe z ziemią
+	double ts1LL;///< Czas wyłączenia strefy 1 zwarcia miedzyfazowe
+	double ts2LE;///< Czas wyłączenia strefy 2 zwarcia jednofazowe z ziemią
+	double ts2LL;///< Czas wyłączenia strefy 2 zwarcia miedzyfazowe
+	double ts3LE;///< Czas wyłączenia strefy 3 zwarcia jednofazowe z ziemią
+	double ts3LL;///< Czas wyłączenia strefy 3 zwarcia miedzyfazowe
+	double ts4LE;///< Czas wyłączenia strefy 4 zwarcia jednofazowe z ziemią
+	double ts4LL;///< Czas wyłączenia strefy 4 zwarcia miedzyfazowe
+	double ts5LE;///< Czas wyłączenia strefy 5 zwarcia jednofazowe z ziemią
+	double ts5LL;///< Czas wyłączenia strefy 5 zwarcia miedzyfazowe
+	double t_LRC;///< Czas podtrzymania w logice odwroconego pradu
+	double t_pod_odbl;///< Czas podtrzymania odblokowania w logice odblokowania
+	double t_lacze_nad;///< Czas przerwy beznapięciowej dla wyłączenia jednofazowego
+	double ZZw_ta;///< Czas działania funkcji po zamknięciu wyłącznika
+	double ZZw_Ir;///< Prąd identyfikacji otwarcia wyłącznika
+	double ZZw_Ur;///< Napięcie identyfikacji otwarcia wyłacznika
+	double ZZw_to;///< Czas identyfikacji otwarcia wyłącznika
+	double U_echa;
+	double ts_plus;
+	double max_t_nadawania;
+	double czas_wyl_echa;
+	
+	long Stf0; ///< Sposób działania strefy 1
+	double ts0LE;///< Czas wyłączenia strefy 1 zwarcia jednofazowe z ziemią
+	double ts0LL;///< Czas wyłączenia strefy 1 zwarcia miedzyfazowe
+	
+}__attribute__((__packed__));
+
+struct ZDistL_args_komp
+{
+	struct ZDistL_io_komp io;
+	struct ZDistL_params_komp params;
+//	u16 crc;
+}__attribute__((__packed__));
+
+extern void ZDistL_komp(void *args, void *logic);
+extern void ZDistL_100hz_komp(void *args, void *logic);
+extern int ZDistL_initlog_komp(void *arguments, void *logic);
+
+#endif /* ZDISTL_H_KOMP_ */
diff --git a/rezultat.md b/rezultat.md
new file mode 100644
index 0000000..4989417
--- /dev/null
+++ b/rezultat.md
@@ -0,0 +1,17 @@
+# Wynik analizy zabezpieczenia odleglosciowego
+
+## Parametry zabezpieczenia
+- Impedancja linii: R=0.00 Ohm, X=-0.01 Ohm
+- Kat linii: -76.9 st.
+- Strefa 1: R=0.00 Ohm, X=-0.01 Ohm (natychmiast)
+- Strefa 2: R=0.00 Ohm, X=-0.02 Ohm (300ms)
+- Strefa 3: R=0.01 Ohm, X=-0.03 Ohm (600ms)
+
+## Wykrycie zwarcia
+
+**Brak wykrycia zwarcia**
+
+Zabezpieczenie nie zadzialalo w okresie rejestracji.
+
+---
+*Wygenerowano automatycznie przez tester zabezpieczenia odleglosciowego*
\ No newline at end of file
diff --git a/src/cfg_var.c b/src/cfg_var.c
new file mode 100644
index 0000000..b6e75fe
--- /dev/null
+++ b/src/cfg_var.c
@@ -0,0 +1,35 @@
+/*
+ * cfg_var.c
+ *
+ *  Created on: 10-09-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#include "cfg_var.h"
+#include "misc.h"
+
+
+const struct config_lookup_table cfg_lut[]=
+{
+    /* var name, var type, var addr, var size, bit mask, flags */
+	{"klapacz_enabled", ARG_TYPE_BOOL, &dev_cfg.bits, sizeof(dev_cfg.bits), CFG_BIT_KLAPACZ_ENABLED },
+	{"device_bits", ARG_TYPE_LONG, &dev_cfg.bits, sizeof(dev_cfg.bits)},
+	{"mwd0_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[0],sizeof(dev_cfg.mwd_ac_mask[0]), 0, NEED_RELOAD_IC},
+	{"mwd1_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[1],sizeof(dev_cfg.mwd_ac_mask[1]), 0, NEED_RELOAD_IC},
+	{"mwd2_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[2],sizeof(dev_cfg.mwd_ac_mask[2]), 0, NEED_RELOAD_IC},
+	{"mwd3_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[3],sizeof(dev_cfg.mwd_ac_mask[3]), 0, NEED_RELOAD_IC},
+	{"mwd4_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[4],sizeof(dev_cfg.mwd_ac_mask[4]), 0, NEED_RELOAD_IC},
+	{"mwd5_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[5],sizeof(dev_cfg.mwd_ac_mask[5]), 0, NEED_RELOAD_IC},
+	{"mwd6_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[6],sizeof(dev_cfg.mwd_ac_mask[6]), 0, NEED_RELOAD_IC},
+	{"mwd7_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[7],sizeof(dev_cfg.mwd_ac_mask[7]), 0, NEED_RELOAD_IC},
+	{"mwd8_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[8],sizeof(dev_cfg.mwd_ac_mask[8]), 0, NEED_RELOAD_IC},
+	{"mwd9_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[9],sizeof(dev_cfg.mwd_ac_mask[9]), 0, NEED_RELOAD_IC},
+	{"mwd10_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[10],sizeof(dev_cfg.mwd_ac_mask[10]), 0, NEED_RELOAD_IC},
+	{"mwd11_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[11],sizeof(dev_cfg.mwd_ac_mask[11]), 0, NEED_RELOAD_IC},
+	{"mwd12_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[12],sizeof(dev_cfg.mwd_ac_mask[12]), 0, NEED_RELOAD_IC},
+	{"mwd13_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[13],sizeof(dev_cfg.mwd_ac_mask[13]), 0, NEED_RELOAD_IC},
+	{"mwd14_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[14],sizeof(dev_cfg.mwd_ac_mask[14]), 0, NEED_RELOAD_IC},
+	{"mwd15_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[15],sizeof(dev_cfg.mwd_ac_mask[15]), 0, NEED_RELOAD_IC},
+};
+
+const unsigned int cfg_lut_elements = sizeof(cfg_lut)/sizeof(struct config_lookup_table);
diff --git a/src/cfg_var.h b/src/cfg_var.h
new file mode 100644
index 0000000..eae07aa
--- /dev/null
+++ b/src/cfg_var.h
@@ -0,0 +1,14 @@
+/*
+ * cfg_var.h
+ *
+ *  Created on: 10-09-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#ifndef CFG_VAR_H_
+#define CFG_VAR_H_
+
+extern const struct config_lookup_table cfg_lut[];
+extern const unsigned int cfg_lut_elements;
+
+#endif /* CFG_VAR_H_ */
diff --git a/src/comm.c b/src/comm.c
new file mode 100644
index 0000000..ed86ea5
--- /dev/null
+++ b/src/comm.c
@@ -0,0 +1,790 @@
+/*
+ * comm.c
+ *
+ *  Created on: 01-08-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+
+#include <xdc/std.h>
+
+#include <string.h>
+#include <stdio.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sysbios/hal/Timer.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Clock.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/MultiProc.h>
+#include <ti/ipc/MessageQ.h>
+#include <ti/ipc/Notify.h>
+
+#include "version.h"
+#include "comm.h"
+#include "misc.h"
+#include "cfg_var.h"
+#include "tdefs.h"
+#include "logman.h"
+#include "spi.h"
+#include "logic_elements/elements.h"
+#include "logic_elements/events_reg.h"
+#include "logic_elements/dfr.h"
+#include "logic_elements/ddr.h"
+#include "logic_elements/measurand.h"
+#include "logic_elements/leds_drv.h"
+#include "logic_elements/virt_in_drv.h"
+#include "logic_elements/dfr_drv.h"
+#include "logic_elements/ddr_drv.h"
+#include "logic_elements/rec_float.h"
+#include "logic_elements/rec_an.h"
+#include "logic_elements/rec_buf.h"
+#include "logic_elements/analog_in.h"
+#include "logic_elements/event.h"
+#include "logic_elements/events_reg.h"
+#include "logic_elements/dev_ctrl.h"
+#include "logic_elements/an_gen.h"
+#include "logic_elements/events_reg.h"
+#include "logic_elements/mki7.h"
+#include "logic_elements/mki7_2.h"
+#include "config.h"
+/// ethernet
+#include "ethernet/ports/am1808/include/lwiplib.h"
+#include "ethernet/emac.h"
+#include "ports/am1808/include/netif/sitaraif.h"
+#include <ti/sysbios/hal/Hwi.h>
+///
+
+Timer_Handle tick_timer_handle;
+u32 tick_timer_period;
+static MessageQ_Handle	msgqueue_local;
+struct notify_data notify;
+struct broadcast_info bcast_nfo;
+volatile struct ping_info ping_nfo;
+
+struct eth_data eth = { .flags = 0 };
+
+volatile u8 saved_bank = 0;
+
+//u8 time_good=0;
+
+Void commFxn(UArg a0, UArg a1) 
+{
+	struct timeval cur_time_old;
+	int status = 0;
+	UInt16 remoteProcId;
+	MessageQ_Params msgqParams;
+	struct msg_data *msg;
+	int ret;
+	u8 may_sync_hw;
+	u8 may_sync_sw;
+	MessageQ_QueueId msgqueue_id_remote;
+	int offset;
+	struct parsed_cfg_transport_line *line = (struct parsed_cfg_transport_line *)shared_buf;
+	int i;
+	float tmp;
+	int tmpstate;
+	u8 *off;
+	char firm_ver[40];
+	u8 first_tsync=1;
+	u16 kob_bin=0;
+
+	snprintf(firm_ver,sizeof(firm_ver),SW_VER" %u",(u32)ic->fpga_verl|((u32)ic->fpga_verh<<16));
+
+	tick_timer_handle = Clock_getTimerHandle();
+	tick_timer_period = Timer_getPeriod(tick_timer_handle);
+	dbg.tick_period = tick_timer_period;
+	dbg.logman_buf_capacity = sizeof(log_manager.buf);
+
+    do
+    {
+    	Task_sleep(1);
+    	status = Ipc_start();
+    }
+    while(status == Ipc_E_NOTREADY);
+
+    remoteProcId = MultiProc_getId("HOST");
+
+    do
+    {
+		Task_sleep(1);
+    	status = Ipc_attach(remoteProcId);
+    } while(status == Ipc_E_NOTREADY);
+
+    MessageQ_Params_init(&msgqParams);
+
+    msgqueue_local = MessageQ_create("MsgQdsp", &msgqParams);
+
+    if(msgqueue_local == NULL)
+    	System_printf("queue failed\n");
+    else
+    	System_printf("queue succ\n");
+
+// notify subsystem from dsp to arm
+
+    notify.lineId               = 0;
+    notify.eventId              = 7;
+    notify.remoteProcId         = remoteProcId;
+
+    do
+    {
+        status = Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_INIT, TRUE);
+
+        if (status == Notify_E_EVTNOTREGISTERED)
+            Task_sleep(10);
+
+    } while (status == Notify_E_EVTNOTREGISTERED);
+
+    for(;;)
+    {
+    	status = MessageQ_get(msgqueue_local, (MessageQ_Msg *)&msg, MessageQ_FOREVER);
+    	if(status == 0)
+    	{
+    		msgqueue_id_remote = MessageQ_getReplyQueue(msg);
+    		switch(msg->cmd)
+    		{
+    			case DSP_CMD_INIT_COMM:
+    				msg->p1 = CMD_ACK;
+    				if(msg->p2 == 0xAA55AA55) // neg pps
+    				    ic->sync_reg=0;
+
+    				while(!spi_fram_restored)
+    					Task_sleep(100); // wait for spi first read
+
+    				msg->p3 = saved_bank;
+
+    				break;
+
+    			case DSP_CMD_GET_ANALOG_BUF:
+    				analog_buf_card = msg->p1;
+    	 			analog_buf_channel = msg->p2;
+
+    	 			for(i=0;i<127;i++)
+    					analog_buf[i]=(short)bus_an_samples_buf[analog_buf_card][analog_buf_channel][(bus_an_cur_sample_num+i)%(SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2)] - 32767;
+
+    				memcpy((char*)shared_buf,(char*)analog_buf,sizeof(analog_buf));
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = sizeof(analog_buf);
+    				break;
+
+    			case DSP_CMD_GET_MEASURANDS:
+
+    				switch(msg->p1)
+    				{
+						case 0:
+	 						for(i=0;i<measurands.count;i++)
+							{
+								*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
+							/*	if(i<=6)
+									tmp=debug_size[i];
+								else*/
+									tmp=*(measurands.value[i]);
+								memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
+							}
+							break;
+						case 1:
+							for(i=0;i<measurands.count;i++)
+							{
+								*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
+								tmp=*(measurands.value_pri[i]);
+								memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
+							}
+							break;
+						case 2:
+							for(i=0;i<measurands.count;i++)
+							{
+								*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
+								tmp=*(measurands.value_sec[i]);
+								memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
+							}
+							break;
+						default:
+							for(i=0;i<measurands.count;i++)
+							{
+								*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
+								tmp=*(measurands.value[i]);
+								memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
+							}
+							break;
+    				}
+
+    				msg->p2 = sizeof(shared_buf);
+    				msg->p3 = measurands.count;
+
+    				break;
+
+    			case DSP_CMD_GET_FWVER:
+   					memcpy((char *)shared_buf,firm_ver,40);
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = sizeof(shared_buf);
+    				break;
+
+    			case DSP_CMD_GET_NET_BUF:
+    				offset=0;
+    				// maybe use semaphore to avoid race condition
+    				memcpy((char*)shared_buf,(char*)&log_manager.nets_data[msg->p1],256);
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = offset;
+    				break;
+
+    			case DSP_CMD_GET_IO_BUF:
+    				offset=0;
+    				// maybe use semaphore to avoid race condition
+    				//memcpy((char*)shared_buf,(char*)ic->bin_in,sizeof(ic->bin_in));
+    				//offset=sizeof(ic->bin_in);
+    				memcpy((char*)shared_buf,(char*)bus_bin_data,sizeof(bus_bin_data));
+    				offset=sizeof(bus_bin_data);
+    				memcpy((char*)shared_buf+offset,(char *)ic->out_set,sizeof(ic->out_set));
+    				offset+=sizeof(ic->out_set);
+    				memcpy((char*)shared_buf+offset,(char *)&ic->kob_an,12); // kobs and errs
+    				offset+=2;
+
+    				kob_bin=ic->kob_bin;
+    				for(i=0;i<8;i++)
+    				{
+    					if(mwd32_mask & (1<<i))
+    					{
+    						if(kob_bin & (1<<i))
+    							kob_bin|=(1<<(i+8));
+    						else
+    							kob_bin&=~(1<<(i+8));
+    					}
+    				}
+
+    				memcpy((char*)shared_buf+offset,(char *)&kob_bin,2); // kobs and errs
+    				offset+=2;
+
+    				memcpy((char*)shared_buf+offset,(char *)&ic->kob_out,8); // kobs and errs
+    				offset+=8;
+
+
+
+
+    				memcpy((char*)shared_buf+offset,(char *)&samples_dropped,2);
+    				offset+=2;
+    				memcpy((char*)shared_buf+offset,(char*)bus_bin_data_ench,sizeof(bus_bin_data_ench));
+    				offset+=sizeof(bus_bin_data_ench);
+
+
+    				for(i=0;i<8;i++)
+    				{
+    					if(mwd32_mask & (1<<i))
+    					{
+    						if(ic->kob_bin & (1<<i))
+    							kob_bin_ench|=(1<<i) | (1<<(i+8));
+    						else
+    							kob_bin_ench&=~((1<<i) | (1<<(i+8)));
+    					}
+    					else
+							kob_bin_ench&=~((1<<i) | (1<<(i+8)));
+    				}
+
+    				memcpy((char*)shared_buf+offset,(char*)&kob_bin_ench,sizeof(kob_bin_ench));
+    				offset+=sizeof(kob_bin_ench);
+
+
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = offset;
+    				break;
+
+    			case DSP_CMD_GET_LEDS_VIRT_IN:
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = 16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2)+8;//+MAX_BIN_CARDS;
+    				memcpy((char*)shared_buf+0,(char *)&led_states,4);
+    				memcpy((char*)shared_buf+4,(char *)&led_blink_states,4);
+    				memcpy((char*)shared_buf+8,(char *)&virt_in_mask,4);
+    				memcpy((char*)shared_buf+12,(char *)&virt_in_states,4);
+    				memcpy((u8*)shared_buf+16,(u8*)force_bus_bin_data,MAX_BIN_CARDS);
+    				memcpy((u8*)shared_buf+16+MAX_BIN_CARDS,(u8*)force_bus_out_data,MAX_OUT_CARDS*2);
+    				memcpy((char*)shared_buf+16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2),(char *)&virt_in2_mask,4);
+    				memcpy((char*)shared_buf+16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2)+4,(char *)&virt_in2_states,4);
+
+//    				memcpy((char*)shared_buf+16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2)+4+4,(char *)&force_bus_bin_data_ench,MAX_BIN_CARDS);
+
+    				break;
+
+    			case DSP_CMD_GET_GI:
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = sizeof(shared_buf);
+
+    				if(ev_reg_log==NULL)
+    				{
+    					msg->p3 = 0;
+    					break;
+    				}
+    				else
+    					msg->p3 = ev_reg_log->events_count;
+
+    				if(msg->p3>1024)
+    					msg->p3=1024;
+
+    				for(i=0;i<msg->p3;i++)
+    				{
+    					struct event_args *ev_args;
+    					struct event_logic *ev_log;
+    					u32 data;
+
+    					ev_args = (struct event_args *)log_manager.log_element[ev_reg_log->element_num[i]].fun_args_ptr;
+    					ev_log = (struct event_logic *)log_manager.log_element[ev_reg_log->element_num[i]].fun_log_ptr;
+
+    					data=((u32)ev_args->params.fun<<16)|((u32)ev_args->params.inf<<8)|ev_log->prev_state;
+    					memcpy((char*)shared_buf+(i<<2),(char *)&data,4);
+    				}
+    				break;
+
+    			case DSP_CMD_SET_VIRT_IN:
+    				tmpstate=virt_in_states & ~msg->p1;
+    				virt_in_states = tmpstate|(msg->p1 & msg->p2);
+    				break;
+
+    			case DSP_CMD_SET_VIRT_IN2:
+    				tmpstate=virt_in2_states & ~msg->p1;
+    				virt_in2_states = tmpstate|(msg->p1 & msg->p2);
+    				break;
+
+    			case DSP_CMD_FORCE_OUT_STATES:
+    				msg->p1 = CMD_ACK;
+    				msg->p2 = dev_ctrl_state;
+    				memcpy((u8*)force_bus_out_data,(u8*)shared_buf,MAX_OUT_CARDS*2);
+    				break;
+
+    			case DSP_CMD_FORCE_BIN_STATES:
+    				memcpy((u8*)force_bus_bin_data,(u8*)shared_buf,MAX_BIN_CARDS);
+    				if(msg->p1==0xBEEF)
+    					memcpy((u8*)force_bus_bin_data_ench,(u8*)shared_buf+MAX_BIN_CARDS,MAX_BIN_CARDS);
+    				msg->p1 = CMD_ACK;
+    				msg->p2 = dev_ctrl_state;
+    				break;
+
+    			case DSP_CMD_FORCE_AN_STATES:
+    				msg->p1 = CMD_ACK;
+    				msg->p2 = dev_ctrl_state;
+    				memcpy((u8*)&genpar,(u8*)shared_buf,sizeof(genpar));
+    				break;
+
+    			case DSP_CMD_GET_AN_STATES:
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = sizeof(genpar);
+    				memcpy((u8*)shared_buf,(u8*)&genpar,sizeof(genpar));
+    				break;
+
+    			case DSP_CMD_GET_SHARED_BUF:
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = sizeof(shared_buf);
+    				break;
+
+    			case DSP_CMD_UPDATE_CFG:
+    				msg->p1 = CMD_ERR;
+
+    				for(i=0;i<cfg_lut_elements;i++)
+    				{
+    					if(!strcmp(cfg_lut[i].name,line->name))
+    					{
+    						if(cfg_lut[i].type == line->type)
+    						{
+    							switch(line->type)
+    							{
+									case ARG_TYPE_BOOL:
+										switch(cfg_lut[i].size)
+										{
+											case sizeof(unsigned char):
+												if(line->bool_val)
+													*((unsigned char*)cfg_lut[i].addr)|=cfg_lut[i].bit_mask;
+												else
+													*((unsigned char*)cfg_lut[i].addr)&=~cfg_lut[i].bit_mask;
+												msg->p1=CMD_ACK;
+												break;
+
+											case sizeof(unsigned short):
+												if(line->bool_val)
+													*((unsigned short*)cfg_lut[i].addr)|=cfg_lut[i].bit_mask;
+												else
+													*((unsigned short*)cfg_lut[i].addr)&=~cfg_lut[i].bit_mask;
+												msg->p1=CMD_ACK;
+												break;
+
+											case sizeof(unsigned int):
+												if(line->bool_val)
+													*((unsigned int*)cfg_lut[i].addr)|=cfg_lut[i].bit_mask;
+												else
+													*((unsigned int*)cfg_lut[i].addr)&=~cfg_lut[i].bit_mask;
+												msg->p1=CMD_ACK;
+												break;
+
+											default:
+												msg->p1=CMD_ERR;
+												break;
+										}
+										break;
+
+									case ARG_TYPE_DOUBLE:
+		    							msg->p1=CMD_ACK;
+										memcpy((char *)cfg_lut[i].addr,(char *)&line->double_val,cfg_lut[i].size);
+										break;
+									case ARG_TYPE_LONG:
+		    							msg->p1=CMD_ACK;
+										memcpy((char *)cfg_lut[i].addr,(char *)&line->long_val,cfg_lut[i].size);
+										break;
+									case ARG_TYPE_TEXT:
+		    							msg->p1=CMD_ACK;
+										memcpy((char *)cfg_lut[i].addr,(char *)line->text_val,cfg_lut[i].size);
+										break;
+									default:
+		    							msg->p1=CMD_ERR;
+										break;
+    							}
+
+    							if(msg->p1==CMD_ACK && (cfg_lut[i].flags & NEED_RELOAD_IC))
+    								reload_ic_cfg();
+
+    							break;
+
+    						}
+    						else
+    						{
+    							msg->p1=CMD_ERR;
+    							break;
+    						}
+    					}
+    				}
+    				break;
+
+    			case DSP_CMD_GET_REG_INF:
+    				memcpy((u8*)shared_buf,(u8*)&regs,sizeof(regs));
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = offset;
+    				break;
+
+    			case DSP_CMD_GET_DDR_REG_INF:
+    				memcpy((u8*)shared_buf,(u8*)&ddr_regs,sizeof(ddr_regs));
+    				msg->p1 = (Uint32)shared_buf;
+    				msg->p2 = offset;
+    				break;
+
+    			case DSP_CMD_GET_REG_MULTIPLIERS:
+    				if(dfr_drv_log_ptr == NULL) // dfr driver not initialized?
+    				{
+    					msg->p1 = CMD_ERR;
+    					break;
+    				}
+
+    				msg->p1 = CMD_ACK;
+					off = (u8 *)shared_buf;
+
+					msg->p2 = dfr_drv_log_ptr->an_count;
+
+
+					for(i=0;i<dfr_drv_log_ptr->an_count;i++)
+					{
+						struct rec_an_logic *an_log;
+						struct rec_buf_logic *an_buf_log;
+						struct rec_float_args *float_args;
+						struct rec_float_logic *float_log;
+						struct dfr_an_comtrade_params an_comtrade_params;
+
+						if(dfr_drv_log_ptr->element_num[i] & ELEMENT_IS_REC_FLOAT)
+						{
+							float_args = (struct rec_float_args *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_args_ptr;
+							float_log = (struct rec_float_logic *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
+							an_comtrade_params.multiplier=float_log->mul;
+							an_comtrade_params.primary=float_args->params.pierw;
+							an_comtrade_params.secondary=float_args->params.wtor;
+							an_comtrade_params.unit=float_args->params.jednostka | AN_IS_FLOAT;
+						}
+						else if(dfr_drv_log_ptr->element_num[i] & ELEMENT_IS_REC_BUF)
+						{
+							an_buf_log = (struct rec_buf_logic *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
+							an_comtrade_params.multiplier=an_buf_log->an_params->multiplier;
+							an_comtrade_params.primary=an_buf_log->an_params->znam_pierw;
+							an_comtrade_params.secondary=an_buf_log->an_params->znam_wtor;
+							an_comtrade_params.unit=an_buf_log->an_params->jednostka & 0x7FFFFFFF;
+						}
+						else
+						{
+							an_log = (struct rec_an_logic *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
+							an_comtrade_params.multiplier=an_log->an_params->multiplier;
+							an_comtrade_params.primary=an_log->an_params->znam_pierw;
+							an_comtrade_params.secondary=an_log->an_params->znam_wtor;
+							an_comtrade_params.unit=an_log->an_params->jednostka & 0x7FFFFFFF;
+						}
+
+						memcpy(off,(u8 *)&an_comtrade_params,sizeof(an_comtrade_params));
+						off+=sizeof(an_comtrade_params);
+					}
+    				break;
+
+    			case DSP_CMD_GET_REG_MULTIPLIERS_DDR:
+    				if(ddr_drv_log_ptr == NULL) // ddr driver not initialized?
+    				{
+    					msg->p1 = CMD_ERR;
+    					break;
+    				}
+
+    				msg->p1 = CMD_ACK;
+					off = (u8 *)shared_buf;
+
+					msg->p2 = ddr_drv_log_ptr->an_count;
+
+					for(i=0;i<ddr_drv_log_ptr->an_count;i++)
+					{
+						struct rec_float_args *float_args;
+						struct rec_float_logic *float_log;
+						struct dfr_an_comtrade_params an_comtrade_params;
+
+						if(ddr_drv_log_ptr->element_num[i] & ELEMENT_IS_REC_FLOAT)
+						{
+							float_args = (struct rec_float_args *)log_manager.log_element[ddr_drv_log_ptr->element_num[i] & 0x3FFF].fun_args_ptr;
+							float_log = (struct rec_float_logic *)log_manager.log_element[ddr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
+							an_comtrade_params.multiplier=float_log->mul;
+							an_comtrade_params.primary=float_args->params.pierw;
+							an_comtrade_params.secondary=float_args->params.wtor;
+							an_comtrade_params.unit=float_args->params.jednostka | AN_IS_FLOAT;
+						}
+						memcpy(off,(u8 *)&an_comtrade_params,sizeof(an_comtrade_params));
+						off+=sizeof(an_comtrade_params);
+					}
+    				break;
+
+    			case DSP_CMD_ACK_REG:
+    				if(msg->p1<MAX_REG_BANKS)
+    				{
+    					if(regs.bank[msg->p1].state == BANK_FILLED)
+    						regs.bank[msg->p1].state = BANK_EMPTY;
+    				}
+    				break;
+
+    			case DSP_CMD_ACK_DDR_REG:
+    				if(msg->p1<DDR_MAX_REG_BANKS)
+    			 	{
+    					if(ddr_regs.bank[msg->p1].state == BANK_FILLED)
+    						ddr_regs.bank[msg->p1].state = BANK_EMPTY;
+    				}
+    				break;
+
+    			case DSP_CMD_CLEAR_RELAYS:
+    				for(i=0;i<MAX_OUT_CARDS;i++)
+    					ic->out_set[i]=0;
+    				msg->p1 = CMD_ACK;
+    				break;
+
+    			case DSP_CMD_TIME_SYNC:
+    				may_sync_hw = (first_tsync || (msg->p2<=950000 && msg->p2>=50000 && cur_time.tv_usec>=10 && cur_time.tv_usec<=990))?1:0;
+    				may_sync_sw = (first_tsync || (msg->p2<=950000 && msg->p2>=50000 && cur_time_sw.tv_usec>=10 && cur_time_sw.tv_usec<=990))?1:0;
+
+    				timesync_method=msg->p3 & 0xFF;
+    				timesync_bits=(msg->p3>>8) & 0xFF;
+
+    				if(timesync_bits & CFG_TSYNC_USE_SWCLK)
+    					cur_time_old = cur_time_sw;
+    				else
+    					cur_time_old = cur_time;
+
+    				if((timesync_method!=SYNC_METHOD_IRIG_B && timesync_method!=SYNC_METHOD_IRIG_B_ZPRAE && (timesync_method!=SYNC_METHOD_CUSTOM || !(timesync_bits & CFG_TSYNC_FROM_DSP)))||first_tsync)
+    				{
+        				if(may_sync_sw)
+        				{
+							cur_time_sw.tv_sec = msg->p1;
+        					if(!(timesync_bits & CFG_TSYNC_USE_SWPPS) || pps3_timeout_cnt>60000)
+        						cur_time_sw.tv_usec = msg->p2 / 1000;
+        				}
+
+        				if(may_sync_hw)
+    					{
+    						cur_time.tv_sec=msg->p1;
+    						first_tsync=0;
+    	    				if(!ext_sync)
+    	    					cur_time.tv_usec=msg->p2 / 1000;
+    					}
+    				}
+
+    				msg->p1=cur_time_old.tv_sec;
+    				msg->p2=cur_time_old.tv_usec;
+    				msg->p3=(dev_ctrl_state&DEV_CTRL_STATE_IRIGB_FIX_OK)?1:0;
+
+    				break;
+
+    			case DSP_CMD_CFG_STATE:
+    				if(msg->p1==SET_CFG_CHANGE)
+    					dev_ctrl_state|=DEV_CTRL_STATE_CFG_CHANGE;
+    				else if(msg->p1==SET_CFG_ERR)
+    					dev_ctrl_state|=DEV_CTRL_STATE_CFG_ERR;
+    				else if(msg->p1==SET_CFG_OK)
+    					dev_ctrl_state&=~DEV_CTRL_STATE_CFG_ERR;
+
+    				if(msg->p2 & 0x01)
+    					dev_ctrl_state|=DEV_CTRL_STATE_PTP_OK;
+    				else
+    					dev_ctrl_state&=~DEV_CTRL_STATE_PTP_OK;
+    				if(msg->p2 & 0x02)
+    					dev_ctrl_state|=DEV_CTRL_STATE_NTP_OK;
+    				else
+    					dev_ctrl_state&=~DEV_CTRL_STATE_NTP_OK;
+
+    				mki7_sfplinks=msg->p3;
+    				mki7_2_sfplinks=msg->p3>>8;
+
+    				break;
+
+    			case DSP_CMD_SET_EVENT_FILTER:
+    				events_reg_filter_act = msg->p1 ? 1 : 0;
+    				events_reg_filter_period = msg->p2 > 65535 ? 65535 : msg->p2;
+    				events_reg_filter_trans_limit = msg->p3 > 127 ? 127 : msg->p3;
+    				break;
+
+    			case DSP_CMD_LOGMAN_STOP:
+    				logman_stop();
+    				msg->p1 = CMD_ACK;
+    				break;
+
+    			case DSP_CMD_LOGMAN_RESET:
+    				logman_reset();
+    				msg->p1 = CMD_ACK;
+    				break;
+
+    			case DSP_CMD_LOGMAN_PUSHFUN:
+    				if(!(ret=logman_pushfunc(msg->p2,(void*)shared_buf,msg->p3)))
+    					msg->p1 = CMD_ACK;
+    				else
+    				{
+    					msg->p1 = CMD_ERR;
+    					msg->p2 = ret;
+    				}
+
+    				msg->p3 = (u32)log_manager.cur_buf_ptr;
+    				break;
+
+    			case DSP_CMD_LOGMAN_START:
+    				saved_bank = msg->p1>5?0:msg->p1;
+    				if(!(ret = logman_start()))
+    					msg->p1 = CMD_ACK;
+    				else
+    				{
+    					msg->p1 = CMD_ERR;
+    					msg->p2 = ret;
+    				}
+
+    				break;
+
+    			case DSP_CMD_DEBUGLOG:
+    				if(msg->p1)
+    					dev_ctrl_state|=DEV_CTRL_STATE_SD_ERR;
+    				else if(dev_ctrl_state & DEV_CTRL_STATE_SD_ERR)
+    					dev_ctrl_state&=~DEV_CTRL_STATE_SD_ERR;
+
+    				dev_ctrl_state&=0x0000FFFF;
+    				dev_ctrl_state|=(msg->p2&0xFFFF)<<16;
+
+    				msg->p1 = CMD_ACK;
+    				dbg.delta_period = ic->delta_period_50M;
+    				dbg.phase_corr = ic->phase_corr;
+    				dbg.sync_reg = ic->sync_reg;
+    				dbg.max_elements = MAX_LOG_ELEMENTS;
+    				dbg.nets_bufsize = LOGMAN_NETSDATA_SIZE;
+    				memcpy((u8*)shared_buf,(u8*)&dbg,sizeof(dbg));
+    				break;
+
+    			case DSP_CMD_GET_EV_BUF:
+    				msg->p1 = CMD_ACK;
+    				memcpy((u8*)shared_buf,(u8*)&ev_db,sizeof(ev_db));
+    				break;
+
+    			case DSP_CMD_GET_PROFILE_BUF:
+    				msg->p1 = (Uint32)shared_buf;
+    				memcpy((u8*)shared_buf,(u8*)&log_profile,sizeof(log_profile));
+    				break;
+
+    			case DSP_CMD_GET_LOGIC_EL_PARAMS:
+    				msg->p1 = (Uint32)shared_buf;
+
+    				i=0;
+    				while(log_elements[i].id!=EOF_ELEMENT && log_elements[i].id<1024 && i<2048)
+    				{
+    					shared_buf[i]=((u32)log_elements[i].log_size<<16) |(u32)log_elements[i].args_size;
+    					i++;
+    				}
+
+    				msg->p2=i;
+    				break;
+
+    			case DSP_CMD_START_PROFILER:
+    				memset(&log_profile,0,sizeof(log_profile));
+    				dbg.logman_cycle_time_max=0;
+    				log_manager.status|=LOGMAN_STATUS_PROFILING;
+    				msg->p1 = CMD_ACK;
+    				break;
+
+    			case DSP_CMD_STOP_PROFILER:
+    				log_manager.status&=~LOGMAN_STATUS_PROFILING;
+    				msg->p1 = CMD_ACK;
+    				break;
+
+    			case DSP_CMD_ETH_ON:
+					memcpy(eth.hwaddr,(char*)shared_buf,sizeof(eth.hwaddr));
+					memcpy(eth.name,(char*)shared_buf+sizeof(eth.hwaddr),sizeof(eth.name));
+					memcpy((char *)&eth.dev_no,(char*)shared_buf+sizeof(eth.hwaddr)+sizeof(eth.name),sizeof(eth.dev_no));
+					memcpy((char *)&eth.unicast_ip,(char*)shared_buf+sizeof(eth.hwaddr)+sizeof(eth.name)+sizeof(eth.dev_no),sizeof(eth.unicast_ip));
+
+					eth.ip=msg->p1;
+					eth.netmask=msg->p2;
+					eth.gateway=msg->p3;
+					eth.flags|=ETH_GOT_SETTINGS;
+
+					lwIPInit(0, eth.hwaddr, eth.ip, eth.netmask, eth.gateway, IPADDR_USE_STATIC);
+
+					memcpy((u8 *)bcast_nfo.id,"ZP6",3);
+					memcpy((u8 *)bcast_nfo.dev_name,"DSP ",4);
+					memcpy((u8 *)bcast_nfo.dev_name+4,eth.name,16);
+					bcast_nfo.dev_name[20]=0;
+					bcast_nfo.mlb_type=ZPRAE_MLB12_TYPE;
+					bcast_nfo.dev_type=0;
+					bcast_nfo.dev_num=eth.dev_no;
+					memcpy((u8 *)bcast_nfo.mac,eth.hwaddr,6);
+
+					eth.flags|=ETH_INITIALIZED;
+					Hwi_enableInterrupt(10);
+					Hwi_enableInterrupt(11);
+/*
+					EMACTxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 0, 0);
+					EMACRxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 0, 0);
+					Hwi_disableInterrupt(10);
+					Hwi_disableInterrupt(11);
+					sitaraif_save_descriptors();
+*/
+    				msg->p1 = CMD_ACK;
+    				break;
+
+    			case DSP_CMD_ETH_OFF:
+    				msg->p1 = CMD_ACK;
+    				//if(eth.flags & ETH_ACTIVE)
+    				{
+						//EMACTxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 1, 1);
+						//EMACRxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 1, 1);
+						Hwi_disableInterrupt(10);
+						Hwi_disableInterrupt(11);
+						eth.flags&=~ETH_ACTIVE;
+    				}
+
+    				break;
+
+    			case DSP_CMD_ETH_OFF_ACK:
+    				msg->p1 = CMD_ACK;
+    				eth.flags|=ETH_OFF_ACK;
+
+    				break;
+
+    			default:
+    				msg->cmd = CMD_ERR;
+    				msg->p1 = CMD_ERR;
+    				break;
+    		}
+
+    		MessageQ_put(msgqueue_id_remote, (MessageQ_Msg)msg);
+    	}
+
+    }
+}
+
diff --git a/src/comm.h b/src/comm.h
new file mode 100644
index 0000000..f98e566
--- /dev/null
+++ b/src/comm.h
@@ -0,0 +1,150 @@
+/*
+ * comm.h
+ *
+ *  Created on: 01-08-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#ifndef COMM_H_
+#define COMM_H_
+
+#include <ti/ipc/MessageQ.h>
+#include <ti/sysbios/hal/Timer.h>
+#include "tdefs.h"
+
+#define DSP_CMD_INIT_COMM				0x01
+#define DSP_CMD_GET_ANALOG_BUF			0x02
+#define DSP_CMD_GET_IO_BUF				0x03
+#define DSP_CMD_GET_SHARED_BUF			0x04
+#define DSP_CMD_UPDATE_CFG				0x05
+#define DSP_CMD_GET_REG_INF				0x06
+#define DSP_CMD_ACK_REG					0x07
+#define DSP_CMD_TIME_SYNC				0x08
+#define DSP_CMD_LOGMAN_STOP				0x09
+#define DSP_CMD_LOGMAN_RESET			0x0A
+#define DSP_CMD_LOGMAN_PUSHFUN			0x0B
+#define DSP_CMD_LOGMAN_START			0x0C
+#define DSP_CMD_LOGMAN_STATS			0x0D
+#define DSP_CMD_GET_REG_MULTIPLIERS		0x0E
+#define DSP_CMD_GET_REG_MULTIPLIERS_DDR	0x0F
+#define DSP_CMD_GET_EV_BUF				0x10
+#define DSP_CMD_GET_MEASURANDS			0x11
+#define DSP_CMD_GET_LEDS_VIRT_IN		0x12
+#define DSP_CMD_SET_VIRT_IN				0x13
+#define DSP_CMD_GET_NET_BUF				0x14
+#define DSP_CMD_GET_GI					0x15
+#define DSP_CMD_GET_FWVER				0x16
+#define DSP_CMD_FORCE_OUT_STATES		0x17
+#define DSP_CMD_FORCE_BIN_STATES		0x18
+#define DSP_CMD_GET_DDR_REG_INF			0x19
+#define DSP_CMD_ACK_DDR_REG				0x1A
+#define DSP_CMD_FORCE_AN_STATES			0x1B
+#define DSP_CMD_GET_AN_STATES			0x1C
+#define DSP_CMD_SET_EVENT_FILTER		0x1D
+#define DSP_CMD_CFG_STATE				0x1E
+#define DSP_CMD_CLEAR_RELAYS			0x1F
+#define DSP_CMD_SET_VIRT_IN2			0x20
+#define DSP_CMD_ETH_ON					0x21
+#define DSP_CMD_ETH_OFF					0x22
+#define DSP_CMD_GET_PROFILE_BUF			0x23
+#define DSP_CMD_START_PROFILER			0x24
+#define DSP_CMD_STOP_PROFILER			0x25
+#define DSP_CMD_ETH_OFF_ACK				0x26
+#define DSP_CMD_GET_LOGIC_EL_PARAMS		0x27
+#define DSP_CMD_DEBUGLOG				0xFE
+
+#define SET_CFG_CHANGE					0x01
+#define SET_CFG_OK						0x02
+#define SET_CFG_ERR						0x03
+
+#define CMD_ACK					0xD5
+#define CMD_ERR					0xE0
+
+struct msg_data
+{
+	MessageQ_MsgHeader hdr;
+	UInt32 cmd;
+	UInt32 p1;
+	UInt32 p2;
+	UInt32 p3;
+};
+
+struct notify_data
+{
+    UInt16          remoteProcId;
+    UInt16          lineId;
+    UInt32          eventId;
+};
+
+struct dfr_an_comtrade_params
+{
+	double multiplier;
+	double primary;
+	double secondary;
+	long unit;
+}__attribute__((__packed__));
+
+extern struct notify_data notify;
+extern struct broadcast_info bcast_nfo;
+extern volatile struct ping_info ping_nfo;
+extern volatile u8 saved_bank;
+
+#define ZPRAE_MLB12_TYPE	43
+
+struct broadcast_info {
+	u8 id[3];
+	u8 mlb_type;
+	u8 dev_name[21];
+	u8 dev_type;
+	u16 dev_num;
+	u8 mac[6];
+}__attribute__((__packed__));
+
+struct ping_info {
+	u8 adr;
+	u8 seq;
+	u16 tstamp;
+	u32 pwmval;
+}__attribute__((__packed__));
+
+struct eth_data
+{
+	u32 ip;
+	u32 netmask;
+	u32 gateway;
+	u8 hwaddr[6];
+	u32 flags;
+	u8 name[21];
+	u16 dev_no;
+	u32 unicast_ip;
+}__attribute__((__packed__));
+
+// eth flags
+#define ETH_NOT_INITIALIZED		0x00
+#define ETH_INITIALIZED			0x01
+#define ETH_ACTIVE				0x02
+#define ETH_GOT_SETTINGS		0x04
+#define ETH_UDP_INITIALIZED		0x08
+#define ETH_OFF_ACK				0x10
+
+extern struct eth_data eth;
+
+#define NOTIFY_INIT			0x00000001
+#define NOTIFY_NEW_EVENTS	0x00000002
+#define NOTIFY_NEW_DFR_REG	0x00000003
+#define NOTIFY_SEL_BANK0	0x00000004
+#define NOTIFY_SEL_BANK1	0x00000005
+#define NOTIFY_SEL_BANK2	0x00000006
+#define NOTIFY_SEL_BANK3	0x00000007
+#define NOTIFY_SEL_BANK4	0x00000008
+#define NOTIFY_NEW_DDR_REG	0x00000009
+#define NOTIFY_ETH_ON		0x0000000a
+#define NOTIFY_ETH_OFF		0x0000000b
+#define NOTIFY_SEL_BANK5	0x0000000c
+
+extern Timer_Handle tick_timer_handle;
+extern u32 tick_timer_period;
+
+extern Void commFxn(UArg a0, UArg a1);
+
+#endif /* COMM_H_ */
diff --git a/src/config.h b/src/config.h
new file mode 100644
index 0000000..f253c9c
--- /dev/null
+++ b/src/config.h
@@ -0,0 +1,41 @@
+/*
+ * config.h
+ *
+ *  Created on: 12-01-2021
+ *      Author: kjakubczyk
+ */
+
+#ifndef CONFIG_H_
+#define CONFIG_H_
+
+#define MAX_LOG_ELEMENTS		1050+10+20 // max logman elements // 20 dodano 26.08.2024 przy TZL
+
+#define LOOP_CYCLE_MS			2  	// how many ms between main logman loops
+#define SAMPLES_PER_MS			4  	// samples per ms -> 3 = 3kHz
+#define MAIN_FREQ_PERIOD_MS		20
+#define SAMPLES_INTERPOLATION 	1   // middle samples config in DFR => 0=sample_duplication, 1=linear interpolation, 2=NAN between
+									// WARNING! linear interpolation needs disable extmem caching for DFR in app.cfg
+
+#define IEC61850_ACTIVE			1 	// activate IEC61850 recv GOOSE/SV
+#define SV_I_CARD_ADDR			14
+#define SV_U_CARD_ADDR			15
+#define SV_WAIT_LOOP_CYCLES		1 	// delay by x main loop cycles to wait for SV samples
+#if IEC61850_ACTIVE==1
+#define IEC61850_MIN_FR_SIZE	64
+#define GOOSE_MAX_FR_SIZE		1100//bylo 1024 przed KAE
+#define GOOSE_MAX_FR_OUT_SIZE	256
+#define GOOSE_QUEUE_DEPTH		16
+#define SV_MIN_FR_SIZE			64
+#define SV_MAX_FR_SIZE			256
+#define SV_QUEUE_DEPTH			16
+#else
+#define IEC61850_MIN_FR_SIZE	1
+#define GOOSE_MAX_FR_SIZE		1
+#define GOOSE_QUEUE_DEPTH		1
+#define SV_MIN_FR_SIZE			1
+#define SV_MAX_FR_SIZE			1
+#define SV_QUEUE_DEPTH			1
+#endif
+
+
+#endif /* CONFIG_H_ */
diff --git a/src/hw_psc_OMAPL138.h b/src/hw_psc_OMAPL138.h
new file mode 100644
index 0000000..3371571
--- /dev/null
+++ b/src/hw_psc_OMAPL138.h
@@ -0,0 +1,285 @@
+/**
+ * \file  hw_psc_OMAPL138.h
+ *
+ * \brief Hardware definitions for OMAPL138
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_PSC_H_
+#define _HW_PSC_H_
+
+/* NOTE1
+ * The actual number of MDCTL and MDSTAT register depend on number of
+ * LPSC modules in a PSC. The number of MDCTL/MDSTAT registers defined
+ * here would be a superset
+ * e.g. PSC0 has 16 MDCTL/MDSTAT register, PSC1 has 32 MDCTL/MDSTAT
+ * registers                                                       */
+
+
+/* NOTE2
+ * Please refer to the device specific PSC user guide to see what
+ *  register bit fields apply to individual registers
+ *  e.g. For PSC0 MERRPR0 bits 14,15 exist but for PSC1 MERRPR0
+ *  these bits are RESERVED                                        */
+
+typedef enum {
+    HW_PSC_CC0              = 0,
+    HW_PSC_TC0              = 1,
+    HW_PSC_TC1              = 2,
+    HW_PSC_EMIFA            = 3,
+    HW_PSC_SPI0             = 4,
+    HW_PSC_MMCSD0           = 5,
+    HW_PSC_AINTC            = 6,
+    HW_PSC_ARM_RAMROM       = 7,
+    HW_PSC_UART0            = 9,
+    HW_PSC_SCR0_SS          = 10,
+    HW_PSC_SCR1_SS          = 11,
+    HW_PSC_SCR2_SS          = 12,
+    HW_PSC_PRU              = 13,
+    HW_PSC_ARM              = 14,
+    HW_PSC_DSP              = 15
+
+} Psc0Peripheral;
+
+typedef enum {
+    HW_PSC_CC1          = 0,
+    HW_PSC_USB0         = 1,
+    HW_PSC_USB1         = 2,
+    HW_PSC_GPIO         = 3,
+    HW_PSC_UHPI         = 4,
+    HW_PSC_EMAC         = 5,
+    HW_PSC_DDR2_MDDR    = 6,
+    HW_PSC_MCASP0       = 7,
+    HW_PSC_SATA         = 8,
+    HW_PSC_VPIF         = 9,
+    HW_PSC_SPI1         = 10,
+    HW_PSC_I2C1         = 11,
+    HW_PSC_UART1        = 12,
+    HW_PSC_UART2        = 13,
+    HW_PSC_MCBSP0       = 14,
+    HW_PSC_MCBSP1       = 15,
+    HW_PSC_LCDC         = 16,
+    HW_PSC_EHRPWM       = 17,
+    HW_PSC_MMCSD1       = 18,
+    HW_PSC_UPP          = 19,
+    HW_PSC_ECAP0_1_2    = 20,
+    HW_PSC_TC2          = 21,
+    HW_PSC_SCRF0_SS     = 24,
+    HW_PSC_SCRF1_SS     = 25,
+    HW_PSC_SCRF2_SS     = 26,
+    HW_PSC_SCRF6_SS     = 27,
+    HW_PSC_SCRF7_SS     = 28,
+    HW_PSC_SCRF8_SS     = 29,
+    HW_PSC_BR_F7        = 30,
+    HW_PSC_SHRAM        = 31
+} Psc1Peripheral;
+
+#define PSC_POWERDOMAIN_ALWAYS_ON    0
+#define PSC_POWERDOMAIN_PD_DSP       1
+
+#define PSC_REVID	(0x0)
+#define PSC_INTEVAL	(0x18)
+#define PSC_MERRPR0	(0x40)
+#define PSC_MERRCR0	(0x50)
+#define PSC_PERRPR	(0x60)
+#define PSC_PERRCR	(0x68)
+#define PSC_PTCMD	(0x120)
+#define PSC_PTSTAT	(0x128)
+#define PSC_PDSTAT0	(0x200)
+#define PSC_PDSTAT1	(0x204)
+#define PSC_PDCTL0	(0x300)
+#define PSC_PDCTL1	(0x304)
+#define PSC_PDCFG0	(0x400)
+#define PSC_PDCFG1	(0x404)
+#define PSC_MDSTAT(n)	(0x800 + (n * 4))
+#define PSC_MDCTL(n)	(0xA00 + (n * 4))
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVID */
+
+#define PSC_REVID_REV             (0xFFFFFFFFu)
+#define PSC_REVID_REV_SHIFT            (0x00000000u)
+
+/* INTEVAL */
+
+#define PSC_INTEVAL_ALLEV      (0x00000001u)
+#define PSC_INTEVAL_ALLEV_SHIFT     (0x00000000u)
+
+/* MERRPR0 */
+#define PSC_MERRPR0_M15        (0x0000C000u)
+#define PSC_MERRPR0_M15_SHIFT       (0x0000000Eu)
+#define PSC_MERRPR0_M14        (0x00006000u)
+#define PSC_MERRPR0_M14_SHIFT       (0x0000000Du)
+
+/* MERRCR0 */
+#define PSC_MERRCR0_M15        (0x0000C000u)
+#define PSC_MERRCR0_M15_SHIFT       (0x0000000Eu)
+#define PSC_MERRCR0_M14        (0x00006000u)
+#define PSC_MERRCR0_M14_SHIFT       (0x0000000Du)
+
+/* PERRPR */
+#define PSC_PERRPR_P1          (0x00000002u)
+#define PSC_PERRPR_P1_SHIFT         (0x00000001u)
+#define PSC_PERRPR_P0          (0x00000001u)
+#define PSC_PERRPR_P0_SHIFT         (0x00000000u)
+
+/* PERRCR */
+#define PSC_PERRCR_P1          (0x00000002u)
+#define PSC_PERRCR_P1_SHIFT         (0x00000001u)
+#define PSC_PERRCR_P0          (0x00000001u)
+#define PSC_PERRCR_P0_SHIFT         (0x00000000u)
+
+/* PTCMD */
+#define PSC_PTCMD_GO1          (0x00000002u)
+#define PSC_PTCMD_GO1_SHIFT         (0x00000001u)
+#define PSC_PTCMD_GO0          (0x00000001u)
+#define PSC_PTCMD_GO0_SHIFT         (0x00000000u)
+
+/* PTSTAT */
+#define PSC_PTSTAT_GOSTAT1     (0x00000002u)
+#define PSC_PTSTAT_GOSTAT1_SHIFT    (0x00000001u)
+#define PSC_PTSTAT_GOSTAT0     (0x00000001u)
+#define PSC_PTSTAT_GOSTAT0_SHIFT    (0x00000000u)
+
+/* PDSTAT0 */
+#define PSC_PDSTAT0_EMUIHB     (0x00000800u)
+#define PSC_PDSTAT0_EMUIHB_SHIFT    (0x0000000Bu)
+#define PSC_PDSTAT0_STATE      (0x0000001Fu)
+#define PSC_PDSTAT0_STATE_SHIFT     (0x00000000u)
+
+/* PDSTAT1 */
+#define PSC_PDSTAT1_EMUIHB     (0x00000800u)
+#define PSC_PDSTAT1_EMUIHB_SHIFT    (0x0000000Bu)
+#define PSC_PDSTAT1_STATE      (0x0000001Fu)
+#define PSC_PDSTAT1_STATE_SHIFT     (0x00000000u)
+
+/* PDCTL0 */
+#define PSC_PDCTL0_WAKECNT     (0x00FF0000u)
+#define PSC_PDCTL0_WAKECNT_SHIFT    (0x00000010u)
+#define PSC_PDCTL0_PDMODE      (0x0000F000u)
+#define PSC_PDCTL0_PDMODE_SHIFT     (0x0000000Cu)
+#define PSC_PDCTL0_EMUIHBIE    (0x00000200u)
+#define PSC_PDCTL0_EMUIHBIE_SHIFT   (0x00000009u)
+#define PSC_PDCTL0_NEXT        (0x00000001u)
+#define PSC_PDCTL0_NEXT_SHIFT       (0x00000000u)
+
+/* PDCTL1 */
+#define PSC_PDCTL1_WAKECNT     (0x00FF0000u)
+#define PSC_PDCTL1_WAKECNT_SHIFT    (0x00000010u)
+#define PSC_PDCTL1_PDMODE      (0x0000F000u)
+#define PSC_PDCTL1_PDMODE_SHIFT     (0x0000000Cu)
+/*----PDMODE Tokens----*/
+#define PSC_PDCTL1_PDMODE_OFF       (0x00000000u)
+#define PSC_PDCTL1_PDMODE_RAM_OFF   (0x00000008u)
+#define PSC_PDCTL1_PDMODE_DEEP_SLEEP (0x00000009u)
+#define PSC_PDCTL1_PDMODE_LIGHT_SLEEP (0x0000000Au)
+#define PSC_PDCTL1_PDMODE_RETENTION (0x0000000Bu)
+#define PSC_PDCTL1_PDMODE_ON        (0x0000000Fu)
+
+#define PSC_PDCTL1_EMUIHBIE    (0x00000200u)
+#define PSC_PDCTL1_EMUIHBIE_SHIFT   (0x00000009u)
+#define PSC_PDCTL1_NEXT        (0x00000001u)
+#define PSC_PDCTL1_NEXT_SHIFT       (0x00000000u)
+
+/* PDCFG0 */
+#define PSC_PDCFG0_PDLOCK      (0x00000008u)
+#define PSC_PDCFG0_PDLOCK_SHIFT     (0x00000003u)
+#define PSC_PDCFG0_ICEPICK     (0x00000004u)
+#define PSC_PDCFG0_ICEPICK_SHIFT    (0x00000002u)
+#define PSC_PDCFG0_RAM_PSM     (0x00000002u)
+#define PSC_PDCFG0_RAM_PSM_SHIFT    (0x00000001u)
+#define PSC_PDCFG0_ALWAYSON    (0x00000001u)
+#define PSC_PDCFG0_ALWAYSON_SHIFT   (0x00000000u)
+
+/* PDCFG1 */
+#define PSC_PDCFG1_PDLOCK      (0x00000008u)
+#define PSC_PDCFG1_PDLOCK_SHIFT     (0x00000003u)
+#define PSC_PDCFG1_ICEPICK     (0x00000004u)
+#define PSC_PDCFG1_ICEPICK_SHIFT    (0x00000002u)
+#define PSC_PDCFG1_RAM_PSM     (0x00000002u)
+#define PSC_PDCFG1_RAM_PSM_SHIFT    (0x00000001u)
+#define PSC_PDCFG1_ALWAYSON    (0x00000001u)
+#define PSC_PDCFG1_ALWAYSON_SHIFT   (0x00000000u)
+
+/* MDSTAT */
+#define PSC_MDSTAT_EMUIHB      (0x00020000u)
+#define PSC_MDSTAT_EMUIHB_SHIFT     (0x00000011u)
+#define PSC_MDSTAT_EMURST      (0x00010000u)
+#define PSC_MDSTAT_EMURST_SHIFT     (0x00000010u)
+#define PSC_MDSTAT_MCKOUT      (0x00001000u)
+#define PSC_MDSTAT_MCKOUT_SHIFT     (0x0000000Cu)
+#define PSC_MDSTAT_MRSTDONE    (0x00000800u)
+#define PSC_MDSTAT_MRSTDONE_SHIFT   (0x0000000Bu)
+#define PSC_MDSTAT_MRST        (0x00000400u)
+#define PSC_MDSTAT_MRST_SHIFT       (0x0000000Au)
+#define PSC_MDSTAT_LRSTDONE    (0x00000200u)
+#define PSC_MDSTAT_LRSTDONE_SHIFT   (0x00000009u)
+#define PSC_MDSTAT_LRST        (0x00000100u)
+#define PSC_MDSTAT_LRST_SHIFT       (0x00000008u)
+#define PSC_MDSTAT_STATE       (0x0000003Fu)
+#define PSC_MDSTAT_STATE_SHIFT      (0x00000000u)
+/*----STATE Tokens----*/
+#define PSC_MDSTAT_STATE_SWRSTDISABLE (0x00000000u)
+#define PSC_MDSTAT_STATE_SYNCRST    (0x00000001u)
+#define PSC_MDSTAT_STATE_AUTOSLEEP  (0x00000004u)
+#define PSC_MDSTAT_STATE_AUTOWAKE   (0x00000005u)
+
+/* MDCTL */
+#define PSC_MDCTL_FORCE        (0x80000000u)
+#define PSC_MDCTL_FORCE_SHIFT       (0x0000001Fu)
+
+#define PSC_MDCTL_EMUIHBIE     (0x00000400u)
+#define PSC_MDCTL_EMUIHBIE_SHIFT    (0x0000000Au)
+
+#define PSC_MDCTL_EMURSTIE     (0x00000200u)
+#define PSC_MDCTL_EMURSTIE_SHIFT    (0x00000009u)
+
+#define PSC_MDCTL_LRST         (0x00000100u)
+#define PSC_MDCTL_LRST_SHIFT        (0x00000008u)
+#define PSC_MDCTL_NEXT         (0x0000001Fu)
+#define PSC_MDCTL_NEXT_SHIFT        (0x00000000u)
+/*----NEXT Tokens----*/
+#define PSC_MDCTL_NEXT_SWRSTDISABLE (0x00000000u)
+#define PSC_MDCTL_NEXT_SYNCRST      (0x00000001u)
+#define PSC_MDCTL_NEXT_DISABLE      (0x00000002u)
+#define PSC_MDCTL_NEXT_ENABLE       (0x00000003u)
+#define PSC_MDCTL_NEXT_AUTOWAKE     (0x00000005u)
+
+#endif
diff --git a/src/hw_syscfg0_OMAPL138.h b/src/hw_syscfg0_OMAPL138.h
new file mode 100644
index 0000000..8d5cab0
--- /dev/null
+++ b/src/hw_syscfg0_OMAPL138.h
@@ -0,0 +1,2167 @@
+/**
+ * \name  hw_syscfg0_OMAPL138.h
+ *
+ * \brief Hardware definitions for OMAPL138
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _HW_SYSCFG0_H_
+#define _HW_SYSCFG0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SYSCFG0_REVID		(0x0)
+#define SYSCFG0_DIEIDR0		(0x8)
+#define SYSCFG0_DIEIDR1		(0xC)
+#define SYSCFG0_DIEIDR2		(0x10)
+#define SYSCFG0_DIEIDR3		(0x14)
+#define SYSCFG0_DEVIDR0		(0x18)
+#define SYSCFG0_BOOTCFG		(0x20)
+#define SYSCFG0_KICK0R		(0x38)
+#define SYSCFG0_KICK1R		(0x3C)
+#define SYSCFG0_HOST0CFG	(0x40)
+#define SYSCFG0_HOST1CFG	(0x44)
+#define SYSCFG0_IRAWSTAT	(0xE0)
+#define SYSCFG0_IENSTAT		(0xE4)
+#define SYSCFG0_IENSET		(0xE8)
+#define SYSCFG0_IENCLR		(0xEC)
+#define SYSCFG0_EOI		(0xF0)
+#define SYSCFG0_FLTADDRR	(0xF4)
+#define SYSCFG0_FLTSTAT		(0xF8)
+#define SYSCFG0_MSTPRI0		(0x110)
+#define SYSCFG0_MSTPRI1		(0x114)
+#define SYSCFG0_MSTPRI2		(0x118)
+#define SYSCFG0_PINMUX(n)	(0x120 + (n * 4))
+#define SYSCFG0_SUSPSRC		(0x170)
+#define SYSCFG0_CHIPSIG		(0x174)
+#define SYSCFG0_CHIPSIG_CLR	(0x178)
+#define SYSCFG0_CFGCHIP0	(0x17C)
+#define SYSCFG0_CFGCHIP1	(0x180)
+#define SYSCFG0_CFGCHIP2	(0x184)
+#define SYSCFG0_CFGCHIP3	(0x188)
+#define SYSCFG0_CFGCHIP4	(0x18C)
+
+/**************************************************************************\
+* Field Definition Macros
+\**************************************************************************/
+
+/* REVID */
+
+#define SYSCFG_REVID_REVID      (0xFFFFFFFFu)
+#define SYSCFG_REVID_REVID_SHIFT     (0x00000000u)
+
+
+/* DIEIDR0 */
+
+#define SYSCFG_DIEIDR0_DIEID0   (0xFFFFFFFFu)
+#define SYSCFG_DIEIDR0_DIEID0_SHIFT  (0x00000000u)
+
+
+/* DIEIDR1 */
+
+#define SYSCFG_DIEIDR1_DIEID1   (0xFFFFFFFFu)
+#define SYSCFG_DIEIDR1_DIEID1_SHIFT  (0x00000000u)
+
+
+/* DIEIDR2 */
+
+#define SYSCFG_DIEIDR2_DIEID2   (0xFFFFFFFFu)
+#define SYSCFG_DIEIDR2_DIEID2_SHIFT  (0x00000000u)
+
+
+/* DIEIDR3 */
+
+#define SYSCFG_DIEIDR3_DIEID3   (0xFFFFFFFFu)
+#define SYSCFG_DIEIDR3_DIEID3_SHIFT  (0x00000000u)
+
+
+/* DEVIDR0 */
+
+#define SYSCFG_DEVIDR0_DEVID0   (0xFFFFFFFFu)
+#define SYSCFG_DEVIDR0_DEVID0_SHIFT  (0x00000000u)
+
+
+/* BOOTCFG */
+
+
+#define SYSCFG_BOOTCFG_SMARTRFLX (0x0FFF0000u)
+#define SYSCFG_BOOTCFG_SMARTRFLX_SHIFT (0x00000010u)
+
+#define SYSCFG_BOOTCFG_BOOTMODE (0x0000FFFFu)
+#define SYSCFG_BOOTCFG_BOOTMODE_SHIFT (0x00000000u)
+
+
+/* CHIPREVIDR */
+
+
+#define SYSCFG_CHIPREVIDR_CHIPREVID (0x0000003Fu)
+#define SYSCFG_CHIPREVIDR_CHIPREVID_SHIFT (0x00000000u)
+
+
+/* KICK0R */
+
+#define SYSCFG_KICK0R_KICK0     (0xFFFFFFFFu)
+#define SYSCFG_KICK0R_KICK0_SHIFT    (0x00000000u)
+
+/* Unlock/Lock code for KICK0 */
+#define SYSCFG_KICK0R_UNLOCK    (0x83E70B13u)
+
+
+/* KICK1R */
+
+#define SYSCFG_KICK1R_KICK1     (0xFFFFFFFFu)
+#define SYSCFG_KICK1R_KICK1_SHIFT    (0x00000000u)
+
+/* Unlock/Lock code for KICK1 */
+#define SYSCFG_KICK1R_UNLOCK    (0x95A4F1E0u)
+
+/* HOST0CFG */
+
+#define SYSCFG_HOST0CFG_BOOTRDY (0x80000000u)
+#define SYSCFG_HOST0CFG_BOOTRDY_SHIFT (0x0000001Fu)
+
+
+
+/* HOST1CFG */
+
+#define SYSCFG_HOST1CFG_DSP_ISTP_RST_VAL (0x003FFFFFu)
+#define SYSCFG_HOST1CFG_DSP_ISTP_RST_VAL_SHIFT (0x0000000Au)
+
+
+/* IRAWSTAT */
+
+
+#define SYSCFG_IRAWSTAT_ADDRERR (0x00000002u)
+#define SYSCFG_IRAWSTAT_ADDRERR_SHIFT (0x00000001u)
+
+#define SYSCFG_IRAWSTAT_PROTERR (0x00000001u)
+#define SYSCFG_IRAWSTAT_PROTERR_SHIFT (0x00000000u)
+
+
+/* IENSTAT */
+
+
+#define SYSCFG_IENSTAT_ADDRERR  (0x00000002u)
+#define SYSCFG_IENSTAT_ADDRERR_SHIFT (0x00000001u)
+
+#define SYSCFG_IENSTAT_PROTERR  (0x00000001u)
+#define SYSCFG_IENSTAT_PROTERR_SHIFT (0x00000000u)
+
+
+/* IENSET */
+
+
+#define SYSCFG_IENSET_ADDRERR_EN (0x00000002u)
+#define SYSCFG_IENSET_ADDRERR_EN_SHIFT (0x00000001u)
+
+#define SYSCFG_IENSET_PROTERR_EN (0x00000001u)
+#define SYSCFG_IENSET_PROTERR_EN_SHIFT (0x00000000u)
+
+
+/* IENCLR */
+
+
+#define SYSCFG_IENCLR_ADDRERR_CLR (0x00000002u)
+#define SYSCFG_IENCLR_ADDRERR_CLR_SHIFT (0x00000001u)
+
+#define SYSCFG_IENCLR_PROTERR_CLR (0x00000001u)
+#define SYSCFG_IENCLR_PROTERR_CLR_SHIFT (0x00000000u)
+
+
+/* EOI */
+
+
+#define SYSCFG_EOI_EOIVECT      (0x000000FFu)
+#define SYSCFG_EOI_EOIVECT_SHIFT     (0x00000000u)
+
+
+/* FLTADDRR */
+
+#define SYSCFG_FLTADDRR_FLTADDR (0xFFFFFFFFu)
+#define SYSCFG_FLTADDRR_FLTADDR_SHIFT (0x00000000u)
+
+
+/* FLTSTAT */
+
+#define SYSCFG_FLTSTAT_ID       (0xFF000000u)
+#define SYSCFG_FLTSTAT_ID_SHIFT      (0x00000018u)
+
+#define SYSCFG_FLTSTAT_MSTID    (0x00FF0000u)
+#define SYSCFG_FLTSTAT_MSTID_SHIFT   (0x00000010u)
+
+
+#define SYSCFG_FLTSTAT_PRIVID   (0x00001E00u)
+#define SYSCFG_FLTSTAT_PRIVID_SHIFT  (0x00000009u)
+
+
+#define SYSCFG_FLTSTAT_NOSECACC (0x00000080u)
+#define SYSCFG_FLTSTAT_NOSECACC_SHIFT (0x00000007u)
+
+
+#define SYSCFG_FLTSTAT_TYPE     (0x0000003Fu)
+#define SYSCFG_FLTSTAT_TYPE_SHIFT    (0x00000000u)
+/*----TYPE Tokens----*/
+#define SYSCFG_FLTSTAT_TYPE_NOFLT    (0x00000000u)
+#define SYSCFG_FLTSTAT_TYPE_USREXE   (0x00000001u)
+#define SYSCFG_FLTSTAT_TYPE_USRWR    (0x00000002u)
+#define SYSCFG_FLTSTAT_TYPE_USRRD    (0x00000004u)
+#define SYSCFG_FLTSTAT_TYPE_SPREXE   (0x00000008u)
+#define SYSCFG_FLTSTAT_TYPE_SPRWR    (0x00000010u)
+#define SYSCFG_FLTSTAT_TYPE_SPRRD    (0x00000020u)
+
+
+/* MSTPRI0 */
+
+
+#define SYSCFG_MSTPRI0_SATA     (0x00700000u)
+#define SYSCFG_MSTPRI0_SATA_SHIFT    (0x00000014u)
+
+
+#define SYSCFG_MSTPRI0_UPP      (0x00070000u)
+#define SYSCFG_MSTPRI0_UPP_SHIFT     (0x00000010u)
+
+
+#define SYSCFG_MSTPRI0_DSP_CFG  (0x00007000u)
+#define SYSCFG_MSTPRI0_DSP_CFG_SHIFT (0x0000000Cu)
+
+
+#define SYSCFG_MSTPRI0_DSP_MDMA (0x00000700u)
+#define SYSCFG_MSTPRI0_DSP_MDMA_SHIFT (0x00000008u)
+
+
+#define SYSCFG_MSTPRI0_ARM_D    (0x00000070u)
+#define SYSCFG_MSTPRI0_ARM_D_SHIFT   (0x00000004u)
+
+
+#define SYSCFG_MSTPRI0_ARM_I    (0x00000007u)
+#define SYSCFG_MSTPRI0_ARM_I_SHIFT   (0x00000000u)
+
+
+/* MSTPRI1 */
+
+
+#define SYSCFG_MSTPRI1_VPIF_DMA_1 (0x70000000u)
+#define SYSCFG_MSTPRI1_VPIF_DMA_1_SHIFT (0x0000001Cu)
+
+
+#define SYSCFG_MSTPRI1_VPIF_DMA_0 (0x07000000u)
+#define SYSCFG_MSTPRI1_VPIF_DMA_0_SHIFT (0x00000018u)
+
+
+#define SYSCFG_MSTPRI1_EDMA31TC0 (0x00070000u)
+#define SYSCFG_MSTPRI1_EDMA31TC0_SHIFT (0x00000010u)
+
+
+#define SYSCFG_MSTPRI1_EDMA30TC1 (0x00007000u)
+#define SYSCFG_MSTPRI1_EDMA30TC1_SHIFT (0x0000000Cu)
+
+
+#define SYSCFG_MSTPRI1_EDMA30TC0 (0x00000700u)
+#define SYSCFG_MSTPRI1_EDMA30TC0_SHIFT (0x00000008u)
+
+
+#define SYSCFG_MSTPRI1_PRU1     (0x00000070u)
+#define SYSCFG_MSTPRI1_PRU1_SHIFT    (0x00000004u)
+
+
+#define SYSCFG_MSTPRI1_PRU0     (0x00000007u)
+#define SYSCFG_MSTPRI1_PRU0_SHIFT    (0x00000000u)
+
+
+/* MSTPRI2 */
+
+
+#define SYSCFG_MSTPRI2_LCDC     (0x70000000u)
+#define SYSCFG_MSTPRI2_LCDC_SHIFT    (0x0000001Cu)
+
+
+#define SYSCFG_MSTPRI2_USB1     (0x07000000u)
+#define SYSCFG_MSTPRI2_USB1_SHIFT    (0x00000018u)
+
+
+#define SYSCFG_MSTPRI2_UHPI     (0x00700000u)
+#define SYSCFG_MSTPRI2_UHPI_SHIFT    (0x00000014u)
+
+
+#define SYSCFG_MSTPRI2_USB0CDMA (0x00007000u)
+#define SYSCFG_MSTPRI2_USB0CDMA_SHIFT (0x0000000Cu)
+
+
+#define SYSCFG_MSTPRI2_USB0CFG  (0x00000700u)
+#define SYSCFG_MSTPRI2_USB0CFG_SHIFT (0x00000008u)
+
+
+#define SYSCFG_MSTPRI2_EMAC     (0x00000007u)
+#define SYSCFG_MSTPRI2_EMAC_SHIFT    (0x00000000u)
+
+
+/* PINMUX0 */
+
+#define SYSCFG_PINMUX0_PINMUX0_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX0_PINMUX0_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX0_31_28 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_31_28_RESERVED1 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_31_28_ALARM (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_31_28_UART2_CTS (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_31_28_GPIO0_8 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX0_PINMUX0_27_24_SHIFT (0x00000018u)
+/*----PINMUX0_27_24 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_27_24_AMUTE0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_27_24_PRU0_R30_16 (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_27_24_UART2_RTS (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_27_24_GPIO0_9 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX0_PINMUX0_23_20_SHIFT (0x00000014u)
+/*----PINMUX0_23_20 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_23_20_AHCLKX0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_23_20_USB_REFCLKIN (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_23_20_UART1_CTS (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_23_20_GPIO0_10 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX0_PINMUX0_19_16_SHIFT (0x00000010u)
+/*----PINMUX0_19_16 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_19_16_AHCLKR0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_19_16_PRU0_R30_18 (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_19_16_UART1_RTS (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_19_16_GPIO0_11 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX0_PINMUX0_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX0_15_12 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_15_12_AFSX0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_15_12_OBSERVE0_LOS (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_15_12_GPIO0_12 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX0_PINMUX0_11_8_SHIFT (0x00000008u)
+/*----PINMUX0_11_8 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_11_8_AFSR0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_11_8_OBSERVE0_SYNC (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_11_8_GPIO0_13 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX0_PINMUX0_7_4_SHIFT (0x00000004u)
+/*----PINMUX0_7_4 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_7_4_ACLKX0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_7_4_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_7_4_PRU0_R30_19 (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_7_4_GPIO0_14 (0x00000008u)
+
+#define SYSCFG_PINMUX0_PINMUX0_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX0_PINMUX0_3_0_SHIFT (0x00000000u)
+/*----PINMUX0_3_0 Tokens----*/
+#define SYSCFG_PINMUX0_PINMUX0_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX0_PINMUX0_3_0_ACLKR0 (0x00000001u)
+#define SYSCFG_PINMUX0_PINMUX0_3_0_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX0_PINMUX0_3_0_PRU0_R30_20 (0x00000004u)
+#define SYSCFG_PINMUX0_PINMUX0_3_0_GPIO0_15 (0x00000008u)
+
+
+/* PINMUX1 */
+
+#define SYSCFG_PINMUX1_PINMUX1_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX1_PINMUX1_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX1_31_28 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_31_28_AXR0_8 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_31_28_CLKS1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_31_28_ECAP1 (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_31_28_GPIO0_0 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX1_PINMUX1_27_24_SHIFT (0x00000018u)
+/*----PINMUX1_27_24 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_27_24_AXR0_9 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_27_24_DX1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_27_24_OBSERVE0_PHY_STATE2 (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_27_24_GPIO0_1 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX1_PINMUX1_23_20_SHIFT (0x00000014u)
+/*----PINMUX1_23_20 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_23_20_AXR0_10 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_23_20_DR1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_23_20_OBSERVE0_PHY_STATE1 (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_23_20_GPIO0_2 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX1_PINMUX1_19_16_SHIFT (0x00000010u)
+/*----PINMUX1_19_16 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_19_16_AXR0_11 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_19_16_FSX1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_19_16_OBSERVE0_PHY_STATE0 (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_19_16_GPIO0_3 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX1_PINMUX1_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX1_15_12 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_15_12_AXR0_12 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_15_12_FSR1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_15_12_OBSERVE0_PHY_READY (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_15_12_GPIO0_4 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX1_PINMUX1_11_8_SHIFT (0x00000008u)
+/*----PINMUX1_11_8 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_11_8_AXR0_13 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_11_8_CLKX1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_11_8_OBSERVE0_COMINIT (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_11_8_GPIO0_5 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX1_PINMUX1_7_4_SHIFT (0x00000004u)
+/*----PINMUX1_7_4 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_7_4_AXR0_14 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_7_4_CLKR1 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_7_4_OBSERVE0_COMWAKE (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_7_4_GPIO0_6 (0x00000008u)
+
+#define SYSCFG_PINMUX1_PINMUX1_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX1_PINMUX1_3_0_SHIFT (0x00000000u)
+/*----PINMUX1_3_0 Tokens----*/
+#define SYSCFG_PINMUX1_PINMUX1_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX1_PINMUX1_3_0_AXR0_15 (0x00000001u)
+#define SYSCFG_PINMUX1_PINMUX1_3_0_EPWM0TZ0 (0x00000002u)
+#define SYSCFG_PINMUX1_PINMUX1_3_0_ECAP2 (0x00000004u)
+#define SYSCFG_PINMUX1_PINMUX1_3_0_GPIO0_7 (0x00000008u)
+
+
+/* PINMUX2 */
+
+#define SYSCFG_PINMUX2_PINMUX2_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX2_PINMUX2_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX2_31_28 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_31_28_AXR0_0 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_31_28_ECAP0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_31_28_GPIO8_7 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_31_28_MII_TXD0 (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX2_PINMUX2_27_24_SHIFT (0x00000018u)
+/*----PINMUX2_27_24 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_27_24_AXR0_1 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_27_24_DX0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_27_24_GPIO1_9 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_27_24_MII_TXD1 (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX2_PINMUX2_23_20_SHIFT (0x00000014u)
+/*----PINMUX2_23_20 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_23_20_AXR0_2 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_23_20_DR0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_23_20_GPIO1_10 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_23_20_MII_TXD2 (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX2_PINMUX2_19_16_SHIFT (0x00000010u)
+/*----PINMUX2_19_16 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_19_16_AXR0_3 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_19_16_FSX0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_19_16_GPIO1_11 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_19_16_MII_TXD3 (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX2_PINMUX2_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX2_15_12 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_15_12_AXR0_4 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_15_12_FSR0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_15_12_GPIO1_12 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_15_12_MII_COL (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX2_PINMUX2_11_8_SHIFT (0x00000008u)
+/*----PINMUX2_11_8 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_11_8_AXR0_5 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_11_8_CLKX0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_11_8_GPIO1_13 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_11_8_MII_TXCLK (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX2_PINMUX2_7_4_SHIFT (0x00000004u)
+/*----PINMUX2_7_4 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_7_4_AXR0_6 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_7_4_CLKR0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_7_4_GPIO1_14 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_7_4_MII_TXEN (0x00000008u)
+
+#define SYSCFG_PINMUX2_PINMUX2_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX2_PINMUX2_3_0_SHIFT (0x00000000u)
+/*----PINMUX2_3_0 Tokens----*/
+#define SYSCFG_PINMUX2_PINMUX2_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX2_PINMUX2_3_0_AXR0_7 (0x00000001u)
+#define SYSCFG_PINMUX2_PINMUX2_3_0_EPWM1TZ0 (0x00000002u)
+#define SYSCFG_PINMUX2_PINMUX2_3_0_PRU0_R30_17 (0x00000004u)
+#define SYSCFG_PINMUX2_PINMUX2_3_0_GPIO1_15 (0x00000008u)
+
+
+/* PINMUX3 */
+
+#define SYSCFG_PINMUX3_PINMUX3_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX3_PINMUX3_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX3_31_28 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_31_28_NSPI0_SCS2 (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_31_28_UART0_RTS (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_31_28_GPIO8_1 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_31_28_MII_RXD0 (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX3_PINMUX3_27_24_SHIFT (0x00000018u)
+/*----PINMUX3_27_24 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_27_24_NSPI0_SCS3 (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_27_24_UART0_CTS (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_27_24_GPIO8_2 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_27_24_MII_RXD1 (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX3_PINMUX3_23_20_SHIFT (0x00000014u)
+/*----PINMUX3_23_20 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_23_20_NSPI0_SCS4 (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_23_20_UART0_TXD (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_23_20_GPIO8_3 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_23_20_MII_RXD2 (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX3_PINMUX3_19_16_SHIFT (0x00000010u)
+/*----PINMUX3_19_16 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_19_16_NSPI0_SCS5 (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_19_16_UART0_RXD (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_19_16_GPIO8_4 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_19_16_MII_RXD3 (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX3_PINMUX3_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX3_15_12 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_15_12_SPI0_SIMO0 (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_15_12_EPWMSYNCO (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_15_12_GPIO8_5 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_15_12_MII_CRS (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX3_PINMUX3_11_8_SHIFT (0x00000008u)
+/*----PINMUX3_11_8 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_11_8_SPI0_SOMI0 (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_11_8_EPWMSYNCI (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_11_8_GPIO8_6 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_11_8_MII_RXER (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX3_PINMUX3_7_4_SHIFT (0x00000004u)
+/*----PINMUX3_7_4 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_7_4_NSPI0_ENA (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_7_4_EPWM0B (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_7_4_PRU0_R30_6 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_7_4_MII_RXDV (0x00000008u)
+
+#define SYSCFG_PINMUX3_PINMUX3_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX3_PINMUX3_3_0_SHIFT (0x00000000u)
+/*----PINMUX3_3_0 Tokens----*/
+#define SYSCFG_PINMUX3_PINMUX3_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX3_PINMUX3_3_0_SPI0_CLK (0x00000001u)
+#define SYSCFG_PINMUX3_PINMUX3_3_0_EPWM0A (0x00000002u)
+#define SYSCFG_PINMUX3_PINMUX3_3_0_GPIO1_8 (0x00000004u)
+#define SYSCFG_PINMUX3_PINMUX3_3_0_MII_RXCLK (0x00000008u)
+
+
+/* PINMUX4 */
+
+#define SYSCFG_PINMUX4_PINMUX4_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX4_PINMUX4_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX4_31_28 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_31_28_NSPI1_SCS2 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_31_28_UART1_TXD (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_31_28_CP_POD (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_31_28_GPIO1_0 (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX4_PINMUX4_27_24_SHIFT (0x00000018u)
+/*----PINMUX4_27_24 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_27_24_NSPI1_SCS3 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_27_24_UART1_RXD (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_27_24_LED (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_27_24_GPIO1_1 (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX4_PINMUX4_23_20_SHIFT (0x00000014u)
+/*----PINMUX4_23_20 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_23_20_NSPI1_SCS4 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_23_20_UART2_TXD (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_23_20_I2C1_SDA (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_23_20_GPIO1_2 (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX4_PINMUX4_19_16_SHIFT (0x00000010u)
+/*----PINMUX4_19_16 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_19_16_NSPI1_SCS5 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_19_16_UART2_RXD (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_19_16_I2C1_SCL (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_19_16_GPIO1_3 (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX4_PINMUX4_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX4_15_12 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_15_12_NSPI1_SCS6 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_15_12_I2C0_SDA (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_15_12_TM64P3_OUT12 (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_15_12_GPIO1_4 (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX4_PINMUX4_11_8_SHIFT (0x00000008u)
+/*----PINMUX4_11_8 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_11_8_NSPI1_SCS7 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_11_8_I2C0_SCL (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_11_8_TM64P2_OUT12 (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_11_8_GPIO1_5 (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX4_PINMUX4_7_4_SHIFT (0x00000004u)
+/*----PINMUX4_7_4 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_7_4_NSPI0_SCS0 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_7_4_TM64P1_OUT12 (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_7_4_GPIO1_6 (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_7_4_MDIO_D (0x00000008u)
+
+#define SYSCFG_PINMUX4_PINMUX4_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX4_PINMUX4_3_0_SHIFT (0x00000000u)
+/*----PINMUX4_3_0 Tokens----*/
+#define SYSCFG_PINMUX4_PINMUX4_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX4_PINMUX4_3_0_NSPI0_SCS1 (0x00000001u)
+#define SYSCFG_PINMUX4_PINMUX4_3_0_TM64P0_OUT12 (0x00000002u)
+#define SYSCFG_PINMUX4_PINMUX4_3_0_GPIO1_7 (0x00000004u)
+#define SYSCFG_PINMUX4_PINMUX4_3_0_MDIO_CLK (0x00000008u)
+
+
+/* PINMUX5 */
+
+#define SYSCFG_PINMUX5_PINMUX5_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX5_PINMUX5_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX5_31_28 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_31_28_EMA_BA0 (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_31_28_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_31_28_GPIO2_8 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX5_PINMUX5_27_24_SHIFT (0x00000018u)
+/*----PINMUX5_27_24 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_27_24_EMA_BA1 (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_27_24_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_27_24_GPIO2_9 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX5_PINMUX5_23_20_SHIFT (0x00000014u)
+/*----PINMUX5_23_20 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_23_20_SPI1_SIMO0 (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_23_20_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_23_20_GPIO2_10 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX5_PINMUX5_19_16_SHIFT (0x00000010u)
+/*----PINMUX5_19_16 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_19_16_SPI1_SOMI0 (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_19_16_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_19_16_GPIO2_11 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX5_PINMUX5_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX5_15_12 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_15_12_NSPI1_ENA (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_15_12_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_15_12_GPIO2_12 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX5_PINMUX5_11_8_SHIFT (0x00000008u)
+/*----PINMUX5_11_8 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_11_8_SPI1_CLK (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_11_8_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_11_8_GPIO2_13 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX5_PINMUX5_7_4_SHIFT (0x00000004u)
+/*----PINMUX5_7_4 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_7_4_NSPI1_SCS0 (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_7_4_EPWM1B (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_7_4_PRU0_R30_7 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_7_4_GPIO2_14 (0x00000008u)
+
+#define SYSCFG_PINMUX5_PINMUX5_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX5_PINMUX5_3_0_SHIFT (0x00000000u)
+/*----PINMUX5_3_0 Tokens----*/
+#define SYSCFG_PINMUX5_PINMUX5_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX5_PINMUX5_3_0_NSPI1_SCS1 (0x00000001u)
+#define SYSCFG_PINMUX5_PINMUX5_3_0_EPWM1A (0x00000002u)
+#define SYSCFG_PINMUX5_PINMUX5_3_0_PRU0_R30_8 (0x00000004u)
+#define SYSCFG_PINMUX5_PINMUX5_3_0_GPIO2_15 (0x00000008u)
+
+
+/* PINMUX6 */
+
+#define SYSCFG_PINMUX6_PINMUX6_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX6_PINMUX6_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX6_31_28 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_31_28_NEMA_CS0 (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_31_28_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_31_28_GPIO2_0 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX6_PINMUX6_27_24_SHIFT (0x00000018u)
+/*----PINMUX6_27_24 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_27_24_EMA_WAIT1 (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_27_24_PRU0_R30_1 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_27_24_GPIO2_1 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX6_PINMUX6_23_20_SHIFT (0x00000014u)
+/*----PINMUX6_23_20 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_23_20_NEMA_WE_DQM1 (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_23_20_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_23_20_GPIO2_2 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX6_PINMUX6_19_16_SHIFT (0x00000010u)
+/*----PINMUX6_19_16 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_19_16_NEMA_WE_DQM0 (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_19_16_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_19_16_GPIO2_3 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX6_PINMUX6_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX6_15_12 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_15_12_NEMA_CAS (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_15_12_PRU0_R30_2 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_15_12_GPIO2_4 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX6_PINMUX6_11_8_SHIFT (0x00000008u)
+/*----PINMUX6_11_8 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_11_8_NEMA_RAS (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_11_8_PRU0_R30_3 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_11_8_GPIO2_5 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX6_PINMUX6_7_4_SHIFT (0x00000004u)
+/*----PINMUX6_7_4 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_7_4_EMA_SDCKE (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_7_4_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_7_4_PRU0_R30_4 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_7_4_GPIO2_6 (0x00000008u)
+
+#define SYSCFG_PINMUX6_PINMUX6_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX6_PINMUX6_3_0_SHIFT (0x00000000u)
+/*----PINMUX6_3_0 Tokens----*/
+#define SYSCFG_PINMUX6_PINMUX6_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX6_PINMUX6_3_0_EMA_CLK (0x00000001u)
+#define SYSCFG_PINMUX6_PINMUX6_3_0_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX6_PINMUX6_3_0_PRU0_R30_5 (0x00000004u)
+#define SYSCFG_PINMUX6_PINMUX6_3_0_GPIO2_7 (0x00000008u)
+
+
+/* PINMUX7 */
+
+#define SYSCFG_PINMUX7_PINMUX7_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX7_PINMUX7_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX7_31_28 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_31_28_EMA_WAIT0 (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_31_28_PRU0_R30_0 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_31_28_GPIO3_8 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX7_PINMUX7_27_24_SHIFT (0x00000018u)
+/*----PINMUX7_27_24 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_27_24_NEMA_RNW (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_27_24_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_27_24_GPIO3_9 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX7_PINMUX7_23_20_SHIFT (0x00000014u)
+/*----PINMUX7_23_20 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_23_20_NEMA_OE (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_23_20_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_23_20_GPIO3_10 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX7_PINMUX7_19_16_SHIFT (0x00000010u)
+/*----PINMUX7_19_16 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_19_16_NEMA_WE (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_19_16_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_19_16_GPIO3_11 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX7_PINMUX7_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX7_15_12 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_15_12_NEMA_CS5 (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_15_12_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_15_12_GPIO3_12 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX7_PINMUX7_11_8_SHIFT (0x00000008u)
+/*----PINMUX7_11_8 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_11_8_NEMA_CS4 (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_11_8_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_11_8_GPIO3_13 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX7_PINMUX7_7_4_SHIFT (0x00000004u)
+/*----PINMUX7_7_4 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_7_4_NEMA_CS3 (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_7_4_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_7_4_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_7_4_GPIO3_14 (0x00000008u)
+
+#define SYSCFG_PINMUX7_PINMUX7_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX7_PINMUX7_3_0_SHIFT (0x00000000u)
+/*----PINMUX7_3_0 Tokens----*/
+#define SYSCFG_PINMUX7_PINMUX7_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX7_PINMUX7_3_0_NEMA_CS2 (0x00000001u)
+#define SYSCFG_PINMUX7_PINMUX7_3_0_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX7_PINMUX7_3_0_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX7_PINMUX7_3_0_GPIO3_15 (0x00000008u)
+
+
+/* PINMUX8 */
+
+#define SYSCFG_PINMUX8_PINMUX8_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX8_PINMUX8_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX8_31_28 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_31_28_EMA_D8 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_31_28_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_31_28_GPIO3_0 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX8_PINMUX8_27_24_SHIFT (0x00000018u)
+/*----PINMUX8_27_24 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_27_24_EMA_D9 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_27_24_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_27_24_GPIO3_1 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX8_PINMUX8_23_20_SHIFT (0x00000014u)
+/*----PINMUX8_23_20 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_23_20_EMA_D10 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_23_20_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_23_20_GPIO3_2 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX8_PINMUX8_19_16_SHIFT (0x00000010u)
+/*----PINMUX8_19_16 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_19_16_EMA_D11 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_19_16_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_19_16_GPIO3_3 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX8_PINMUX8_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX8_15_12 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_15_12_EMA_D12 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_15_12_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_15_12_GPIO3_4 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX8_PINMUX8_11_8_SHIFT (0x00000008u)
+/*----PINMUX8_11_8 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_11_8_EMA_D13 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_11_8_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_11_8_GPIO3_5 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX8_PINMUX8_7_4_SHIFT (0x00000004u)
+/*----PINMUX8_7_4 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_7_4_EMA_D14 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_7_4_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_7_4_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_7_4_GPIO3_6 (0x00000008u)
+
+#define SYSCFG_PINMUX8_PINMUX8_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX8_PINMUX8_3_0_SHIFT (0x00000000u)
+/*----PINMUX8_3_0 Tokens----*/
+#define SYSCFG_PINMUX8_PINMUX8_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX8_PINMUX8_3_0_EMA_D15 (0x00000001u)
+#define SYSCFG_PINMUX8_PINMUX8_3_0_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX8_PINMUX8_3_0_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX8_PINMUX8_3_0_GPIO3_7 (0x00000008u)
+
+
+/* PINMUX9 */
+
+#define SYSCFG_PINMUX9_PINMUX9_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX9_PINMUX9_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX9_31_28 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_31_28_EMA_D0 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_31_28_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_31_28_GPIO4_8 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX9_PINMUX9_27_24_SHIFT (0x00000018u)
+/*----PINMUX9_27_24 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_27_24_EMA_D1 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_27_24_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_27_24_GPIO4_9 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX9_PINMUX9_23_20_SHIFT (0x00000014u)
+/*----PINMUX9_23_20 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_23_20_EMA_D2 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_23_20_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_23_20_GPIO4_10 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX9_PINMUX9_19_16_SHIFT (0x00000010u)
+/*----PINMUX9_19_16 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_19_16_EMA_D3 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_19_16_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_19_16_GPIO4_11 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX9_PINMUX9_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX9_15_12 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_15_12_EMA_D4 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_15_12_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_15_12_GPIO4_12 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX9_PINMUX9_11_8_SHIFT (0x00000008u)
+/*----PINMUX9_11_8 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_11_8_EMA_D5 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_11_8_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_11_8_GPIO4_13 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX9_PINMUX9_7_4_SHIFT (0x00000004u)
+/*----PINMUX9_7_4 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_7_4_EMA_D6 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_7_4_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_7_4_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_7_4_GPIO4_14 (0x00000008u)
+
+#define SYSCFG_PINMUX9_PINMUX9_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX9_PINMUX9_3_0_SHIFT (0x00000000u)
+/*----PINMUX9_3_0 Tokens----*/
+#define SYSCFG_PINMUX9_PINMUX9_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX9_PINMUX9_3_0_EMA_D7 (0x00000001u)
+#define SYSCFG_PINMUX9_PINMUX9_3_0_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX9_PINMUX9_3_0_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX9_PINMUX9_3_0_GPIO4_15 (0x00000008u)
+
+
+/* PINMUX10 */
+
+#define SYSCFG_PINMUX10_PINMUX10_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX10_PINMUX10_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX10_31_28 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_31_28_EMA_A16 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_31_28_MMCSD0_DAT5 (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_31_28_PRU1_R30_24 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_31_28_GPIO4_0 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX10_PINMUX10_27_24_SHIFT (0x00000018u)
+/*----PINMUX10_27_24 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_27_24_EMA_A17 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_27_24_MMCSD0_DAT4 (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_27_24_PRU1_R30_25 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_27_24_GPIO4_1 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX10_PINMUX10_23_20_SHIFT (0x00000014u)
+/*----PINMUX10_23_20 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_23_20_EMA_A18 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_23_20_MMCSD0_DAT3 (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_23_20_PRU1_R30_26 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_23_20_GPIO4_2 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX10_PINMUX10_19_16_SHIFT (0x00000010u)
+/*----PINMUX10_19_16 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_19_16_EMA_A19 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_19_16_MMCSD0_DAT2 (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_19_16_PRU1_R30_27 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_19_16_GPIO4_3 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX10_PINMUX10_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX10_15_12 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_15_12_EMA_A20 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_15_12_MMCSD0_DAT1 (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_15_12_PRU1_R30_28 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_15_12_GPIO4_4 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX10_PINMUX10_11_8_SHIFT (0x00000008u)
+/*----PINMUX10_11_8 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_11_8_EMA_A21 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_11_8_MMCSD0_DAT0 (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_11_8_PRU1_R30_29 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_11_8_GPIO4_5 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX10_PINMUX10_7_4_SHIFT (0x00000004u)
+/*----PINMUX10_7_4 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_7_4_EMA_A22 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_7_4_MMCSD0_CMD (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_7_4_PRU1_R30_30 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_7_4_GPIO4_6 (0x00000008u)
+
+#define SYSCFG_PINMUX10_PINMUX10_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX10_PINMUX10_3_0_SHIFT (0x00000000u)
+/*----PINMUX10_3_0 Tokens----*/
+#define SYSCFG_PINMUX10_PINMUX10_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX10_PINMUX10_3_0_EMA_A23 (0x00000001u)
+#define SYSCFG_PINMUX10_PINMUX10_3_0_MMCSD0_CLK (0x00000002u)
+#define SYSCFG_PINMUX10_PINMUX10_3_0_PRU1_R30_31 (0x00000004u)
+#define SYSCFG_PINMUX10_PINMUX10_3_0_GPIO4_7 (0x00000008u)
+
+
+/* PINMUX11 */
+
+#define SYSCFG_PINMUX11_PINMUX11_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX11_PINMUX11_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX11_31_28 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_31_28_EMA_A8 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_31_28_PRU1_R30_16 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_31_28_GPIO5_8 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX11_PINMUX11_27_24_SHIFT (0x00000018u)
+/*----PINMUX11_27_24 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_27_24_EMA_A9 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_27_24_PRU1_R30_17 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_27_24_GPIO5_9 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX11_PINMUX11_23_20_SHIFT (0x00000014u)
+/*----PINMUX11_23_20 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_23_20_EMA_A10 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_23_20_PRU1_R30_18 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_23_20_GPIO5_10 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX11_PINMUX11_19_16_SHIFT (0x00000010u)
+/*----PINMUX11_19_16 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_19_16_EMA_A11 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_19_16_PRU1_R30_19 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_19_16_GPIO5_11 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX11_PINMUX11_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX11_15_12 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_15_12_EMA_A12 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_15_12_PRU1_R30_20 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_15_12_GPIO5_12 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX11_PINMUX11_11_8_SHIFT (0x00000008u)
+/*----PINMUX11_11_8 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_11_8_EMA_A13 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_11_8_PRU0_R30_21 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_11_8_PRU1_R30_21 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_11_8_GPIO5_13 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX11_PINMUX11_7_4_SHIFT (0x00000004u)
+/*----PINMUX11_7_4 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_7_4_EMA_A14 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_7_4_MMCSD0_DAT7 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_7_4_PRU1_R30_22 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_7_4_GPIO5_14 (0x00000008u)
+
+#define SYSCFG_PINMUX11_PINMUX11_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX11_PINMUX11_3_0_SHIFT (0x00000000u)
+/*----PINMUX11_3_0 Tokens----*/
+#define SYSCFG_PINMUX11_PINMUX11_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX11_PINMUX11_3_0_EMA_A15 (0x00000001u)
+#define SYSCFG_PINMUX11_PINMUX11_3_0_MMCSD0_DAT6 (0x00000002u)
+#define SYSCFG_PINMUX11_PINMUX11_3_0_PRU1_R30_23 (0x00000004u)
+#define SYSCFG_PINMUX11_PINMUX11_3_0_GPIO5_15 (0x00000008u)
+
+
+/* PINMUX12 */
+
+#define SYSCFG_PINMUX12_PINMUX12_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX12_PINMUX12_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX12_31_28 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_31_28_EMA_A0 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_31_28_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_31_28_GPIO5_0 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX12_PINMUX12_27_24_SHIFT (0x00000018u)
+/*----PINMUX12_27_24 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_27_24_EMA_A1 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_27_24_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_27_24_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_27_24_GPIO5_1 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX12_PINMUX12_23_20_SHIFT (0x00000014u)
+/*----PINMUX12_23_20 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_23_20_EMA_A2 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_23_20_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_23_20_GPIO5_2 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX12_PINMUX12_19_16_SHIFT (0x00000010u)
+/*----PINMUX12_19_16 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_19_16_EMA_A3 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_19_16_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_19_16_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_19_16_GPIO5_3 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX12_PINMUX12_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX12_15_12 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_15_12_EMA_A4 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_15_12_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_15_12_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_15_12_GPIO5_4 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX12_PINMUX12_11_8_SHIFT (0x00000008u)
+/*----PINMUX12_11_8 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_11_8_EMA_A5 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_11_8_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_11_8_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_11_8_GPIO5_5 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX12_PINMUX12_7_4_SHIFT (0x00000004u)
+/*----PINMUX12_7_4 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_7_4_EMA_A6 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_7_4_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_7_4_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_7_4_GPIO5_6 (0x00000008u)
+
+#define SYSCFG_PINMUX12_PINMUX12_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX12_PINMUX12_3_0_SHIFT (0x00000000u)
+/*----PINMUX12_3_0 Tokens----*/
+#define SYSCFG_PINMUX12_PINMUX12_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX12_PINMUX12_3_0_EMA_A7 (0x00000001u)
+#define SYSCFG_PINMUX12_PINMUX12_3_0_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX12_PINMUX12_3_0_PRU1_R30_15 (0x00000004u)
+#define SYSCFG_PINMUX12_PINMUX12_3_0_GPIO5_7 (0x00000008u)
+
+
+/* PINMUX13 */
+
+#define SYSCFG_PINMUX13_PINMUX13_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX13_PINMUX13_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX13_31_28 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_31_28_PRU0_R30_26 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_31_28_UHPI_HRNW (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_31_28_CH1_WAIT (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_31_28_GPIO6_8 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX13_PINMUX13_27_24_SHIFT (0x00000018u)
+/*----PINMUX13_27_24 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_27_24_PRU0_R30_27 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_27_24_UHPI_HHWIL (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_27_24_GPIO6_9 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX13_PINMUX13_23_20_SHIFT (0x00000014u)
+/*----PINMUX13_23_20 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_23_20_PRU0_R30_28 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_23_20_UHPI_HCNTL1 (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_23_20_CH1_START (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_23_20_GPIO6_10 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX13_PINMUX13_19_16_SHIFT (0x00000010u)
+/*----PINMUX13_19_16 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_19_16_PRU0_R30_29 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_19_16_UHPI_HCNTL0 (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_19_16_CH1_CLK (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_19_16_GPIO6_11 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX13_PINMUX13_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX13_15_12 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_15_12_PRU0_R30_30 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_15_12_NUHPI_HINT (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_15_12_PRU1_R30_11 (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_15_12_GPIO6_12 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX13_PINMUX13_11_8_SHIFT (0x00000008u)
+/*----PINMUX13_11_8 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_11_8_PRU0_R30_31 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_11_8_NUHPI_HRDY (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_11_8_PRU1_R30_12 (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_11_8_GPIO6_13 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX13_PINMUX13_7_4_SHIFT (0x00000004u)
+/*----PINMUX13_7_4 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_7_4_OBSCLK0 (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_7_4_NUHPI_HDS2 (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_7_4_PRU1_R30_13 (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_7_4_GPIO6_14 (0x00000008u)
+
+#define SYSCFG_PINMUX13_PINMUX13_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX13_PINMUX13_3_0_SHIFT (0x00000000u)
+/*----PINMUX13_3_0 Tokens----*/
+#define SYSCFG_PINMUX13_PINMUX13_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX13_PINMUX13_3_0_NRESETOUT (0x00000001u)
+#define SYSCFG_PINMUX13_PINMUX13_3_0_NUHPI_HAS (0x00000002u)
+#define SYSCFG_PINMUX13_PINMUX13_3_0_PRU1_R30_14 (0x00000004u)
+#define SYSCFG_PINMUX13_PINMUX13_3_0_GPIO6_15 (0x00000008u)
+
+
+/* PINMUX14 */
+
+#define SYSCFG_PINMUX14_PINMUX14_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX14_PINMUX14_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX14_31_28 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_31_28_DIN2 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_31_28_UHPI_HD10 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_31_28_UPP_D10 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_31_28_RMII_RXER (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX14_PINMUX14_27_24_SHIFT (0x00000018u)
+/*----PINMUX14_27_24 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_27_24_DIN3 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_27_24_UHPI_HD11 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_27_24_UPP_D11 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_27_24_RMII_RXD0 (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX14_PINMUX14_23_20_SHIFT (0x00000014u)
+/*----PINMUX14_23_20 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_23_20_DIN4 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_23_20_UHPI_HD12 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_23_20_UPP_D12 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_23_20_RMII_RXD1 (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX14_PINMUX14_19_16_SHIFT (0x00000010u)
+/*----PINMUX14_19_16 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_19_16_DIN5 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_19_16_UHPI_HD13 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_19_16_UPP_D13 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_19_16_RMII_TXEN (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX14_PINMUX14_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX14_15_12 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_15_12_DIN6 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_15_12_UHPI_HD14 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_15_12_UPP_D14 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_15_12_RMII_TXD0 (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX14_PINMUX14_11_8_SHIFT (0x00000008u)
+/*----PINMUX14_11_8 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_11_8_DIN7 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_11_8_UHPI_HD15 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_11_8_UPP_D15 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_11_8_RMII_TXD1 (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX14_PINMUX14_7_4_SHIFT (0x00000004u)
+/*----PINMUX14_7_4 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_7_4_CLKIN1 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_7_4_NUHPI_HDS1 (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_7_4_PRU1_R30_9 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_7_4_GPIO6_6 (0x00000008u)
+
+#define SYSCFG_PINMUX14_PINMUX14_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX14_PINMUX14_3_0_SHIFT (0x00000000u)
+/*----PINMUX14_3_0 Tokens----*/
+#define SYSCFG_PINMUX14_PINMUX14_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX14_PINMUX14_3_0_CLKIN0 (0x00000001u)
+#define SYSCFG_PINMUX14_PINMUX14_3_0_NUHPI_HCS (0x00000002u)
+#define SYSCFG_PINMUX14_PINMUX14_3_0_PRU1_R30_10 (0x00000004u)
+#define SYSCFG_PINMUX14_PINMUX14_3_0_GPIO6_7 (0x00000008u)
+
+
+/* PINMUX15 */
+
+#define SYSCFG_PINMUX15_PINMUX15_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX15_PINMUX15_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX15_31_28 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_31_28_DIN10 (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_31_28_UHPI_HD2 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_31_28_UPP_D2 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_31_28_PRU0_R30_10 (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX15_PINMUX15_27_24_SHIFT (0x00000018u)
+/*----PINMUX15_27_24 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_27_24_DIN11 (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_27_24_UHPI_HD3 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_27_24_UPP_D3 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_27_24_PRU0_R30_11 (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX15_PINMUX15_23_20_SHIFT (0x00000014u)
+/*----PINMUX15_23_20 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_23_20_DIN12 (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_23_20_UHPI_HD4 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_23_20_UPP_D4 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_23_20_PRU0_R30_12 (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX15_PINMUX15_19_16_SHIFT (0x00000010u)
+/*----PINMUX15_19_16 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_19_16_DIN13_FIELD (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_19_16_UHPI_HD5 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_19_16_UPP_D5 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_19_16_PRU0_R30_13 (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX15_PINMUX15_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX15_15_12 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_15_12_DIN14_HSYNC (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_15_12_UHPI_HD6 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_15_12_UPP_D6 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_15_12_PRU0_R30_14 (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX15_PINMUX15_11_8_SHIFT (0x00000008u)
+/*----PINMUX15_11_8 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_11_8_DIN15_VSYNC (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_11_8_UHPI_HD7 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_11_8_UPP_D7 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_11_8_PRU0_R30_15 (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX15_PINMUX15_7_4_SHIFT (0x00000004u)
+/*----PINMUX15_7_4 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_7_4_DIN0 (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_7_4_UHPI_HD8 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_7_4_UPP_D8 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_7_4_RMII_CRS_DV (0x00000008u)
+
+#define SYSCFG_PINMUX15_PINMUX15_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX15_PINMUX15_3_0_SHIFT (0x00000000u)
+/*----PINMUX15_3_0 Tokens----*/
+#define SYSCFG_PINMUX15_PINMUX15_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX15_PINMUX15_3_0_DIN1 (0x00000001u)
+#define SYSCFG_PINMUX15_PINMUX15_3_0_UHPI_HD9 (0x00000002u)
+#define SYSCFG_PINMUX15_PINMUX15_3_0_UPP_D9 (0x00000004u)
+#define SYSCFG_PINMUX15_PINMUX15_3_0_RMII_MHZ_50_CLK (0x00000008u)
+
+
+/* PINMUX16 */
+
+#define SYSCFG_PINMUX16_PINMUX16_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX16_PINMUX16_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX16_31_28 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_31_28_DOUT2 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_31_28_LCD_D2 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_31_28_UPP_XD10 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_31_28_GPIO7_10 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX16_PINMUX16_27_24_SHIFT (0x00000018u)
+/*----PINMUX16_27_24 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_27_24_DOUT3 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_27_24_LCD_D3 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_27_24_UPP_XD11 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_27_24_GPIO7_11 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX16_PINMUX16_23_20_SHIFT (0x00000014u)
+/*----PINMUX16_23_20 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_23_20_DOUT4 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_23_20_LCD_D4 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_23_20_UPP_XD12 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_23_20_GPIO7_12 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX16_PINMUX16_19_16_SHIFT (0x00000010u)
+/*----PINMUX16_19_16 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_19_16_DOUT5 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_19_16_LCD_D5 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_19_16_UPP_XD13 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_19_16_GPIO7_13 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX16_PINMUX16_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX16_15_12 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_15_12_DOUT6 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_15_12_LCD_D6 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_15_12_UPP_XD14 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_15_12_GPIO7_14 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX16_PINMUX16_11_8_SHIFT (0x00000008u)
+/*----PINMUX16_11_8 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_11_8_DOUT7 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_11_8_LCD_D7 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_11_8_UPP_XD15 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_11_8_GPIO7_15 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX16_PINMUX16_7_4_SHIFT (0x00000004u)
+/*----PINMUX16_7_4 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_7_4_DIN8 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_7_4_UHPI_HD0 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_7_4_UPP_D0 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_7_4_GPIO6_5 (0x00000008u)
+
+#define SYSCFG_PINMUX16_PINMUX16_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX16_PINMUX16_3_0_SHIFT (0x00000000u)
+/*----PINMUX16_3_0 Tokens----*/
+#define SYSCFG_PINMUX16_PINMUX16_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX16_PINMUX16_3_0_DIN9 (0x00000001u)
+#define SYSCFG_PINMUX16_PINMUX16_3_0_UHPI_HD1 (0x00000002u)
+#define SYSCFG_PINMUX16_PINMUX16_3_0_UPP_D1 (0x00000004u)
+#define SYSCFG_PINMUX16_PINMUX16_3_0_PRU0_R30_9 (0x00000008u)
+
+
+/* PINMUX17 */
+
+#define SYSCFG_PINMUX17_PINMUX17_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX17_PINMUX17_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX17_31_28 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_31_28_DOUT10 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_31_28_LCD_D10 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_31_28_UPP_XD2 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_31_28_GPIO7_2 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX17_PINMUX17_27_24_SHIFT (0x00000018u)
+/*----PINMUX17_27_24 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_27_24_DOUT11 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_27_24_LCD_D11 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_27_24_UPP_XD3 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_27_24_GPIO7_3 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX17_PINMUX17_23_20_SHIFT (0x00000014u)
+/*----PINMUX17_23_20 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_23_20_DOUT12 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_23_20_LCD_D12 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_23_20_UPP_XD4 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_23_20_GPIO7_4 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX17_PINMUX17_19_16_SHIFT (0x00000010u)
+/*----PINMUX17_19_16 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_19_16_DOUT13 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_19_16_LCD_D13 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_19_16_UPP_XD5 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_19_16_GPIO7_5 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX17_PINMUX17_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX17_15_12 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_15_12_DOUT14 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_15_12_LCD_D14 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_15_12_UPP_XD6 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_15_12_GPIO7_6 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX17_PINMUX17_11_8_SHIFT (0x00000008u)
+/*----PINMUX17_11_8 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_11_8_DOUT15 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_11_8_LCD_D15 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_11_8_UPP_XD7 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_11_8_GPIO7_7 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX17_PINMUX17_7_4_SHIFT (0x00000004u)
+/*----PINMUX17_7_4 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_7_4_DOUT0 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_7_4_LCD_D0 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_7_4_UPP_XD8 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_7_4_GPIO7_8 (0x00000008u)
+
+#define SYSCFG_PINMUX17_PINMUX17_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX17_PINMUX17_3_0_SHIFT (0x00000000u)
+/*----PINMUX17_3_0 Tokens----*/
+#define SYSCFG_PINMUX17_PINMUX17_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX17_PINMUX17_3_0_DOUT1 (0x00000001u)
+#define SYSCFG_PINMUX17_PINMUX17_3_0_LCD_D1 (0x00000002u)
+#define SYSCFG_PINMUX17_PINMUX17_3_0_UPP_XD9 (0x00000004u)
+#define SYSCFG_PINMUX17_PINMUX17_3_0_GPIO7_9 (0x00000008u)
+
+
+/* PINMUX18 */
+
+#define SYSCFG_PINMUX18_PINMUX18_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX18_PINMUX18_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX18_31_28 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_31_28_MMCSD1_DAT6 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_31_28_LCD_MCLK (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_31_28_PRU1_R30_6 (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_31_28_GPIO8_10 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX18_PINMUX18_27_24_SHIFT (0x00000018u)
+/*----PINMUX18_27_24 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_27_24_MMCSD1_DAT7 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_27_24_LCD_PCLK (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_27_24_PRU1_R30_7 (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_27_24_GPIO8_11 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX18_PINMUX18_23_20_SHIFT (0x00000014u)
+/*----PINMUX18_23_20 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_23_20_PRU0_R30_22 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_23_20_PRU1_R30_8 (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_23_20_CH0_WAIT (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_23_20_GPIO8_12 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX18_PINMUX18_19_16_SHIFT (0x00000010u)
+/*----PINMUX18_19_16 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_19_16_PRU0_R30_23 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_19_16_MMCSD1_CMD (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_19_16_GPIO8_13 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX18_PINMUX18_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX18_15_12 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_15_12_PRU0_R30_24 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_15_12_MMCSD1_CLK (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_15_12_CH0_START (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_15_12_GPIO8_14 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX18_PINMUX18_11_8_SHIFT (0x00000008u)
+/*----PINMUX18_11_8 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_11_8_PRU0_R30_25 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_11_8_MMCSD1_DAT0 (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_11_8_CH0_CLK (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_11_8_GPIO8_15 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX18_PINMUX18_7_4_SHIFT (0x00000004u)
+/*----PINMUX18_7_4 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_7_4_DOUT8 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_7_4_LCD_D8 (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_7_4_UPP_XD0 (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_7_4_GPIO7_0 (0x00000008u)
+
+#define SYSCFG_PINMUX18_PINMUX18_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX18_PINMUX18_3_0_SHIFT (0x00000000u)
+/*----PINMUX18_3_0 Tokens----*/
+#define SYSCFG_PINMUX18_PINMUX18_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX18_PINMUX18_3_0_DOUT9 (0x00000001u)
+#define SYSCFG_PINMUX18_PINMUX18_3_0_LCD_D9 (0x00000002u)
+#define SYSCFG_PINMUX18_PINMUX18_3_0_UPP_XD1 (0x00000004u)
+#define SYSCFG_PINMUX18_PINMUX18_3_0_GPIO7_1 (0x00000008u)
+
+
+/* PINMUX19 */
+
+#define SYSCFG_PINMUX19_PINMUX19_31_28 (0xF0000000u)
+#define SYSCFG_PINMUX19_PINMUX19_31_28_SHIFT (0x0000001Cu)
+/*----PINMUX19_31_28 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_31_28_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_31_28_RTCK (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_31_28_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_31_28_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_31_28_GPIO8_0 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_27_24 (0x0F000000u)
+#define SYSCFG_PINMUX19_PINMUX19_27_24_SHIFT (0x00000018u)
+/*----PINMUX19_27_24 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_27_24_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_27_24_RESERVED1 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_27_24_NLCD_AC_ENB_CS (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_27_24_RESERVED4 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_27_24_GPIO6_0 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_23_20 (0x00F00000u)
+#define SYSCFG_PINMUX19_PINMUX19_23_20_SHIFT (0x00000014u)
+/*----PINMUX19_23_20 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_23_20_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_23_20_CLKO3 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_23_20_RESERVED2 (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_23_20_PRU1_R30_0 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_23_20_GPIO6_1 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_19_16 (0x000F0000u)
+#define SYSCFG_PINMUX19_PINMUX19_19_16_SHIFT (0x00000010u)
+/*----PINMUX19_19_16 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_19_16_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_19_16_CLKIN3 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_19_16_MMCSD1_DAT1 (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_19_16_PRU1_R30_1 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_19_16_GPIO6_2 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_15_12 (0x0000F000u)
+#define SYSCFG_PINMUX19_PINMUX19_15_12_SHIFT (0x0000000Cu)
+/*----PINMUX19_15_12 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_15_12_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_15_12_CLKO2 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_15_12_MMCSD1_DAT2 (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_15_12_PRU1_R30_2 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_15_12_GPIO6_3 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_11_8 (0x00000F00u)
+#define SYSCFG_PINMUX19_PINMUX19_11_8_SHIFT (0x00000008u)
+/*----PINMUX19_11_8 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_11_8_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_11_8_CLKIN2 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_11_8_MMCSD1_DAT3 (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_11_8_PRU1_R30_3 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_11_8_GPIO6_4 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_7_4 (0x000000F0u)
+#define SYSCFG_PINMUX19_PINMUX19_7_4_SHIFT (0x00000004u)
+/*----PINMUX19_7_4 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_7_4_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_7_4_MMCSD1_DAT4 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_7_4_LCD_VSYNC (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_7_4_PRU1_R30_4 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_7_4_GPIO8_8 (0x00000008u)
+
+#define SYSCFG_PINMUX19_PINMUX19_3_0 (0x0000000Fu)
+#define SYSCFG_PINMUX19_PINMUX19_3_0_SHIFT (0x00000000u)
+/*----PINMUX19_3_0 Tokens----*/
+#define SYSCFG_PINMUX19_PINMUX19_3_0_DEFAULT (0x00000000u)
+#define SYSCFG_PINMUX19_PINMUX19_3_0_MMCSD1_DAT5 (0x00000001u)
+#define SYSCFG_PINMUX19_PINMUX19_3_0_LCD_HSYNC (0x00000002u)
+#define SYSCFG_PINMUX19_PINMUX19_3_0_PRU1_R30_5 (0x00000004u)
+#define SYSCFG_PINMUX19_PINMUX19_3_0_GPIO8_9 (0x00000008u)
+
+
+/* SUSPSRC */
+
+
+#define SYSCFG_SUSPSRC_TIMER64P_2SRC (0x20000000u)
+#define SYSCFG_SUSPSRC_TIMER64P_2SRC_SHIFT (0x0000001Du)
+
+#define SYSCFG_SUSPSRC_TIMER64P_1SRC (0x10000000u)
+#define SYSCFG_SUSPSRC_TIMER64P_1SRC_SHIFT (0x0000001Cu)
+
+#define SYSCFG_SUSPSRC_TIMER64P_0SRC (0x08000000u)
+#define SYSCFG_SUSPSRC_TIMER64P_0SRC_SHIFT (0x0000001Bu)
+
+
+#define SYSCFG_SUSPSRC_EPWM1SRC (0x01000000u)
+#define SYSCFG_SUSPSRC_EPWM1SRC_SHIFT (0x00000018u)
+
+#define SYSCFG_SUSPSRC_EPWM0SRC (0x00800000u)
+#define SYSCFG_SUSPSRC_EPWM0SRC_SHIFT (0x00000017u)
+
+#define SYSCFG_SUSPSRC_SPI1SRC  (0x00400000u)
+#define SYSCFG_SUSPSRC_SPI1SRC_SHIFT (0x00000016u)
+
+#define SYSCFG_SUSPSRC_SPI0SRC  (0x00200000u)
+#define SYSCFG_SUSPSRC_SPI0SRC_SHIFT (0x00000015u)
+
+#define SYSCFG_SUSPSRC_UART2SRC (0x00100000u)
+#define SYSCFG_SUSPSRC_UART2SRC_SHIFT (0x00000014u)
+
+#define SYSCFG_SUSPSRC_UART1SRC (0x00080000u)
+#define SYSCFG_SUSPSRC_UART1SRC_SHIFT (0x00000013u)
+
+#define SYSCFG_SUSPSRC_UART0SRC (0x00040000u)
+#define SYSCFG_SUSPSRC_UART0SRC_SHIFT (0x00000012u)
+
+#define SYSCFG_SUSPSRC_I2C1SRC  (0x00020000u)
+#define SYSCFG_SUSPSRC_I2C1SRC_SHIFT (0x00000011u)
+
+#define SYSCFG_SUSPSRC_I2C0SRC  (0x00010000u)
+#define SYSCFG_SUSPSRC_I2C0SRC_SHIFT (0x00000010u)
+
+
+#define SYSCFG_SUSPSRC_VPIFSRC  (0x00004000u)
+#define SYSCFG_SUSPSRC_VPIFSRC_SHIFT (0x0000000Eu)
+
+#define SYSCFG_SUSPSRC_SATASRC  (0x00002000u)
+#define SYSCFG_SUSPSRC_SATASRC_SHIFT (0x0000000Du)
+
+#define SYSCFG_SUSPSRC_HPISRC   (0x00001000u)
+#define SYSCFG_SUSPSRC_HPISRC_SHIFT  (0x0000000Cu)
+
+
+#define SYSCFG_SUSPSRC_USB0SRC  (0x00000200u)
+#define SYSCFG_SUSPSRC_USB0SRC_SHIFT (0x00000009u)
+
+#define SYSCFG_SUSPSRC_MCBSP1SRC (0x00000100u)
+#define SYSCFG_SUSPSRC_MCBSP1SRC_SHIFT (0x00000008u)
+
+#define SYSCFG_SUSPSRC_MCBSP0SRC (0x00000080u)
+#define SYSCFG_SUSPSRC_MCBSP0SRC_SHIFT (0x00000007u)
+
+#define SYSCFG_SUSPSRC_PRUSRC   (0x00000040u)
+#define SYSCFG_SUSPSRC_PRUSRC_SHIFT  (0x00000006u)
+
+#define SYSCFG_SUSPSRC_EMACSRC  (0x00000020u)
+#define SYSCFG_SUSPSRC_EMACSRC_SHIFT (0x00000005u)
+
+#define SYSCFG_SUSPSRC_UPPSRC   (0x00000010u)
+#define SYSCFG_SUSPSRC_UPPSRC_SHIFT  (0x00000004u)
+
+#define SYSCFG_SUSPSRC_TIMER64P_3SRC (0x00000008u)
+#define SYSCFG_SUSPSRC_TIMER64P_3SRC_SHIFT (0x00000003u)
+
+#define SYSCFG_SUSPSRC_ECAP2SRC (0x00000004u)
+#define SYSCFG_SUSPSRC_ECAP2SRC_SHIFT (0x00000002u)
+
+#define SYSCFG_SUSPSRC_ECAP1SRC (0x00000002u)
+#define SYSCFG_SUSPSRC_ECAP1SRC_SHIFT (0x00000001u)
+
+#define SYSCFG_SUSPSRC_ECAP0SRC (0x00000001u)
+#define SYSCFG_SUSPSRC_ECAP0SRC_SHIFT (0x00000000u)
+
+
+/* CHIPSIG */
+
+
+#define SYSCFG_CHIPSIG_CHIPSIG4 (0x00000010u)
+#define SYSCFG_CHIPSIG_CHIPSIG4_SHIFT (0x00000004u)
+
+#define SYSCFG_CHIPSIG_CHIPSIG3 (0x00000008u)
+#define SYSCFG_CHIPSIG_CHIPSIG3_SHIFT (0x00000003u)
+
+#define SYSCFG_CHIPSIG_CHIPSIG2 (0x00000004u)
+#define SYSCFG_CHIPSIG_CHIPSIG2_SHIFT (0x00000002u)
+
+#define SYSCFG_CHIPSIG_CHIPSIG1 (0x00000002u)
+#define SYSCFG_CHIPSIG_CHIPSIG1_SHIFT (0x00000001u)
+
+#define SYSCFG_CHIPSIG_CHIPSIG0 (0x00000001u)
+#define SYSCFG_CHIPSIG_CHIPSIG0_SHIFT (0x00000000u)
+
+
+/* CHIPSIG_CLR */
+
+
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG4 (0x00000010u)
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG4_SHIFT (0x00000004u)
+
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG3 (0x00000008u)
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG3_SHIFT (0x00000003u)
+
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG2 (0x00000004u)
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG2_SHIFT (0x00000002u)
+
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG1 (0x00000002u)
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG1_SHIFT (0x00000001u)
+
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG0 (0x00000001u)
+#define SYSCFG_CHIPSIG_CLR_CHIPSIG0_SHIFT (0x00000000u)
+
+
+/* CFGCHIP0 */
+
+#define SYSCFG_CFGCHIP0_ARM_CLK_DIS0 (0x80000000u)
+#define SYSCFG_CFGCHIP0_ARM_CLK_DIS0_SHIFT (0x0000001Fu)
+
+#define SYSCFG_CFGCHIP0_ARM_TAP_DIS0 (0x40000000u)
+#define SYSCFG_CFGCHIP0_ARM_TAP_DIS0_SHIFT (0x0000001Eu)
+
+
+#define SYSCFG_CFGCHIP0_PLL_MASTER_LOCK (0x00000010u)
+#define SYSCFG_CFGCHIP0_PLL_MASTER_LOCK_SHIFT (0x00000004u)
+
+#define SYSCFG_CFGCHIP0_EDMA30TC1DBS (0x0000000Cu)
+#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_SHIFT (0x00000002u)
+/*----EDMA30TC1DBS Tokens----*/
+#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_16BYTE (0x00000000u)
+#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_32BYTE (0x00000001u)
+#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_64BYTE (0x00000002u)
+#define SYSCFG_CFGCHIP0_EDMA30TC1DBS_RESERVED (0x00000003u)
+
+#define SYSCFG_CFGCHIP0_EDMA30TC0DBS (0x00000003u)
+#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_SHIFT (0x00000000u)
+/*----EDMA30TC0DBS Tokens----*/
+#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_16BYTE (0x00000000u)
+#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_32BYTE (0x00000001u)
+#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_64BYTE (0x00000002u)
+#define SYSCFG_CFGCHIP0_EDMA30TC0DBS_RESERVED (0x00000003u)
+
+
+/* CFGCHIP1 */
+
+#define SYSCFG_CFGCHIP1_CAP2SRC (0xF8000000u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_SHIFT (0x0000001Bu)
+/*----CAP2SRC Tokens----*/
+#define SYSCFG_CFGCHIP1_CAP2SRC_ECAP2 (0x00000000u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP0_TXDMA (0x00000001u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP0_RXDMA (0x00000002u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP1_TXDMA (0x00000003u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP1_RXDMA (0x00000004u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP2_TXDMA (0x00000005u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_MCASP2_RXDMA (0x00000006u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_RXTHPLSEINT (0x00000007u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_RXPLSEINT (0x00000008u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_TXPLSEINT (0x00000009u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C0_MISCINT (0x0000000au)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_RXPLSEINT (0x0000000cu)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_TXPLSEINT (0x0000000du)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C1_MISCINT (0x0000000eu)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_RXPLSEINT (0x00000010u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_TXPLSEINT (0x00000011u)
+#define SYSCFG_CFGCHIP1_CAP2SRC_EMAC_C2_MISCINT (0x00000012u)
+
+#define SYSCFG_CFGCHIP1_CAP1SRC (0x07C00000u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_SHIFT (0x00000016u)
+/*----CAP1SRC Tokens----*/
+#define SYSCFG_CFGCHIP1_CAP1SRC_ECAP1 (0x00000000u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP0_TXDMA (0x00000001u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP0_RXDMA (0x00000002u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP1_TXDMA (0x00000003u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP1_RXDMA (0x00000004u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP2_TXDMA (0x00000005u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_MCASP2_RXDMA (0x00000006u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_RXTHPLSEINT (0x00000007u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_RXPLSEINT (0x00000008u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_TXPLSEINT (0x00000009u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C0_MISCINT (0x0000000au)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_RXPLSEINT (0x0000000cu)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_TXPLSEINT (0x0000000du)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C1_MISCINT (0x0000000eu)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_RXPLSEINT (0x00000010u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_TXPLSEINT (0x00000011u)
+#define SYSCFG_CFGCHIP1_CAP1SRC_EMAC_C2_MISCINT (0x00000012u)
+
+#define SYSCFG_CFGCHIP1_CAP0SRC (0x003E0000u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_SHIFT (0x00000011u)
+/*----CAP0SRC Tokens----*/
+#define SYSCFG_CFGCHIP1_CAP0SRC_ECAP0 (0x00000000u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP0_TXDMA (0x00000001u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP0_RXDMA (0x00000002u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP1_TXDMA (0x00000003u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP1_RXDMA (0x00000004u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP2_TXDMA (0x00000005u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_MCASP2_RXDMA (0x00000006u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_RXTHPLSEINT (0x00000007u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_RXPLSEINT (0x00000008u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_TXPLSEINT (0x00000009u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C0_MISCINT (0x0000000au)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_RXTHPLSEINT (0x0000000bu)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_RXPLSEINT (0x0000000cu)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_TXPLSEINT (0x0000000du)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C1_MISCINT (0x0000000eu)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_RXTHPLSEINT (0x0000000fu)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_RXPLSEINT (0x00000010u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_TXPLSEINT (0x00000011u)
+#define SYSCFG_CFGCHIP1_CAP0SRC_EMAC_C2_MISCINT (0x00000012u)
+
+#define SYSCFG_CFGCHIP1_HPIBYTEAD (0x00010000u)
+#define SYSCFG_CFGCHIP1_HPIBYTEAD_SHIFT (0x00000010u)
+
+#define SYSCFG_CFGCHIP1_HPIENA  (0x00008000u)
+#define SYSCFG_CFGCHIP1_HPIENA_SHIFT (0x0000000Fu)
+
+#define SYSCFG_CFGCHIP1_EDMA31TC0DBS (0x00006000u)
+#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_SHIFT (0x0000000Du)
+/*----EDMA31TC0DBS Tokens----*/
+#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_16BYTE (0x00000000u)
+#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_32BYTE (0x00000001u)
+#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_64BYTE (0x00000002u)
+#define SYSCFG_CFGCHIP1_EDMA31TC0DBS_RESERVED (0x00000003u)
+
+#define SYSCFG_CFGCHIP1_TBCLKSYNC (0x00001000u)
+#define SYSCFG_CFGCHIP1_TBCLKSYNC_SHIFT (0x0000000Cu)
+
+
+#define SYSCFG_CFGCHIP1_AMUTESEL0 (0x0000000Fu)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_SHIFT (0x00000000u)
+/*----AMUTESEL0 Tokens----*/
+#define SYSCFG_CFGCHIP1_AMUTESEL0_LOW (0x00000000u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B0 (0x00000001u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B1 (0x00000002u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B2 (0x00000003u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B3 (0x00000004u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B4 (0x00000005u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B5 (0x00000006u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B6 (0x00000007u)
+#define SYSCFG_CFGCHIP1_AMUTESEL0_GPIO_B7 (0x00000008u)
+
+
+/* CFGCHIP2 */
+
+
+#define SYSCFG_CFGCHIP2_USB0PHYCLKGD (0x00020000u)
+#define SYSCFG_CFGCHIP2_USB0PHYCLKGD_SHIFT (0x00000011u)
+
+#define SYSCFG_CFGCHIP2_USB0VBUSSENSE (0x00010000u)
+#define SYSCFG_CFGCHIP2_USB0VBUSSENSE_SHIFT (0x00000010u)
+
+#define SYSCFG_CFGCHIP2_RESET   (0x00008000u)
+#define SYSCFG_CFGCHIP2_RESET_SHIFT  (0x0000000Fu)
+
+#define SYSCFG_CFGCHIP2_USB0OTGMODE (0x00006000u)
+#define SYSCFG_CFGCHIP2_USB0OTGMODE_SHIFT (0x0000000Du)
+/*----USB0OTGMODE Tokens----*/
+#define SYSCFG_CFGCHIP2_USB0OTGMODE_PHY (0x00000000u)
+#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_HOST (0x00000001u)
+#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_DEVICE (0x00000002u)
+#define SYSCFG_CFGCHIP2_USB0OTGMODE_USB_HOST_LOW (0x00000003u)
+
+#define SYSCFG_CFGCHIP2_USB1PHYCLKMUX (0x00001000u)
+#define SYSCFG_CFGCHIP2_USB1PHYCLKMUX_SHIFT (0x0000000Cu)
+
+#define SYSCFG_CFGCHIP2_USB0PHYCLKMUX (0x00000800u)
+#define SYSCFG_CFGCHIP2_USB0PHYCLKMUX_SHIFT (0x0000000Bu)
+
+#define SYSCFG_CFGCHIP2_USB0PHYPWDN (0x00000400u)
+#define SYSCFG_CFGCHIP2_USB0PHYPWDN_SHIFT (0x0000000Au)
+
+#define SYSCFG_CFGCHIP2_USB0OTGPWRDN (0x00000200u)
+#define SYSCFG_CFGCHIP2_USB0OTGPWRDN_SHIFT (0x00000009u)
+
+#define SYSCFG_CFGCHIP2_USB0DATPOL (0x00000100u)
+#define SYSCFG_CFGCHIP2_USB0DATPOL_SHIFT (0x00000008u)
+
+#define SYSCFG_CFGCHIP2_USB1SUSPENDM (0x00000080u)
+#define SYSCFG_CFGCHIP2_USB1SUSPENDM_SHIFT (0x00000007u)
+
+#define SYSCFG_CFGCHIP2_USB0PHY_PLLON (0x00000040u)
+#define SYSCFG_CFGCHIP2_USB0PHY_PLLON_SHIFT (0x00000006u)
+
+#define SYSCFG_CFGCHIP2_USB0SESNDEN (0x00000020u)
+#define SYSCFG_CFGCHIP2_USB0SESNDEN_SHIFT (0x00000005u)
+
+#define SYSCFG_CFGCHIP2_USB0VBDTCTEN (0x00000010u)
+#define SYSCFG_CFGCHIP2_USB0VBDTCTEN_SHIFT (0x00000004u)
+
+#define SYSCFG_CFGCHIP2_USB0REF_FREQ (0x0000000Fu)
+#define SYSCFG_CFGCHIP2_USB0REF_FREQ_SHIFT (0x00000000u)
+
+
+/* CFGCHIP3 */
+
+
+
+#define SYSCFG_CFGCHIP3_RMII_SEL (0x00000100u)
+#define SYSCFG_CFGCHIP3_RMII_SEL_SHIFT (0x00000008u)
+
+#define SYSCFG_CFGCHIP3_UPP_TX_CLKSRC (0x00000040u)
+#define SYSCFG_CFGCHIP3_UPP_TX_CLKSRC_SHIFT (0x00000006u)
+
+#define SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK (0x00000020u)
+#define SYSCFG_CFGCHIP3_PLL1_MASTER_LOCK_SHIFT (0x00000005u)
+
+#define SYSCFG_CFGCHIP3_ASYNC3_CLKSRC (0x00000010u)
+#define SYSCFG_CFGCHIP3_ASYNC3_CLKSRC_SHIFT (0x00000004u)
+
+#define SYSCFG_CFGCHIP3_PRUEVTSEL (0x00000008u)
+#define SYSCFG_CFGCHIP3_PRUEVTSEL_SHIFT (0x00000003u)
+
+#define SYSCFG_CFGCHIP3_DIV4P5ENA (0x00000004u)
+#define SYSCFG_CFGCHIP3_DIV4P5ENA_SHIFT (0x00000002u)
+
+#define SYSCFG_CFGCHIP3_EMA_CLKSRC (0x00000002u)
+#define SYSCFG_CFGCHIP3_EMA_CLKSRC_SHIFT (0x00000001u)
+
+#define SYSCFG_CFGCHIP4_AMUTECLR0 (0x00000001u)
+#define SYSCFG_CFGCHIP4_AMUTECLR0_SHIFT (0x00000000u)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _HW_SYSCFG1_H_ */
diff --git a/src/logman.c b/src/logman.c
new file mode 100644
index 0000000..db91907
--- /dev/null
+++ b/src/logman.c
@@ -0,0 +1,430 @@
+/*
+ * logman.c
+ *
+ *  Created on: 08-04-2014
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#include <string.h>
+#include <stdlib.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Clock.h>
+#include <ti/sysbios/hal/Timer.h>
+
+#include "tdefs.h"
+#include "logman.h"
+#include "misc.h"
+#include "comm.h"
+
+#include "logic_elements/elements.h"
+#include "logic_elements/eth.h"
+#include "ports/am1808/include/netif/sitaraif.h"
+
+struct logic_manager log_manager;
+struct logman_profiler log_profile[MAX_LOG_ELEMENTS];
+//u32 debug_size[8];
+
+#pragma LOCATION(log_profile,0xc5400000) // @ non-cached memory above 128MB
+
+void logman_reset()
+{
+	u32 i;
+	memset((void *)&measurands,0,sizeof(measurands));
+	memset(&log_manager,0,sizeof(log_manager));
+	memset(&log_profile,0,sizeof(log_profile));
+
+	dbg.logman_cycle_time_max=0;
+	dbg.logman_cycle_time=0;
+	ev_reg_log=NULL;
+//	led_blink_states=0;
+//	led_states=0;
+//	virt_in_states=0;
+	virt_in_mask=0;
+	virt_in2_mask=0;
+	dfr_drv_log_ptr=NULL;
+	ddr_drv_log_ptr=NULL;
+	dev_ctrl_state=0;
+	memset((u8*)force_bus_bin_data,0,sizeof(force_bus_bin_data));
+	memset((u8*)force_bus_out_data,0,sizeof(force_bus_out_data));
+	memset((u8*)bus_an_samples_neg,0,sizeof(bus_an_samples_neg));
+//	memset((u8*)ic->out_set,0,sizeof(ic->out_set));
+	for(i=0;i<MAX_REG_BANKS;i++)
+		regs.bank[i].state=BANK_EMPTY;
+
+	log_manager.cur_buf_ptr = log_manager.buf;
+	log_manager.nets_data[0]&=~0x01; // all unused inputs will be pulled down
+	log_manager.nets_data[0]|=0x02;
+	logman_notify=0;
+
+	mwd32_mask=0;
+	ic->mwd32_present=0;
+
+	emac_hash_clear(EMAC_0_BASE);
+}
+
+int logman_pushfunc(u16 fun_id,void *args, u32 args_size)
+{
+	u32 i=0;
+	u32 fun_index=0;
+//	u32 dbgg;
+
+	void *argsptr,*logptr;
+
+	if(log_manager.cur_element_num>=MAX_LOG_ELEMENTS)
+		return -5;
+
+	while(log_elements[i].id!=EOF_ELEMENT)
+	{
+		if(log_elements[i].id == fun_id)
+			break;
+		i++;
+	}
+
+	if(log_elements[i].id==EOF_ELEMENT)
+		return -1;
+
+	fun_index=i;
+
+	if(log_elements[fun_index].args_size != args_size && ((fun_id != GOOSE_FUN_ID && fun_id != SV_FUN_ID && fun_id != GOOSE_OUT_FUN_ID) || args_size<log_elements[fun_index].args_size) )
+		return -2;
+
+	if((log_manager.cur_buf_ptr + args_size) > (log_manager.buf + LOGMAN_BUFSIZE))
+		return -3;
+
+	log_manager.log_element[log_manager.cur_element_num].el_num = fun_index;
+//	log_manager.log_element[log_manager.cur_element_num].fun_main_ptr = log_elements[fun_index].fun_ptr;
+//	log_manager.log_element[log_manager.cur_element_num].fun_100hz_ptr = log_elements[fun_index].fun_100hz_ptr;
+//	log_manager.log_element[log_manager.cur_element_num].fun_20hz_ptr = log_elements[fun_index].fun_20hz_ptr;
+
+//	dbgg=(u32)(log_manager.cur_buf_ptr);
+
+	memcpy(log_manager.cur_buf_ptr,args,args_size);
+	log_manager.log_element[log_manager.cur_element_num].fun_args_ptr = log_manager.cur_buf_ptr;
+	argsptr=log_manager.cur_buf_ptr;
+	log_manager.cur_buf_ptr+=args_size;
+
+	if((log_manager.cur_buf_ptr + log_elements[fun_index].log_size) > (log_manager.buf + LOGMAN_BUFSIZE))
+		return -4;
+
+	log_manager.log_element[log_manager.cur_element_num].fun_log_ptr = log_manager.cur_buf_ptr;
+	logptr=log_manager.cur_buf_ptr;
+
+	log_manager.cur_buf_ptr+=log_elements[fun_index].log_size;
+
+	if(log_elements[fun_index].initlog_ptr)
+		if(log_elements[fun_index].initlog_ptr(argsptr,logptr))
+			return -6;
+
+	if(fun_id == EVENTS_REG_FUN_ID)
+	{
+		struct events_reg_logic *evreg_l = (struct events_reg_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&evreg_l->element_num[evreg_l->events_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[0]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == OUT_DRV_FUN_ID)
+	{
+		struct out_drv_logic *out_drv_l = (struct out_drv_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&out_drv_l->element_num[out_drv_l->out_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[1]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == DFR_DRV_FUN_ID)
+	{
+		struct dfr_drv_logic *dfr_l = (struct dfr_drv_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&dfr_l->element_num[dfr_l->an_count+dfr_l->bin_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[2]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == DDR_DRV_FUN_ID)
+	{
+		struct ddr_drv_logic *ddr_l = (struct ddr_drv_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&ddr_l->element_num[ddr_l->an_count+ddr_l->bin_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[3]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == LEDS_DRV_FUN_ID)
+	{
+		struct leds_drv_logic *leds_l = (struct leds_drv_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&leds_l->element_num[leds_l->leds_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[4]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == VIRT_IN_DRV_FUN_ID)
+	{
+		struct virt_in_drv_logic *virt_l = (struct virt_in_drv_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&virt_l->element_num[virt_l->virt_in_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[5]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == GOOSE_DRV_FUN_ID)
+	{
+		struct goose_drv_logic *g = (struct goose_drv_logic *)logptr;
+		log_manager.cur_buf_ptr=(u8*)&g->element_num[g->gooses_count+1];
+		log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
+	//	debug_size[6]=(u32)(log_manager.cur_buf_ptr)-dbgg;
+	}
+	else if(fun_id == AN_GEN_FUN_ID)
+	{
+	//	struct an_gen_logic *an_gen_l = (struct an_gen_logic *)logptr;
+	//	log_manager.cur_buf_ptr=(u8*)&an_gen_l->element_num[an_gen_l->an_count+1];
+	}
+
+	log_manager.log_element[log_manager.cur_element_num].flags = FUNCTION_ENABLED;
+
+	if(fun_id == EVENT_FUN_ID)
+	{
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_EVENT;
+		log_manager.status|=LOGMAN_USING_EVENTS;
+	}
+	else if(fun_id == REC_AN_FUN_ID)
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_AN;
+	else if(fun_id == REC_BUF_FUN_ID)
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_BUF;
+	else if(fun_id == REC_FLOAT_FUN_ID)
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_FLOAT;
+	else if(fun_id == REC_BIN_FUN_ID)
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_BIN;
+	else if(fun_id == REL_OUT_FUN_ID)
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REL_OUT;
+	else if(fun_id == SV_FUN_ID)
+		log_manager.status|= LOGMAN_USING_IEC_SV;
+	else if(fun_id == GOOSE_FUN_ID)
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_GOOSE;
+	else if(fun_id == DFR_FUN_ID)
+	{
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_DFR;
+		log_manager.status|=LOGMAN_USING_DFR;
+	}
+	else if(fun_id == DDR_FUN_ID)
+	{
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_DDR;
+		log_manager.status|=LOGMAN_USING_DDR;
+	}
+	else if(fun_id == LED_FUN_ID || fun_id == BUZZER_FUN_ID)
+	{
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_LED;
+		log_manager.status|=LOGMAN_USING_LEDS;
+	}
+	else if(fun_id == VIRT_IN_FUN_ID)
+	{
+		log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_VIRT_IN;
+		log_manager.status|=LOGMAN_USING_VIRT_IN;
+	}
+
+	log_manager.cur_element_num++;
+
+	dbg.logman_buf_size_cur = log_manager.cur_buf_ptr - log_manager.buf;
+
+	log_manager.status|=LOGMAN_USING_AN_GEN;
+
+	return 0;
+}
+
+void logman_stop()
+{
+	log_manager.requests|=LOGMAN_REQUEST_STOP;
+	while(log_manager.status & LOGMAN_STATUS_STARTED)
+    	Task_sleep(1);
+}
+
+int logman_start()
+{
+	int ret;
+
+	log_manager.soft_start_cnt=0;
+
+	ret=logman_pushfunc(OUT_DRV_FUN_ID,NULL,0);
+	if(ret)
+		return -7;
+
+	if(log_manager.status & LOGMAN_USING_EVENTS)
+	{
+		ret=logman_pushfunc(EVENTS_REG_FUN_ID,NULL,0);
+		if(ret)
+			return -1;
+		log_manager.status&=~LOGMAN_USING_EVENTS;
+	}
+	if(log_manager.status & LOGMAN_USING_LEDS)
+	{
+		ret=logman_pushfunc(LEDS_DRV_FUN_ID,NULL,0);
+		if(ret)
+			return -2;
+		log_manager.status&=~LOGMAN_USING_LEDS;
+	}
+	if(log_manager.status & LOGMAN_USING_VIRT_IN)
+	{
+		ret=logman_pushfunc(VIRT_IN_DRV_FUN_ID,NULL,0);
+		if(ret)
+			return -3;
+		log_manager.status&=~LOGMAN_USING_VIRT_IN;
+	}
+	if(log_manager.status & LOGMAN_USING_DFR)
+	{
+		ret=logman_pushfunc(DFR_DRV_FUN_ID,NULL,0);
+		if(ret)
+			return -4;
+		log_manager.status&=~LOGMAN_USING_DFR;
+	}
+	if(log_manager.status & LOGMAN_USING_DDR)
+	{
+		ret=logman_pushfunc(DDR_DRV_FUN_ID,NULL,0);
+		if(ret)
+			return -5;
+		log_manager.status&=~LOGMAN_USING_DDR;
+	}
+
+	if(log_manager.status & LOGMAN_USING_AN_GEN)
+	{
+		ret=logman_pushfunc(AN_GEN_FUN_ID,NULL,0);
+		if(ret)
+			return -6;
+		log_manager.status&=~LOGMAN_USING_AN_GEN;
+	}
+
+	log_manager.requests|=LOGMAN_REQUEST_START;
+	while(!(log_manager.status & LOGMAN_STATUS_STARTED))
+    	Task_sleep(1);
+
+	return 0;
+}
+
+void logman_init()
+{
+	logman_reset();
+}
+
+void logman_xkhz()
+{
+	u32 i;
+	u32 t_pre,t_post,t;
+
+	if(log_manager.status & LOGMAN_STATUS_SOFT_STARTED && !(dev_ctrl_state & DEV_CTRL_STATE_TEST_OUT))
+		memcpy((void*)bus_out_data,(void*)ic->out_set,MAX_OUT_CARDS);
+
+	memcpy((void*)bus_bin_data,(void*)ic->bin_in,MAX_BIN_CARDS);
+	memcpy((void*)bus_bin_data_ench,(void*)ic->bin_in_ench,MAX_BIN_CARDS);
+	if(dev_ctrl_state & DEV_CTRL_STATE_TEST_IN)
+	{
+		for(i=0;i<MAX_BIN_CARDS;i++)
+		{
+			bus_bin_data[i]^=force_bus_bin_data[i];
+			bus_bin_data_ench[i]^=force_bus_bin_data_ench[i];
+		}
+	}
+
+	if(log_manager.requests & LOGMAN_REQUEST_STOP)
+	{
+		log_manager.status&=~LOGMAN_STATUS_STARTED;
+		log_manager.requests&=~LOGMAN_REQUEST_STOP;
+	}
+
+	if(log_manager.requests & LOGMAN_REQUEST_START)
+	{
+		log_manager.status|=LOGMAN_STATUS_STARTED;
+		log_manager.requests&=~LOGMAN_REQUEST_START;
+	}
+
+	if(log_manager.status & LOGMAN_STATUS_STARTED)
+	{
+		//logman_notify=0;
+
+		if(log_manager.soft_start_cnt<LOGMAN_SOFT_START_TIME)
+			log_manager.soft_start_cnt++;
+		else
+		{
+			if(!(log_manager.status & LOGMAN_STATUS_SOFT_STARTED))
+				log_manager.status|=LOGMAN_STATUS_SOFT_STARTED;
+		}
+		if(!(log_manager.status & LOGMAN_STATUS_PROFILING))
+		{
+			for(i=0;i<MAX_LOG_ELEMENTS;i++)
+			{
+				if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_main_ptr)
+					log_elements[log_manager.log_element[i].el_num].fun_main_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
+				else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
+				{
+					dbg.used_elements=i;
+					break;
+				}
+			}
+		}
+		else // profiling
+		{
+			for(i=0;i<MAX_LOG_ELEMENTS;i++)
+			{
+				if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_main_ptr)
+				{
+					t_pre=PWM1_GET(PWM1_TBCNT);
+					log_elements[log_manager.log_element[i].el_num].fun_main_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
+					t_post=PWM1_GET(PWM1_TBCNT);
+					if(t_post>=t_pre)
+						t = t_post-t_pre;
+					else
+						t = t_post+65536-t_pre;
+
+					log_profile[i].t_cur=t;
+
+					if(t>log_profile[i].t_max)
+						log_profile[i].t_max=t;
+				}
+				else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
+					break;
+			}
+		}
+
+		if(logman_notify)
+			Swi_post(swi_notify);
+	}
+
+	if(log_manager.status & LOGMAN_STATUS_SOFT_STARTED)
+	{
+		if(dev_ctrl_state & DEV_CTRL_STATE_TEST_OUT)
+		{
+			for(i=0;i<MAX_OUT_CARDS;i++)
+				bus_out_data_test[i]=force_bus_out_data[i]^bus_out_data[i];
+
+			if(!(dev_ctrl_state & DEV_CTRL_STATE_BLOCK_OUT))
+				memcpy((void*)ic->out_set,(void*)bus_out_data_test,MAX_OUT_CARDS*2);
+		}
+		else
+		{
+			if(!(dev_ctrl_state & DEV_CTRL_STATE_BLOCK_OUT))
+				memcpy((void*)ic->out_set,(void*)bus_out_data,MAX_OUT_CARDS*2);
+		}
+	}
+
+}
+
+void logman_100hz()
+{
+	u32 i;
+
+	if(log_manager.status & LOGMAN_STATUS_STARTED)
+	{
+		for(i=0;i<MAX_LOG_ELEMENTS;i++)
+		{
+			if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_100hz_ptr)
+				log_elements[log_manager.log_element[i].el_num].fun_100hz_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
+			else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
+				break;
+		}
+
+	}
+}
+
+void logman_20hz()
+{
+	u32 i;
+
+	if(log_manager.status & LOGMAN_STATUS_STARTED)
+	{
+		for(i=0;i<MAX_LOG_ELEMENTS;i++)
+		{
+			if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_20hz_ptr)
+				log_elements[log_manager.log_element[i].el_num].fun_20hz_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
+			else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
+				break;
+		}
+	}
+}
diff --git a/src/logman.h b/src/logman.h
new file mode 100644
index 0000000..4f9dd87
--- /dev/null
+++ b/src/logman.h
@@ -0,0 +1,94 @@
+/*
+ * logman.h
+ *
+ *  Created on: 08-04-2014
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#ifndef LOGMAN_H_
+#define LOGMAN_H_
+
+#include "config.h"
+
+// logic manager function flags
+#define FUNCTION_NOT_INITIALIZED		0x0000
+#define FUNCTION_ENABLED				0x0001
+#define FUNCTION_IS_DDR					0x8000
+#define FUNCTION_IS_REC_FLOAT			0x4000
+#define FUNCTION_IS_DFR					0x2000
+#define FUNCTION_IS_VIRT_IN				0x1000
+#define FUNCTION_IS_LED					0x0800
+#define FUNCTION_IS_MEASURAND			0x0400
+#define FUNCTION_IS_REC_AN				0x0200
+#define FUNCTION_IS_REC_BIN				0x0100
+#define FUNCTION_IS_EVENT				0x0080
+#define FUNCTION_IS_REL_OUT				0x0040
+#define FUNCTION_IS_REC_BUF				0x0020
+#define FUNCTION_IS_GOOSE				0x0010
+
+// logman status
+#define LOGMAN_STATUS_STARTED		0x00000001
+#define LOGMAN_STATUS_SOFT_STARTED	0x00000002
+#define LOGMAN_STATUS_PROFILING		0x00000004
+#define LOGMAN_USING_IEC_SV			0x02000000
+#define LOGMAN_USING_AN_GEN			0x04000000
+#define LOGMAN_USING_DDR			0x08000000
+#define LOGMAN_USING_DFR			0x10000000
+#define LOGMAN_USING_VIRT_IN		0x20000000
+#define LOGMAN_USING_EVENTS			0x40000000
+#define LOGMAN_USING_LEDS			0x80000000
+
+// logman requests
+#define LOGMAN_REQUEST_START	0x00000001
+#define LOGMAN_REQUEST_STOP		0x00000002
+
+#define LOGMAN_BUFSIZE			65536-8192+1792+2560 //98304 +2048 dodano 26.08.2024 dla TZL-8
+#define LOGMAN_NETSDATA_SIZE	1536//32768
+
+#define LOGMAN_SOFT_START_TIME	200
+
+extern u32 debug_size[8];
+
+struct logman_profiler
+{
+	u16 t_cur;
+	u16 t_max;
+};
+
+extern struct logman_profiler log_profile[MAX_LOG_ELEMENTS];
+
+struct logic_element
+{
+	u16 flags;
+	u8 el_num;
+//	void (*fun_main_ptr)(void*,void*);
+//	void (*fun_100hz_ptr)(void*,void*);
+//	void (*fun_20hz_ptr)(void*,void*);
+	void (*fun_args_ptr);
+	void (*fun_log_ptr);
+};
+
+struct logic_manager
+{
+	u32 status;
+	u32 requests;
+	u16 cur_element_num;
+	u8 *cur_buf_ptr;
+	struct logic_element log_element[MAX_LOG_ELEMENTS];
+	u8 buf[LOGMAN_BUFSIZE];
+	u8 nets_data[LOGMAN_NETSDATA_SIZE];
+	u8 soft_start_cnt;
+};
+
+extern struct logic_manager log_manager;
+
+extern void logman_xkhz();
+extern void logman_100hz();
+extern void logman_20hz();
+extern void logman_init();
+extern void logman_reset();
+extern void logman_stop();
+extern int logman_start();
+extern int logman_pushfunc(u16 fun_id,void *args, u32 args_size);
+
+#endif /* LOGMAN_H_ */
diff --git a/src/main.c b/src/main.c
new file mode 100644
index 0000000..68a6446
--- /dev/null
+++ b/src/main.c
@@ -0,0 +1,533 @@
+/*
+ * main.c
+ *
+ *  Created on: 01-06-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#include <xdc/std.h>
+
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Swi.h>
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/hal/Timer.h>
+#include <ti/sysbios/knl/Clock.h>
+#include <ti/ipc/Notify.h>
+#include <string.h>
+
+#include "misc.h"
+#include "comm.h"
+#include "tdefs.h"
+#include "logman.h"
+#include "spi.h"
+#include "logic_elements/dev_ctrl.h"
+#include "logic_elements/an_gen.h"
+#include "logic_elements/events_reg.h"
+//pwm
+#include "psc.h"
+#include "soc_OMAPL138.h"
+#include "hw_syscfg0_OMAPL138.h"
+#include "hw_types.h"
+//
+/// ethernet
+#include "ethernet/ports/am1808/include/lwiplib.h"
+///
+#include "config.h"
+
+volatile unsigned short last_sample_no;
+volatile unsigned short samples_dropped = 0;
+volatile unsigned short last_sample_sync_no;
+volatile unsigned short samples_sync_dropped = 0;
+volatile int is_first_sample = 1;
+volatile int irqs = 0;
+u16 bus_an_cur_timestamp = 0;
+
+#pragma LOCATION(shared_buf,0xc5500000) // @ non-cached memory above 128MB
+volatile int shared_buf[1024];
+
+#pragma DATA_ALIGN(analog_buf, 128) // place @ cache line boundary
+volatile short analog_buf[127];
+
+//volatile int analog_buf_ready = 0;
+//volatile int analog_buf_cnt = 0;
+unsigned int analog_buf_card = 0;
+unsigned int analog_buf_channel = 0;
+
+struct device_config dev_cfg;
+
+u8 mwd_states_cur[MAX_BIN_CARDS];
+u8 mwd_states_prev[MAX_BIN_CARDS];
+
+Swi_Handle swi_notify;
+Swi_Params swi_notify_params;
+
+Swi_Handle swi_ms;
+Swi_Params swi_ms_params;
+
+Swi_Handle swi_10ms;
+Swi_Params swi_10ms_params;
+
+Swi_Handle swi_50ms;
+Swi_Params swi_50ms_params;
+
+extern Timer_Handle timer0;
+
+u8 loops_synced=0;
+
+u8 khz_trigger=LOOP_CYCLE_MS * SAMPLES_PER_MS;
+
+volatile u32 cycle_pwm=0;
+volatile struct timeval cur_time = { 1388563200, 0 }; // default 2014-01-01
+volatile struct timeval cur_time_sw = { 1577836800, 0 }; // default 2020-01-01
+u8 bus_an_cur_sample_num_prev=0;
+u8 sample_watch_init=0;
+u8 cur_sample_diff=0;
+
+void pwm_init()
+{
+    PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_EHRPWM, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
+	PWM1_SET(PWM1_TBCTL, 0x8D03); //FREE RUN, CLKDIV /8, HSPCLKDIV /4, STOP
+	PWM1_SET(PWM1_TBPRD, 0xFFFF);
+	PWM1_SET(PWM1_TBCNT, 0x0000);
+	HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP1) |= SYSCFG_CFGCHIP1_TBCLKSYNC;
+}
+
+void pwm_start_cnt()
+{
+	PWM1_SET(PWM1_TBCNT, 0x0000); //COUNTER = 0
+	PWM1_SET(PWM1_TBCTL, 0x8D00); //START
+}
+
+u32 pwm_stop_cnt()
+{
+	PWM1_SET(PWM1_TBCTL, 0x8D03);//STOP
+	return PWM1_GET(PWM1_TBCNT);
+}
+
+Void notify_swi(UArg a0, UArg a1)
+{
+	u32 requests = logman_notify;
+
+	if(requests & LOGMAN_NOTIFY_NEW_EVENTS)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_EVENTS | ((u32)ev_db.pos<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_NEW_EVENTS;
+	}
+
+	if(requests & LOGMAN_NOTIFY_NEW_DFR)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_DFR_REG, TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_NEW_DFR;
+	}
+
+	if(requests & LOGMAN_NOTIFY_NEW_DDR)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_DDR_REG, TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_NEW_DDR;
+	}
+
+	if(requests & LOGMAN_NOTIFY_BANK0)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK0|(service_mode<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_BANK0;
+	}
+
+	if(requests & LOGMAN_NOTIFY_BANK1)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK1|(service_mode<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_BANK1;
+	}
+
+	if(requests & LOGMAN_NOTIFY_BANK2)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK2|(service_mode<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_BANK2;
+	}
+
+	if(requests & LOGMAN_NOTIFY_BANK3)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK3|(service_mode<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_BANK3;
+	}
+
+	if(requests & LOGMAN_NOTIFY_BANK4)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK4|(service_mode<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_BANK4;
+	}
+
+	if(requests & LOGMAN_NOTIFY_BANK5)
+	{
+		Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK5|(service_mode<<8), TRUE);
+		logman_notify&=~LOGMAN_NOTIFY_BANK5;
+	}
+
+}
+
+volatile u16 pps_low_cnt=0;
+volatile u16 pps3_timeout_cnt=0xFFFF;
+
+Void ms_hook(UArg a0, UArg a1)
+{
+	u32 t_pre,t_post,sync_reg;
+	u8 pps=0;
+
+	t_pre=PWM1_GET(PWM1_TBCNT);
+
+	bus_an_cur_sample_num=bus_an_cur_sample_num_xkhz;//bus_an_cur_sample_num_3khz;
+
+	// gdy IEC SV to cofamy czas/pozycje bufora o obiegi pętli w celu synchronizacji próbek
+  	if(log_manager.status & LOGMAN_USING_IEC_SV)
+	{
+		if(bus_an_cur_sample_num<(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES))
+			bus_an_cur_sample_num=SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2-((SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES)-bus_an_cur_sample_num);
+		else
+			bus_an_cur_sample_num-=(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES);
+	}
+
+	sync_reg = ic->sync_reg;
+	if(sync_reg & (PPS_SYNCED|IRIGB_SYNCED))
+		ext_sync=1;
+
+
+	if(timesync_method==SYNC_METHOD_IEC103||timesync_method==SYNC_METHOD_ZP6||timesync_method==SYNC_METHOD_MLB || (timesync_method==SYNC_METHOD_CUSTOM & !(timesync_bits & CFG_TSYNC_USE_PPS)))
+		ext_sync=0;
+
+	bus_an_cur_timestamp=tstamp_khz;
+  	if(log_manager.status & LOGMAN_USING_IEC_SV)
+  	{
+		if(bus_an_cur_timestamp<(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES))
+			bus_an_cur_timestamp=SAMPLES_PER_MS*1000-((SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES)-bus_an_cur_timestamp);
+		else
+			bus_an_cur_timestamp-=(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES);
+  	}
+
+	if(!ext_sync)
+	{
+		cur_time.tv_usec+=LOOP_CYCLE_MS;
+
+		if(cur_time.tv_usec>=1000)
+		{
+			cur_time.tv_usec=0;
+			cur_time.tv_sec++;
+		}
+	}
+	else
+	{
+		u32 usec_prev;
+		usec_prev=cur_time.tv_usec;
+		cur_time.tv_usec=bus_an_cur_timestamp/SAMPLES_PER_MS;
+	  	if(!cur_time.tv_usec && usec_prev)
+			cur_time.tv_sec++;
+
+	}
+
+	if(pps3_timeout_cnt!=0xFFFF)
+		pps3_timeout_cnt++;
+
+	if(!(IN_DATA01 & (1<<4)))
+	{
+		if(pps_low_cnt<(1000/LOOP_CYCLE_MS))
+			pps_low_cnt++;
+	}
+	else
+	{
+		if(pps_low_cnt>(600/LOOP_CYCLE_MS) && pps_low_cnt<(900/LOOP_CYCLE_MS))
+		{
+			pps=1;
+			pps3_timeout_cnt=0;
+		}
+
+		pps_low_cnt=0;
+	}
+
+	if(((sync_reg & 0x80) && (timesync_method==SYNC_METHOD_IRIG_B || timesync_method==SYNC_METHOD_IRIG_B_ZPRAE || (timesync_method==SYNC_METHOD_CUSTOM && (timesync_bits & CFG_TSYNC_FROM_DSP))))
+		|| (pps && (timesync_method==SYNC_METHOD_CUSTOM && (timesync_bits & CFG_TSYNC_USE_SWPPS)))
+	)
+	{
+		if(cur_time_sw.tv_usec>900)
+			cur_time_sw.tv_sec++;
+
+		//if(pps)
+		//	zprae_event_add(1,97);
+		cur_time_sw.tv_usec=0;
+	}
+	else
+	{
+		cur_time_sw.tv_usec+=LOOP_CYCLE_MS;
+
+		if(cur_time_sw.tv_usec>=1000)
+		{
+			cur_time_sw.tv_usec=0;
+			cur_time_sw.tv_sec++;
+		}
+	}
+
+
+	if(bus_an_cur_sample_num_prev<=bus_an_cur_sample_num)
+		cur_sample_diff=bus_an_cur_sample_num-bus_an_cur_sample_num_prev;
+	else
+		cur_sample_diff=(u16)bus_an_cur_sample_num+(SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2)-bus_an_cur_sample_num_prev;
+
+	if(cur_sample_diff!=(SAMPLES_PER_MS*LOOP_CYCLE_MS) && sample_watch_init) // debug lost x kHz loops
+	{
+	//	if(cur_sample_diff>dbg.delta_period)
+		//	dbg.delta_period=cur_sample_diff;
+		dbg.temp_dbg++;
+	}
+
+	bus_an_cur_sample_num_prev = bus_an_cur_sample_num;
+	sample_watch_init=1;
+
+	logman_xkhz();
+
+	t_post=PWM1_GET(PWM1_TBCNT);
+
+	if(t_post>=t_pre)
+		dbg.logman_cycle_time = t_post-t_pre;
+	else
+		dbg.logman_cycle_time = t_post+65536-t_pre;
+
+	if(dbg.logman_cycle_time>dbg.logman_cycle_time_max)
+		dbg.logman_cycle_time_max=dbg.logman_cycle_time;
+
+
+
+}
+
+Void ms10_hook(UArg a0, UArg a1)
+{
+	logman_100hz();
+}
+
+Void ms50_hook(UArg a0, UArg a1)
+{
+	logman_20hz();
+}
+
+Void spi_irq(UArg arg)
+{
+	 Hwi_clearInterrupt(14);
+}
+
+UInt IntGlobalDisable()
+{
+	return Hwi_disable();
+}
+
+UInt IntGlobalRestore(UInt hwi_key)
+{
+	Hwi_restore(hwi_key);
+	return 0;
+}
+
+u8 spi_frame[32];
+u8 spi_processed=1;
+
+Void comm_irq(UArg arg)
+{
+	int i;
+	u32 t_pre,t_post;
+
+	t_pre=PWM1_GET(PWM1_TBCNT);
+
+	bus_an_cur_sample_num_3khz++;
+	bus_an_cur_sample_num_3khz%=(SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2);
+
+/* Nie potrzebne przy PPS
+	if(!ext_sync && timesync_method!=SYNC_METHOD_IRIG_B && timesync_method!=SYNC_METHOD_IRIG_B_ZPRAE && !(timesync_bits & CFG_TSYNC_FROM_DSP) && ic->spi_reg & 0x01)
+	{
+		if(ic->spi_frame[7]==0x01 && ic->spi_frame[0]==0x68 && ic->spi_frame[31]==0x16 && ic->spi_frame[1]==0x1a && spi_processed)
+		{
+			memcpy(spi_frame,(char *)&ic->spi_frame[0],32);
+			if(mod256_cksum(spi_frame+4,26)==spi_frame[30] && spi_frame[1]==0x1a && spi_frame[7]==0x01 && spi_frame[9]!=0xD5) // time sync req
+			{
+				u16 ms;
+				ms = (u16)spi_frame[9] | ((u16)spi_frame[10]<<8);
+				ms%=1000;
+
+				if(!ext_sync)
+					cur_time.tv_usec = ms;
+
+				cur_time_sw.tv_usec = ms;
+
+				//dbg.temp_dbg++;
+				spi_processed=0;
+			}
+		}
+	}
+	else
+		spi_processed=1;
+*/
+
+	for(i=0;i<MAX_AN_CARDS/2;i++)
+	{
+		if((dev_ctrl_state & DEV_CTRL_STATE_TEST_AN) && an_gen_buf_ready && (i<MAX_AN_CARDS/2))
+		{
+			if(!(genpar.an_force_mask & (1<< ((i<<2)+(0)))))
+				bus_an_samples_buf[i][0][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][0]?(65534-((u16)ic->an_in[i].l1 + 32767)):((u16)ic->an_in[i].l1 + 32767);
+
+			if(!(genpar.an_force_mask & (1<< ((i<<2)+(1)))))
+				bus_an_samples_buf[i][1][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][1]?(65534-((u16)ic->an_in[i].l2 + 32767)):((u16)ic->an_in[i].l2 + 32767);
+
+			if(!(genpar.an_force_mask & (1<< ((i<<2)+(2)))))
+				bus_an_samples_buf[i][2][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][2]?(65534-((u16)ic->an_in[i].l3 + 32767)):((u16)ic->an_in[i].l3 + 32767);
+
+			if(!(genpar.an_force_mask & (1<< ((i<<2)+(3)))))
+				bus_an_samples_buf[i][3][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][3]?(65534-((u16)ic->an_in[i].l4 + 32767)):((u16)ic->an_in[i].l4 + 32767);
+
+		}
+		else
+		{
+			bus_an_samples_buf[i][0][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][0]?(65534-((u16)ic->an_in[i].l1 + 32767)):((u16)ic->an_in[i].l1 + 32767);
+			bus_an_samples_buf[i][1][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][1]?(65534-((u16)ic->an_in[i].l2 + 32767)):((u16)ic->an_in[i].l2 + 32767);
+			bus_an_samples_buf[i][2][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][2]?(65534-((u16)ic->an_in[i].l3 + 32767)):((u16)ic->an_in[i].l3 + 32767);
+			bus_an_samples_buf[i][3][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][3]?(65534-((u16)ic->an_in[i].l4 + 32767)):((u16)ic->an_in[i].l4 + 32767);
+		}
+	}
+
+
+	if(loops_synced)
+	{
+		if(!--khz_trigger)
+		{
+			bus_an_cur_sample_num_xkhz=bus_an_cur_sample_num_3khz;
+			tstamp_khz=ic->sample_sync_no;
+			Swi_post(swi_ms);
+			khz_trigger=SAMPLES_PER_MS*LOOP_CYCLE_MS;
+		}
+		//Swi_dec(swi_1ms);
+		Swi_dec(swi_10ms);
+		Swi_dec(swi_50ms);
+	}
+
+	if(!loops_synced && (ic->sample_sync_no==0))
+	{
+		loops_synced=1;
+		bus_an_cur_sample_num_3khz=0; //dodano przy okazji SV
+	}
+
+	//dodano na wszelki wypadek, bo czasem pętle się nie synchronizowały, dlaczego? FPGA?
+	//trzeba to sprawdzic bo moze byc skutek uboczny || zakomentowano jednak po poprawie sync na 2ms w fpga
+	//if(ic->sample_sync_no==0)
+	//	khz_trigger=LOOP_CYCLE_MS * SAMPLES_PER_MS;
+	//
+
+	i=ic->sample_no;
+
+	if(is_first_sample)
+		is_first_sample=0;
+	else
+		samples_dropped+=(i - last_sample_no)-1;
+
+	last_sample_no=i;
+
+	t_post=PWM1_GET(PWM1_TBCNT);
+
+	if(t_post>=t_pre)
+		dbg.irq_time = t_post-t_pre;
+	else
+		dbg.irq_time = t_post+65536-t_pre;
+}
+
+void configure_pwr_ok_gpio()
+{
+	KICK0R=KICK0R_VAL;
+	KICK1R=KICK1R_VAL;
+
+	PINMUX0=(PINMUX0 & ~(PINMUX3_15_12)) | (0x08 << 12); // pwr1_ok GP0[12] as GPIO
+	PINMUX1=(PINMUX1 & ~(PINMUX3_11_8)) | (0x08 << 8); // pwr2_ok GP0[5] as GPIO
+	PINMUX1=(PINMUX1 & ~(PINMUX3_15_12)) | (0x08 << 12); // pps3 GP0[4] as GPIO
+	PINMUX2=(PINMUX2 & ~(PINMUX3_19_16)) | (0x04 << 16); // gp1[11] (PPS from GPS) as GPIO
+
+	DIR01|=((1<<4)|(1<<5)|(1<<12)|(1<<27)); // gp0.4, gp0.5, gp0.12 and gp1 .11 as input
+	PUPD_ENA|=((1<<0)|(1<<2)); // enable pull up/down control 1<<5 == GP1[11]
+	PUPD_ENA&=~(1<<5); // disable pull up/down for gp1[11]
+	PUPD_SEL|=((1<<0)|(1<<2)); // set pull up
+}
+
+/*
+** Interrupt Handler for Core 0 Receive interrupt
+*/
+void EMACCore0RxIsr(void)
+{
+    lwIPRxIntHandler(0);
+}
+
+/*
+** Interrupt Handler for Core 0 Transmit interrupt
+*/
+void EMACCore0TxIsr(void)
+{
+    lwIPTxIntHandler(0);
+}
+
+Void main()
+{ 
+    Task_Handle task,task2;
+
+    memset((u8*)&dbg,0,sizeof(dbg));
+    ic->sync_reg|=NEG_PPS_IN;
+
+    task = Task_create(commFxn, NULL, NULL);
+    Task_setPri(task,3);
+
+    if (task == NULL) {
+        BIOS_exit(0);
+    }
+
+    task2 = Task_create(spiFxn, NULL, NULL);
+    Task_setPri(task2,2);
+
+    if (task2 == NULL) {
+        BIOS_exit(0);
+    }
+
+    analog_inputs_init();
+
+    logman_init();
+
+    Swi_Params_init(&swi_ms_params);
+    swi_ms_params.priority = 15;
+
+    swi_ms_params.trigger = SAMPLES_PER_MS * LOOP_CYCLE_MS; // every x samples
+    swi_ms = Swi_create(&ms_hook,&swi_ms_params,NULL);
+
+    Swi_Params_init(&swi_10ms_params);
+    swi_10ms_params.priority = 10;
+    swi_10ms_params.trigger = SAMPLES_PER_MS * 10; // (10 ms)
+    swi_10ms = Swi_create(&ms10_hook,&swi_10ms_params,NULL);
+
+    Swi_Params_init(&swi_50ms_params);
+    swi_50ms_params.priority = 8;
+    swi_50ms_params.trigger = SAMPLES_PER_MS * 50; // (50 ms)
+    swi_50ms = Swi_create(&ms50_hook,&swi_50ms_params,NULL);
+
+    Swi_Params_init(&swi_notify_params);
+    swi_notify_params.priority = 1;
+    swi_notify_params.trigger = 1;
+    swi_notify = Swi_create(&notify_swi,&swi_notify_params,NULL);
+
+    SET_RIS_TRIG8 = (1<<15); // rising edge trig from GP8.15
+
+    configure_pwr_ok_gpio();
+    pwm_init();
+    pwm_start_cnt();
+
+//	eth.hwaddr[0]=0xC4;
+  //  eth.hwaddr[1]=0xff;
+//	eth.hwaddr[2]=0xBC;
+//	eth.hwaddr[3]=0x70;
+//	eth.hwaddr[4]=0x14;
+//	eth.hwaddr[5]=0x3f;
+	//lwIPInit(0, eth.hwaddr, eth.ip, eth.netmask, eth.gateway, IPADDR_USE_STATIC);
+	//Hwi_enableInterrupt(10);
+	//Hwi_enableInterrupt(11);
+
+    BIOS_start();     /* enable interrupts and start SYS/BIOS */
+}
diff --git a/src/misc.c b/src/misc.c
new file mode 100644
index 0000000..7ea0a91
--- /dev/null
+++ b/src/misc.c
@@ -0,0 +1,349 @@
+/*
+ * misc.c
+ *
+ *  Created on: 10-09-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#include "misc.h"
+#include <time.h>
+#include "tdefs.h"
+#include <string.h>
+#include "config.h"
+
+volatile u16 kob_bin_ench=0;
+volatile u16 mwd32_mask=0;
+
+u16 bus_out_data[MAX_OUT_CARDS];
+u16 bus_out_data_test[MAX_OUT_CARDS];
+u16 force_bus_out_data[MAX_OUT_CARDS];
+
+u8 bus_bin_data[MAX_BIN_CARDS];
+u8 force_bus_bin_data[MAX_BIN_CARDS];
+u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
+u8 bus_bin_data_ench[MAX_BIN_CARDS];
+u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
+
+u8 bus_an_samples_neg[MAX_AN_CARDS][4];
+u16 bus_an_samples_buf[MAX_AN_CARDS][4][SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2];
+u8 bus_an_cur_sample_num_3khz = 0;
+u8 bus_an_cur_sample_num_xkhz = 0;
+
+u16 tstamp_khz = 0;
+
+u8 bus_an_cur_sample_num = 0;
+u32 logman_notify = 0;
+volatile u8 ext_sync=0;
+volatile u32 timesync_method=0;
+volatile u32 timesync_bits=0;
+volatile struct in_cards *ic = (struct in_cards *)IN_CARDS_BASE_ADDR;
+struct debug_info dbg;
+
+const uint8_t _ytab[2][12] ={ { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } ,
+						 	  { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } };
+
+
+static int is_leap(unsigned y)
+{
+	y += 1900;
+    return (y % 4) == 0 && ((y % 100) != 0 || (y % 400) == 0);
+}
+
+
+uint32_t timegm (const struct tm *tm)
+{
+	uint32_t res = 0;
+	uint16_t i;
+
+  	for (i = 70; i < tm->tm_year; ++i)
+    	res += is_leap(i) ? 366 : 365;
+
+  	for (i = 0; i < tm->tm_mon; ++i)
+    	res += _ytab[is_leap(tm->tm_year)][i];
+
+  	res += tm->tm_mday - 1;
+  	res *= 24;
+  	res += tm->tm_hour;
+  	res *= 60;
+  	res += tm->tm_min;
+  	res *= 60;
+  	res += tm->tm_sec;
+
+  	return res;
+}
+
+void my_gmtime(const uint32_t *timer, struct tm *timep)
+{
+        uint32_t time = *timer;
+
+        u32 dayclock, dayno;
+        int16_t year = EPOCH_YR;
+
+        dayclock = time % SECS_DAY;
+        dayno = time / SECS_DAY;
+
+        timep->tm_sec = dayclock % 60;
+        timep->tm_min = (dayclock % 3600) / 60;
+        timep->tm_hour = dayclock / 3600;
+        timep->tm_wday = (dayno + 4) % 7;       /* day 0 was a thursday */
+        while (dayno >= YEARSIZE(year)) {
+                dayno -= YEARSIZE(year);
+                year++;
+        }
+        timep->tm_year = year - YEAR0;
+        timep->tm_yday = dayno;
+        timep->tm_mon = 0;
+        while (dayno >= _ytab[LEAPYEAR(year)][timep->tm_mon]) {
+                dayno -= _ytab[LEAPYEAR(year)][timep->tm_mon];
+                timep->tm_mon++;
+        }
+        timep->tm_mday = dayno + 1;
+
+        timep->tm_isdst = 0;
+}
+
+/*
+	isindst() - check if date is in daylight save time
+
+	cest_cet_n - 1 when source tm is a summer time, 0 - winter
+*/
+
+uint8_t isindst(struct tm *tb, uint8_t cest_cet_n)
+{
+	uint8_t tmp;
+
+	if (tb->tm_mon < 2 || tb->tm_mon > 9)
+		return 0;
+
+	if (tb->tm_mon > 2 && tb->tm_mon < 9)
+		return 1;
+
+	tmp=7 - tb->tm_wday + tb->tm_mday;
+
+	if(tb->tm_mon==2) /* march */
+	{
+		if(tmp>31)
+		{
+			if(tb->tm_wday==0)
+			{
+				if ((!cest_cet_n && tb->tm_hour>=2)||(cest_cet_n && tb->tm_hour>=3)) /* it's the last sunday */
+					return 1;
+				else
+					return 0;
+			}
+			else
+				return 1;
+		}
+		else
+			return 0;
+	}
+
+	if(tb->tm_mon==9) /* october */
+	{
+		if(tmp>31)
+		{
+			if(tb->tm_wday==0)
+			{
+				if ((!cest_cet_n && tb->tm_hour>=2)||(cest_cet_n && tb->tm_hour>=3)) /* it's the last sunday */
+					return 0;
+				else
+					return 1;
+			}
+			else
+				return 0;
+		}
+		else
+			return 1;
+	}
+
+	return 0;
+}
+
+
+struct time_data irigb_process_frame()
+{
+	u8 i;
+	u8 tmp_secs;
+	u8 tmp_mins;
+	u8 tmp_hour;
+	u8 tmp_month;
+	u8 tmp_mday;
+	u16 tmp_year;
+	u16 tmp_yearday;
+	u16 tmp;
+	u16 tmp2;
+	uint32_t secs;
+    struct tm tim;
+    struct time_data irigb_time;
+
+	if(ic->sync_reg & 0x4000) // IRIG-B sync
+	{
+		tmp = ic->irigb_p[0] & 0x01FF;
+		tmp_secs = (((tmp & 0x1C0) >> 6)*10) + ((tmp>>1) & 0x00F);
+
+		tmp = ic->irigb_p[1] & 0x01FF;
+		tmp_mins = (((tmp & 0xE0) >> 5)*10) + (tmp & 0x00F);
+
+		tmp = ic->irigb_p[2] & 0x01FF;
+		tmp_hour = (((tmp & 0x60) >> 5)*10) + (tmp & 0x00F);
+
+		tmp = ic->irigb_p[3] & 0x01FF;
+		tmp_yearday = (((tmp & 0x01E0) >> 5)*10) + (tmp & 0x00F);
+		tmp = ic->irigb_p[4] & 0x01FF;
+		tmp_yearday+=((tmp & 0x03)*100);
+
+		tmp = ic->irigb_p[5] & 0x01FF;
+		tmp_year = (((tmp & 0x1E0) >> 5)*10) + (tmp & 0x00F);
+		tmp_year+=2000;
+
+		tmp2=0;
+
+		if(LEAPYEAR(tmp_year))
+		{
+			for(i=0;i<12;i++)
+			{
+				tmp2+=_ytab[1][i];
+				if(tmp_yearday<=tmp2)
+					break;
+			}
+			tmp_mday=tmp_yearday-(tmp2-_ytab[1][i]);
+		}
+		else
+		{
+			for(i=0;i<12;i++)
+			{
+				tmp2+=_ytab[0][i];
+				if(tmp_yearday<=tmp2)
+					break;
+			}
+			tmp_mday=tmp_yearday-(tmp2-_ytab[0][i]);
+		}
+
+		tmp_month=i+1;
+		tmp_year-=1900;
+
+		tmp = (ic->irigb_p[6]) & 0x0000001F;
+		irigb_time.fix_sat=tmp;
+		irigb_time.day=tmp_mday;
+		irigb_time.month=tmp_month-1;
+		irigb_time.year=tmp_year;
+		irigb_time.hour=tmp_hour;
+		irigb_time.min=tmp_mins;
+		irigb_time.sec=tmp_secs;
+
+		tim.tm_hour = irigb_time.hour;
+		tim.tm_min = irigb_time.min;
+		tim.tm_sec = irigb_time.sec;
+
+		tim.tm_mday = irigb_time.day;
+		tim.tm_mon = irigb_time.month;
+		tim.tm_year = irigb_time.year;
+
+		secs=timegm(&tim);
+		my_gmtime(&secs,&tim);
+
+		if(isindst(&tim,0))
+		{
+			tim.tm_hour-=2; /* DST adjust is done by the GPS-Synchro IRIG-B modified protocol */
+			tim.tm_isdst=1;
+		}
+		else
+			tim.tm_hour-=1;
+
+		irigb_time.secs=timegm(&tim)+1;
+
+//		if(!validate_time(&irigb_time))
+		{
+/*			ctime.tv_sec=irigb_time.secs;
+
+			time_flags&=~TIME_INVALID;
+
+			if(tim.tm_isdst)
+				time_flags|=TIME_SUMMER;
+			else
+				time_flags&=~TIME_SUMMER;*/
+		}
+	}
+	else
+		memset((u8 *)&irigb_time,0,sizeof(irigb_time));
+
+	return irigb_time;
+}
+
+void reload_ic_cfg()
+{
+	memcpy((void*)ic->bin_ac_mask,(void*)dev_cfg.mwd_ac_mask,sizeof(ic->bin_ac_mask));
+}
+
+u8 mod256_cksum(uint8_t *buf, u32 len)
+{
+    uint8_t cksum;
+    u32 i;
+
+    cksum=0;
+
+    for(i=0;i<len;i++)
+		cksum+=*(buf++);
+
+    return cksum;
+}
+
+int asn_parse(u8 **buf,int *bytes_left, u8 *tag)
+{
+	int len = 0;
+	u8 oct;
+
+	*tag=**buf;
+	(*buf)++;
+	(*bytes_left)--;
+
+
+	if(**buf & 0x80)
+	{
+		oct = **buf&0x7f;
+		if(oct>2 || oct==0) // too long for us
+			return -1;
+
+		(*buf)++;
+		(*bytes_left)--;
+
+		while(oct && *bytes_left)
+		{
+			len|=**buf;
+			oct--;
+			(*bytes_left)--;
+			(*buf)++;
+			if(oct)
+				len<<=8;
+		}
+
+	}
+	else
+	{
+		len = **buf;
+		(*bytes_left)--;
+		(*buf)++;
+	}
+
+	if (*bytes_left<len)
+		return -1;
+
+	return len;
+}
+
+void analog_inputs_init()
+{
+	int i;
+
+	for(i=0;i<MAX_AN_CARDS;i++)
+	{
+		ic->an_offset[i].l1=32767;
+		ic->an_offset[i].l2=32767;
+		ic->an_offset[i].l3=32767;
+		ic->an_offset[i].l4=32767;
+	}
+
+	bus_an_cur_sample_num_3khz = 0;
+	bus_an_cur_sample_num = 0;
+	memset(bus_an_samples_buf,0,sizeof(bus_an_samples_buf));
+}
diff --git a/src/misc.h b/src/misc.h
new file mode 100644
index 0000000..e4ceb15
--- /dev/null
+++ b/src/misc.h
@@ -0,0 +1,351 @@
+/*
+ * misc.h
+ *
+ *  Created on: 30-07-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#ifndef MISC_H_
+#define MISC_H_
+
+#include "tdefs.h"
+#include "logman.h"
+#include "config.h"
+
+#include <ti/sysbios/hal/Timer.h>
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/knl/Swi.h>
+
+#define MAX_AN_CARDS	16
+#define MAX_BIN_CARDS	16
+#define MAX_OUT_CARDS	16
+
+#define NEED_RELOAD_IC	0x01
+
+#define IN_CARDS_BASE_ADDR	0x64000000
+
+extern u32 logman_notify;
+
+#define LOGMAN_NOTIFY_NEW_EVENTS	0x01
+#define LOGMAN_NOTIFY_NEW_DFR		0x02
+#define LOGMAN_NOTIFY_NEW_DDR		0x04
+#define LOGMAN_NOTIFY_BANK0			0x08
+#define LOGMAN_NOTIFY_BANK1			0x10
+#define LOGMAN_NOTIFY_BANK2			0x20
+#define LOGMAN_NOTIFY_BANK3			0x40
+#define LOGMAN_NOTIFY_BANK4			0x80
+#define LOGMAN_NOTIFY_BANK5			0x100
+
+extern volatile short analog_buf[127];
+extern volatile int shared_buf[1024];
+extern volatile int analog_buf_ready;
+extern volatile int analog_buf_cnt;
+extern unsigned int analog_buf_card;
+extern unsigned int analog_buf_channel;
+extern volatile unsigned short samples_dropped;
+extern volatile struct timeval cur_time;
+extern volatile struct timeval cur_time_sw;
+extern volatile u8 ext_sync;
+extern volatile u8 have;
+extern u8 cur_sample_diff;
+extern int omapl138EthSendPacket(u8 *buf,u16 len);
+extern int asn_parse(u8 **buf,int *bytes_left, u8 *tag);
+
+extern u8 bus_an_samples_neg[MAX_AN_CARDS][4];
+enum arg_type { ARG_TYPE_BOOL = 0, ARG_TYPE_TEXT = 1, ARG_TYPE_DOUBLE = 2, ARG_TYPE_LONG = 3 };
+
+struct timeval
+{
+    u32	tv_sec; 	/* seconds 			*/
+	u32	tv_usec;	/* and microseconds */
+};
+
+struct parsed_cfg_transport_line
+{
+	char name[32];
+	enum arg_type type;
+	char text_val[256];
+	double double_val;
+	long int long_val;
+	unsigned char bool_val;
+};
+
+struct klapacz_config
+{
+	unsigned int interval1;
+	unsigned int interval2;
+};
+
+struct device_config
+{
+	unsigned char mwd_ac_mask[MAX_OUT_CARDS];
+	unsigned int bits;
+};
+
+extern struct device_config dev_cfg;
+
+
+struct config_lookup_table
+{
+	char name[32];
+	enum arg_type type;
+	void *addr;
+	unsigned char size;
+	unsigned char bit_mask;
+	unsigned char flags;
+};
+
+#define CFG_BIT_KLAPACZ_ENABLED		(1<<4)
+
+extern struct klapacz_config klap_cfg;
+
+/* CPU registers */
+#define SET_RIS_TRIG67 	 *((volatile int*)0x01E2609C)
+#define SET_RIS_TRIG8	 *((volatile int*)0x01E260C4)
+#define INTSTAT67		 *((volatile int*)0x01E260AC)
+
+#define PINMUX0			 *((volatile int*)0x01C14120)
+#define PINMUX1			 *((volatile int*)0x01C14124)
+#define PINMUX2			 *((volatile int*)0x01C14128)
+#define PINMUX3			 *((volatile int*)0x01C1412C)
+#define PINMUX7			 *((volatile int*)0x01C1413C)
+#define DIR8			 *((volatile int*)0x01E260B0)
+#define SETDATA8		 *((volatile int*)0x01E260B8)
+#define CLRDATA8		 *((volatile int*)0x01E260BC)
+#define SPIGCR0 		 *((volatile int*)0x01C41000)
+#define SPIGCR1 		 *((volatile int*)0x01C41004)
+#define SPIPC0	 		 *((volatile int*)0x01C41014)
+#define SPIDAT0			 *((volatile int*)0x01C41038)
+#define SPIDAT1			 *((volatile int*)0x01C4103C)
+#define SPIFMT0			 *((volatile int*)0x01C41050)
+#define SPIGCR1			 *((volatile int*)0x01C41004)
+#define SPIINT0			 *((volatile int*)0x01C41008)
+#define SPILVL			 *((volatile int*)0x01C4100C)
+#define SPIBUF			 *((volatile int*)0x01C41040)
+#define SPIFLG			 *((volatile int*)0x01C41010)
+
+#define DIR01			 *((volatile int*)0x01E26010)
+#define IN_DATA01		 *((volatile int*)0x01E26020)
+
+#define PUPD_ENA		 *((volatile int*)0x01E2C00C)
+#define PUPD_SEL		 *((volatile int*)0x01E2C010)
+
+#define KICK0R			 *((volatile int*)0x01C14038)
+#define KICK1R			 *((volatile int*)0x01C1403C)
+
+#define KICK0R_VAL		 0x83E70B13
+#define KICK1R_VAL		 0x95A4F1E0
+
+#define	PINMUX3_3_0 	 0x0000000F
+#define	PINMUX3_11_8 	 0x00000F00
+#define	PINMUX3_15_12 	 0x0000F000
+#define	PINMUX3_19_16 	 0x000F0000
+#define PINMUX3_31_28    0xF0000000
+
+
+// PSC
+#define PTCMD 	*((volatile int*)0x01C10120)
+#define PTSTAT	*((volatile int*)0x01C10128)
+#define MDCTL4	*((volatile int*)0x01C10A10)
+#define MDSTAT4 *((volatile int*)0x01C10810)
+#define MDSTAT10 *((volatile int*)0x01E27828)
+
+extern Semaphore_Handle spi_semaphore;
+
+extern volatile int was_irq;
+extern u16 bus_an_cur_timestamp;
+extern u8 bus_an_cur_sample_num_xkhz;
+extern u16 tstamp_khz;
+
+struct an_card
+{
+	short l1;
+	short l2;
+	short l3;
+	short l4;
+};
+
+//mux
+#define C37_MUX_BUFSIZE			256
+
+//mux bits
+#define MUX_REG_CHAN_NUM_OFFSET		12
+#define MUX_REG_EXT_CLK				(1<<11)
+#define MUX_REG_WR					(1<<10)
+#define MUX_REG_SKIP_FF				(1<<9)
+#define MUX_REG_TX_BYTES_MASK		0x00FF
+
+//
+#define MUX_STATE_ERR				(1<<15)
+#define MUX_STATE_ERR_CNT_MASK		0x7E00
+#define MUX_STATE_ERR_CNT_OFFSET	9
+#define MUX_STATE_RX_BYTES_MASK		0x00FF
+#define MUX_STATE_YELLOW_BIT_IN		(1<<14)
+
+#define YEAR0           1900                    /* the first year */
+#define EPOCH_YR        1970            /* EPOCH = Jan 1 1970 00:00:00 */
+#define SECS_DAY        (24L * 60L * 60L)
+#define LEAPYEAR(year)  (!((year) % 4) && (((year) % 100) || !((year) % 400)))
+#define YEARSIZE(year)  (LEAPYEAR(year) ? 366 : 365)
+#define FIRSTSUNDAY(timp)       (((timp)->tm_yday - (timp)->tm_wday + 420) % 7)
+#define FIRSTDAYOF(timp)        (((timp)->tm_wday - (timp)->tm_yday + 420) % 7)
+#define TIME_MAX        ULONG_MAX
+#define ABB_LEN         3
+
+struct time_data
+{
+	uint8_t hour;
+	uint8_t min;
+	uint8_t sec;
+	uint8_t day;
+	uint8_t month;
+	uint8_t year;
+	uint32_t secs;
+	uint8_t fix_sat;
+};
+
+struct in_cards
+{
+	struct an_card an_in[MAX_AN_CARDS];
+	unsigned char bin_in[MAX_BIN_CARDS];
+   	unsigned short out_set[MAX_OUT_CARDS];
+	unsigned char bin_ac_mask[MAX_BIN_CARDS];
+	unsigned short unused[32];
+	struct an_card an_offset[MAX_AN_CARDS];
+	unsigned short reverse_curr;
+	unsigned short kob_an;
+	unsigned short kob_bin;
+	unsigned short kob_out;
+	unsigned short an_errs;
+	unsigned short bin_errs;
+	unsigned short out_errs;
+	unsigned short valid_an_samples;
+	unsigned short sample_no;
+	unsigned short spi_reg;
+	signed short delta_period_50M; 			//202
+	signed short phase_corr; 				//203
+	unsigned short sync_reg;				//204   //	bit15-synced pps, 14-synced irig, 13-4kHz imp   0-neg out pps
+	unsigned short fpga_verl;
+	unsigned short fpga_verh;
+	unsigned short sample_sync_no;
+	unsigned short mux_reg;
+	unsigned short mux_state;
+	unsigned short mux2_reg;
+	unsigned short mux2_state;
+	unsigned char mux_shift;
+	unsigned char mux2_shift;
+	unsigned short irigb_p[10];
+	unsigned short eof;
+	unsigned char bin_in_ench[MAX_BIN_CARDS];
+	unsigned char bin_ac_mask_ench[MAX_BIN_CARDS];
+	unsigned short mwd32_present;
+	unsigned short padding[800-512-16-1];
+	unsigned char mux_indata[C37_MUX_BUFSIZE];
+	unsigned char mux_outdata[C37_MUX_BUFSIZE];
+	unsigned char mux2_indata[C37_MUX_BUFSIZE];
+	unsigned char mux2_outdata[C37_MUX_BUFSIZE];
+	unsigned char spi_frame[2048];
+};
+
+// sync reg
+#define PPS_SYNCED		0x8000
+#define IRIGB_SYNCED	0x4000
+#define NEG_PPS_IN		0x0002
+#define NEG_PPS_OUT		0x0004
+#define MKI_PPS_IN		0x0008
+
+struct time_data irigb_process_frame();
+
+extern volatile u32 timesync_method;
+extern volatile u32 timesync_bits;
+extern volatile u16 pps3_timeout_cnt;
+
+extern volatile u16 kob_bin_ench;
+extern volatile u16 mwd32_mask;
+
+#define SYNC_METHOD_MGB				0x00 // standardowo czas z MGB + PPS
+#define SYNC_METHOD_MKI				0x01 // MGB + MKI4 + PPS
+#define SYNC_METHOD_MKI_PTP			0x02 // MKI7 + PPS
+#define SYNC_METHOD_IEC103			0x03 // IEC103
+#define SYNC_METHOD_IRIG_B_ZPRAE	0x04 // IRIG_B Proto ZPrAE
+#define	SYNC_METHOD_IRIG_B			0x05 // IRIG_B
+#define SYNC_METHOD_ZP6				0x06 // ZP6 z uwzglednieniem milisekund
+#define SYNC_METHOD_MLB				0x07 // ZP6 z uwzglednieniem milisekund, nie przyjmowanie od MGB czasu
+#define SYNC_METHOD_CUSTOM			0xFF
+
+
+#define CFG_TSYNC_ACCEPT_FROM_MGB			(1<<0)
+#define CFG_TSYNC_ACCEPT_FROM_ETH_AND_RS	(1<<1)
+#define CFG_TSYNC_ACCEPT_IEC103				(1<<2)
+#define CFG_TSYNC_FROM_DSP					(1<<3)
+#define CFG_TSYNC_USE_PPS					(1<<4)
+#define CFG_TSYNC_USE_SWPPS					(1<<6)
+#define CFG_TSYNC_USE_SWCLK					(1<<7)
+
+struct debug_info
+{
+	u32 tick_period;
+	u32 logman_cycle_time;
+	u32 logman_cycle_time_max;
+	u32 logman_buf_size_cur;
+	u32 logman_buf_capacity;
+	u32 irq_time;
+	u32 logman_cycle_period;
+	u32 logman_cycle_period_max;
+	volatile u32 temp_dbg;
+	short delta_period;
+	short phase_corr;
+	unsigned short sync_reg;
+	unsigned short max_elements;
+	unsigned short used_elements;
+	unsigned short nets_bufsize;
+}__attribute__((__packed__));
+
+extern struct debug_info dbg;
+
+// spi reg
+#define SPI_GOT_FRAME		0x01
+#define SPI_ALLOW_FRAME_N	0x01
+#define SPI_ANSWER_READY	0x02
+#define SPI_NEW_EVENTS		0x04
+
+extern volatile struct in_cards *ic;
+extern void reload_ic_cfg();
+extern void ms_hook();
+extern void analog_inputs_init();
+
+#define PI 3.14159265
+
+#define CKSUM_IV	0xAB	/* config cksum init vector */
+extern u8 mod256_cksum(uint8_t *buf, u32 len);
+extern u8 bus_an_cur_sample_num_3khz;
+extern u8 bus_an_cur_sample_num;
+extern u16 bus_an_samples_buf[MAX_AN_CARDS][4][SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2];
+extern u16 bus_out_data[MAX_OUT_CARDS];
+extern u8 bus_bin_data[MAX_BIN_CARDS];
+extern u16 force_bus_out_data[MAX_OUT_CARDS];
+extern u8 force_bus_bin_data[MAX_BIN_CARDS];
+extern u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
+extern u16 bus_out_data_test[MAX_OUT_CARDS];
+
+extern u8 bus_bin_data_ench[MAX_BIN_CARDS];
+extern u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
+
+extern Swi_Handle swi_notify;
+
+#define PWM1_SET(x,y) *((volatile uint16_t*)x) = y
+#define PWM1_GET(x) *((volatile uint16_t*)x)
+
+#define PWM1_BEG 0x01F02000
+#define PWM1_TBCTL 0x01F02000
+#define PWM1_TBCNT 0x01F02008
+#define PWM1_TBPRD 0x01F0200A
+#define PWM1_CMPA 0x01F02012
+#define PWM1_CMPB 0x01F02014
+#define PWM1_AQCTLA 0x01F02016
+#define PWM1_ETSEL 0x01F02032
+#define PWM1_ETPS 0x01F02034
+#define PWM1_ETCLR 0x01F02038
+#define PWM1_ETFRC 0x01F0203A
+
+#endif /* MISC_H_ */
diff --git a/src/omapl138_eth_driver.h b/src/omapl138_eth_driver.h
new file mode 100644
index 0000000..0ab98e2
--- /dev/null
+++ b/src/omapl138_eth_driver.h
@@ -0,0 +1,353 @@
+/**
+ * @file omapl138_eth_driver.h
+ * @brief OMAP-L138 Ethernet MAC controller
+ *
+ * @section License
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
+ *
+ * This file is part of CycloneTCP Open.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * @author Oryx Embedded SARL (www.oryx-embedded.com)
+ * @version 1.9.6
+ **/
+
+#ifndef _OMAPL138_ETH_DRIVER_H
+#define _OMAPL138_ETH_DRIVER_H
+
+//Dependencies
+//#include "core/nic.h"
+#include "soc_OMAPL138.h"
+
+//Number of TX buffers
+#ifndef OMAPL138_ETH_TX_BUFFER_COUNT
+   #define OMAPL138_ETH_TX_BUFFER_COUNT 8
+#elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1)
+   #error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid
+#endif
+
+//TX buffer size
+#ifndef OMAPL138_ETH_TX_BUFFER_SIZE
+   #define OMAPL138_ETH_TX_BUFFER_SIZE 1536
+#elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536)
+   #error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid
+#endif
+
+//Number of RX buffers
+#ifndef OMAPL138_ETH_RX_BUFFER_COUNT
+   #define OMAPL138_ETH_RX_BUFFER_COUNT 8
+#elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1)
+   #error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid
+#endif
+
+//RX buffer size
+#ifndef OMAPL138_ETH_RX_BUFFER_SIZE
+   #define OMAPL138_ETH_RX_BUFFER_SIZE 1536
+#elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536)
+   #error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid
+#endif
+
+//Channel number for the TX interrupt
+#ifndef OMAPL138_ETH_TX_IRQ_CHANNEL
+   #define OMAPL138_ETH_TX_IRQ_CHANNEL 3
+#elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31)
+   #error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid
+#endif
+
+//Channel number for the RX interrupt
+#ifndef OMAPL138_ETH_RX_IRQ_CHANNEL
+   #define OMAPL138_ETH_RX_IRQ_CHANNEL 3
+#elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31)
+   #error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid
+#endif
+
+//EMAC cores
+#define EMAC_CORE0 0
+#define EMAC_CORE1 1
+#define EMAC_CORE2 2
+
+//EMAC channels
+#define EMAC_CH0 0
+#define EMAC_CH1 1
+#define EMAC_CH2 2
+#define EMAC_CH3 3
+#define EMAC_CH4 4
+#define EMAC_CH5 5
+#define EMAC_CH6 6
+#define EMAC_CH7 7
+
+//SYSCFG0 registers
+#define SYSCFG0_PINMUX_R(n)         HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
+#define SYSCFG0_CFGCHIP3_R          HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
+
+//EMAC registers
+#define EMAC_TXREVID_R              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID)
+#define EMAC_TXCONTROL_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL)
+#define EMAC_TXTEARDOWN_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN)
+#define EMAC_RXREVID_R              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID)
+#define EMAC_RXCONTROL_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL)
+#define EMAC_RXTEARDOWN_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN)
+#define EMAC_TXINTSTATRAW_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW)
+#define EMAC_TXINTSTATMASKED_R      HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED)
+#define EMAC_TXINTMASKSET_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET)
+#define EMAC_TXINTMASKCLEAR_R       HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR)
+#define EMAC_MACINVECTOR_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR)
+#define EMAC_MACEOIVECTOR_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR)
+#define EMAC_RXINTSTATRAW_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW)
+#define EMAC_RXINTSTATMASKED_R      HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED)
+#define EMAC_RXINTMASKSET_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET)
+#define EMAC_RXINTMASKCLEAR_R       HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR)
+#define EMAC_MACINTSTATRAW_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW)
+#define EMAC_MACINTSTATMASKED_R     HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED)
+#define EMAC_MACINTMASKSET_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET)
+#define EMAC_MACINTMASKCLEAR_R      HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR)
+#define EMAC_RXMBPENABLE_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE)
+#define EMAC_RXUNICASTSET_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET)
+#define EMAC_RXUNICASTCLEAR_R       HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR)
+#define EMAC_RXMAXLEN_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN)
+#define EMAC_RXBUFFEROFFSET_R       HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET)
+#define EMAC_RXFILTERLOWTHRESH_R    HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH)
+#define EMAC_RXFLOWTHRESH_R(n)      HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n))
+#define EMAC_RXFREEBUFFER_R(n)      HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n))
+#define EMAC_MACCONTROL_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL)
+#define EMAC_MACSTATUS_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS)
+#define EMAC_EMCONTROL_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL)
+#define EMAC_FIFOCONTROL_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL)
+#define EMAC_MACCONFIG_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG)
+#define EMAC_SOFTRESET_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET)
+#define EMAC_MACSRCADDRLO_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO)
+#define EMAC_MACSRCADDRHI_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI)
+#define EMAC_MACHASH1_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1)
+#define EMAC_MACHASH2_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2)
+#define EMAC_BOFFTEST_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST)
+#define EMAC_TPACETEST_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST)
+#define EMAC_RXPAUSE_R              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE)
+#define EMAC_TXPAUSE_R              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE)
+#define EMAC_RXGOODFRAMES_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES)
+#define EMAC_RXBCASTFRAMES_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES)
+#define EMAC_RXMCASTFRAMES_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES)
+#define EMAC_RXPAUSEFRAMES_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES)
+#define EMAC_RXCRCERRORS_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS)
+#define EMAC_RXALIGNCODEERRORS_R    HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED)
+#define EMAC_RXJABBER_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER)
+#define EMAC_RXUNDERSIZED_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED)
+#define EMAC_RXFRAGMENTS_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS)
+#define EMAC_RXFILTERED_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED)
+#define EMAC_RXQOSFILTERED_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED)
+#define EMAC_RXOCTETS_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS)
+#define EMAC_TXGOODFRAMES_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES)
+#define EMAC_TXBCASTFRAMES_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES)
+#define EMAC_TXMCASTFRAMES_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES)
+#define EMAC_TXPAUSEFRAMES_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES)
+#define EMAC_TXDEFERRED_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED)
+#define EMAC_TXCOLLISION_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION)
+#define EMAC_TXSINGLECOLL_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL)
+#define EMAC_TXMULTICOLL_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL)
+#define EMAC_TXEXCESSIVECOLL_R      HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL)
+#define EMAC_TXLATECOLL_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL)
+#define EMAC_TXUNDERRUN_R           HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN)
+#define EMAC_TXCARRIERSENSE_R       HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE)
+#define EMAC_TXOCTETS_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS)
+#define EMAC_FRAME64_R              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64)
+#define EMAC_FRAME65T127_R          HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127)
+#define EMAC_FRAME128T255_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255)
+#define EMAC_FRAME256T511_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511)
+#define EMAC_FRAME512T1023_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023)
+#define EMAC_FRAME1024TUP_R         HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP)
+#define EMAC_NETOCTETS_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS)
+#define EMAC_RXSOFOVERRUNS_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS)
+#define EMAC_RXMOFOVERRUNS_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS)
+#define EMAC_RXDMAOVERRUNS_R        HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS)
+#define EMAC_MACADDRLO_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO)
+#define EMAC_MACADDRHI_R            HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI)
+#define EMAC_MACINDEX_R             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX)
+#define EMAC_TXHDP_R(n)             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n))
+#define EMAC_RXHDP_R(n)             HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n))
+#define EMAC_TXCP_R(n)              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n))
+#define EMAC_RXCP_R(n)              HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n))
+
+//EMAC control registers
+#define EMAC_CTRL_REVID_R           HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID)
+#define EMAC_CTRL_SOFTRESET_R       HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET)
+#define EMAC_CTRL_INTCONTRO_R       HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL)
+#define EMAC_CTRL_C0RXTHRESHEN_R    HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN)
+#define EMAC_CTRL_CnRXEN_R(n)       HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n))
+#define EMAC_CTRL_CnTXEN_R(n)       HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n))
+#define EMAC_CTRL_CnMISCEN_R(n)     HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n))
+#define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n))
+#define EMAC_CTRL_C0RXTHRESHSTAT_R  HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT)
+#define EMAC_CTRL_C0RXSTAT_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT)
+#define EMAC_CTRL_C0TXSTAT_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT)
+#define EMAC_CTRL_C0MISCSTAT_R      HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT)
+#define EMAC_CTRL_C1RXTHRESHSTAT_R  HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
+#define EMAC_CTRL_C1RXSTAT_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXSTAT)
+#define EMAC_CTRL_C1TXSTAT_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT)
+#define EMAC_CTRL_C1MISCSTAT_R      HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT)
+#define EMAC_CTRL_C2RXTHRESHSTAT_R  HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT)
+#define EMAC_CTRL_C2RXSTAT_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT)
+#define EMAC_CTRL_C2TXSTAT_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT)
+#define EMAC_CTRL_C2MISCSTAT_R      HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT)
+#define EMAC_CTRL_C0RXIMAX_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX)
+#define EMAC_CTRL_C0TXIMAX_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX)
+#define EMAC_CTRL_C1RXIMAX_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX)
+#define EMAC_CTRL_C1TXIMAX_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX)
+#define EMAC_CTRL_C2RXIMAX_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX)
+#define EMAC_CTRL_C2TXIMAX_R        HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX)
+
+//MDIO registers
+#define MDIO_REVID_R                HWREG(SOC_MDIO_0_REGS + MDIO_REVID)
+#define MDIO_CONTROL_R              HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL)
+#define MDIO_ALIVE_R                HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE)
+#define MDIO_LINK_R                 HWREG(SOC_MDIO_0_REGS + MDIO_LINK)
+#define MDIO_LINKINTRAW_R           HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW)
+#define MDIO_LINKINTMASKED_R        HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED)
+#define MDIO_USERINTRAW_R           HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW)
+#define MDIO_USERINTMASKED_R        HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED)
+#define MDIO_USERINTMASKSET_R       HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET)
+#define MDIO_USERINTMASKCLEAR_R     HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR)
+#define MDIO_USERACCESS0_R          HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0)
+#define MDIO_USERPHYSEL0_R          HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0)
+#define MDIO_USERACCESS1_R          HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1)
+#define MDIO_USERPHYSEL1_R          HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1)
+
+//MACEOIVECTOR register
+#define EMAC_MACEOIVECTOR_C0RXTHRESH    0x00000000
+#define EMAC_MACEOIVECTOR_C0RX          0x00000001
+#define EMAC_MACEOIVECTOR_C0TX          0x00000002
+#define EMAC_MACEOIVECTOR_C0MISC        0x00000003
+#define EMAC_MACEOIVECTOR_C1RXTHRESH    0x00000004
+#define EMAC_MACEOIVECTOR_C1RX          0x00000005
+#define EMAC_MACEOIVECTOR_C1TX          0x00000006
+#define EMAC_MACEOIVECTOR_C1MISC        0x00000007
+#define EMAC_MACEOIVECTOR_C2RXTHRESH    0x00000008
+#define EMAC_MACEOIVECTOR_C2RX          0x00000009
+#define EMAC_MACEOIVECTOR_C2TX          0x0000000A
+#define EMAC_MACEOIVECTOR_C2MISC        0x0000000B
+
+//TX buffer descriptor flags
+#define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
+#define EMAC_TX_WORD1_BUFFER_POINTER    0xFFFFFFFF
+#define EMAC_TX_WORD2_BUFFER_OFFSET     0xFFFF0000
+#define EMAC_TX_WORD2_BUFFER_LENGTH     0x0000FFFF
+#define EMAC_TX_WORD3_SOP               0x80000000
+#define EMAC_TX_WORD3_EOP               0x40000000
+#define EMAC_TX_WORD3_OWNER             0x20000000
+#define EMAC_TX_WORD3_EOQ               0x10000000
+#define EMAC_TX_WORD3_TDOWNCMPLT        0x08000000
+#define EMAC_TX_WORD3_PASSCRC           0x04000000
+#define EMAC_TX_WORD3_PACKET_LENGTH     0x0000FFFF
+
+//RX buffer descriptor flags
+#define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
+#define EMAC_RX_WORD1_BUFFER_POINTER    0xFFFFFFFF
+#define EMAC_RX_WORD2_BUFFER_OFFSET     0x07FF0000
+#define EMAC_RX_WORD2_BUFFER_LENGTH     0x000007FF
+#define EMAC_RX_WORD3_SOP               0x80000000
+#define EMAC_RX_WORD3_EOP               0x40000000
+#define EMAC_RX_WORD3_OWNER             0x20000000
+#define EMAC_RX_WORD3_EOQ               0x10000000
+#define EMAC_RX_WORD3_TDOWNCMPLT        0x08000000
+#define EMAC_RX_WORD3_PASSCRC           0x04000000
+#define EMAC_RX_WORD3_ERROR_MASK        0x03FF0000
+#define EMAC_RX_WORD3_JABBER            0x02000000
+#define EMAC_RX_WORD3_OVERSIZE          0x01000000
+#define EMAC_RX_WORD3_FRAGMENT          0x00800000
+#define EMAC_RX_WORD3_UNDERSIZED        0x00400000
+#define EMAC_RX_WORD3_CONTROL           0x00200000
+#define EMAC_RX_WORD3_OVERRUN           0x00100000
+#define EMAC_RX_WORD3_CODEERROR         0x00080000
+#define EMAC_RX_WORD3_ALIGNERROR        0x00040000
+#define EMAC_RX_WORD3_CRCERROR          0x00020000
+#define EMAC_RX_WORD3_NOMATCH           0x00010000
+#define EMAC_RX_WORD3_PACKET_LENGTH     0x0000FFFF
+
+//C++ guard
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief TX buffer descriptor
+ **/
+
+typedef struct _Omapl138TxBufferDesc
+{
+   uint32_t word0;
+   uint32_t word1;
+   uint32_t word2;
+   uint32_t word3;
+   struct _Omapl138TxBufferDesc *next;
+   struct _Omapl138TxBufferDesc *prev;
+} Omapl138TxBufferDesc;
+
+
+/**
+ * @brief RX buffer descriptor
+ **/
+
+typedef struct _Omapl138RxBufferDesc
+{
+   uint32_t word0;
+   uint32_t word1;
+   uint32_t word2;
+   uint32_t word3;
+   struct _Omapl138RxBufferDesc *next;
+   struct _Omapl138RxBufferDesc *prev;
+} Omapl138RxBufferDesc;
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+
+//AM335x Ethernet MAC driver
+//extern const NicDriver omapl138EthDriver;
+
+//AM335x Ethernet MAC related functions
+/*error_t omapl138EthInit(NetInterface *interface);
+void omapl138EthInitGpio(NetInterface *interface);
+void omapl138EthInitBufferDesc(NetInterface *interface);
+
+void omapl138EthTick(NetInterface *interface);
+
+void omapl138EthEnableIrq(NetInterface *interface);
+void omapl138EthDisableIrq(NetInterface *interface);
+void omapl138EthTxIrqHandler(void);
+void omapl138EthRxIrqHandler(void);
+void omapl138EthEventHandler(NetInterface *interface);
+
+error_t omapl138EthSendPacket(NetInterface *interface,
+   const NetBuffer *buffer, size_t offset);
+
+error_t omapl138EthReceivePacket(NetInterface *interface);
+
+error_t omapl138EthUpdateMacAddrFilter(NetInterface *interface);
+error_t omapl138EthUpdateMacConfig(NetInterface *interface);
+*/
+void omapl138EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
+   uint8_t regAddr, uint16_t data);
+
+uint16_t omapl138EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
+   uint8_t regAddr);
+
+//C++ guard
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/psc.c b/src/psc.c
new file mode 100644
index 0000000..4053a54
--- /dev/null
+++ b/src/psc.c
@@ -0,0 +1,114 @@
+/**
+ * \file      psc.c
+ *
+ * \brief     This file contains the device abstraction layer APIs for the
+ *            PSC module. There are APIs here to enable power domain, 
+ *            transitions for a particular module
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/* HW Macros */
+#include "hw_types.h"
+
+/* DSP System Defines */
+#include "hw_psc_OMAPL138.h"
+
+/**************************************************************************
+  API FUNCTION DEFINITIONS
+***************************************************************************/
+
+/**
+ *
+ *  \brief   This function sets the requested module in the required state
+ *
+ * \param     baseAdd         Memory address of the PSC instance used.
+ * \param     moduleId        The module number of the module to be commanded.
+ * \param     powerDomain     The power domain of the module to be commanded.
+ * \param     flags           This contains the flags that is a logical OR of
+ *                            the commands that can be given to a module.
+ *
+ * \return                    0 in case of successful transition, -1 otherwise.
+ *            
+ */
+
+int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
+                         unsigned int powerDomain, unsigned int flags)
+{
+    volatile unsigned int timeout = 0xFFFFFF;
+    int    retVal = 0;
+    unsigned int    status = 0;
+
+    HWREG(baseAdd +  PSC_MDCTL(moduleId)) = (flags & PSC_MDCTL_NEXT);
+
+    if (powerDomain == 0)
+    {
+        HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO0;
+    }
+    else
+    {
+        HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO1;
+    }
+
+    if (powerDomain == 0)
+    {
+        do {
+            status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT0;
+        } while (status && timeout--);
+    }
+    else
+    {
+        do {
+            status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
+        } while (status && timeout--);
+    }
+
+    if (timeout != 0)
+    {
+        timeout = 0xFFFFFF;
+        status = flags & PSC_MDCTL_NEXT; 
+        do {
+            timeout--;
+        } while(timeout && 
+                (HWREG(baseAdd + PSC_MDSTAT(moduleId)) & PSC_MDSTAT_STATE) != status);
+    }
+
+    if (timeout == 0)
+    {
+        retVal = -1;
+    }
+
+    return retVal;
+}
diff --git a/src/psc.h b/src/psc.h
new file mode 100644
index 0000000..e33497d
--- /dev/null
+++ b/src/psc.h
@@ -0,0 +1,69 @@
+/**
+ *  \file  psc.h
+ *
+ *  \brief This file contains the function prototypes for the device abstraction 
+ *         layer for PSC. It also contains some related macro definitions and some 
+ *         files to be included.
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+#ifndef _PSC_H
+#define _PSC_H
+
+#if defined c6748
+#include "hw_psc_C6748.h"
+#elif defined omapl138
+#include "hw_psc_OMAPL138.h"
+#else
+#include "hw_psc_AM1808.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
+                      unsigned int powerDomain, unsigned int flags);
+
+extern void USBModuleClkEnable(unsigned int ulIndex, unsigned int ulBase);
+extern void USBModuleClkDisable(unsigned int ulIndex, unsigned int ulBase);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
diff --git a/src/soc_OMAPL138.h b/src/soc_OMAPL138.h
new file mode 100644
index 0000000..a123620
--- /dev/null
+++ b/src/soc_OMAPL138.h
@@ -0,0 +1,595 @@
+/**
+ * \file  soc_OMAPL138.h
+ *
+ * \brief This file contains the peripheral information for OMAPL138 SOC
+ */
+
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+#ifndef _SOC_OMAPL138_H_
+#define _SOC_OMAPL138_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+**                      PERIPHERAL INSTANCE COUNT
+******************************************************************************/
+
+/** \brief Number of UPP  instances                                           */
+#define SOC_UPP_PER_CNT                     1
+
+/** \brief Number of UHPI instances                                           */
+#define SOC_HPI_PER_CNT                     1
+
+/** \brief Number of McASP instances                                          */
+#define SOC_MCASP_PER_CNT                   1
+
+/** \brief Number of TIMER instances                                          */
+#define SOC_TMR_PER_CNT                     4
+
+/** \brief Number of PSC instances                                            */
+#define SOC_PSC_PER_CNT                     2
+
+/** \brief Number of UART instances                                           */
+#define SOC_UART_PER_CNT                    3
+
+/** \brief Number of SPI instances                                            */
+#define SOC_SPI_PER_CNT                     2
+
+/** \brief Number of I2C instances                                            */
+#define SOC_I2C_PER_CNT                     2
+
+/** \brief Number of PLL instances                                            */
+#define SOC_PLLC_PER_CNT                    2
+
+/** \brief Number of MMCSD instances                                          */
+#define SOC_MMCSD_PER_CNT                   2
+
+/** \brief Number of LCDC instances                                           */
+#define SOC_LCDC_PER_CNT                    1
+
+/** \brief Number of Mcbsp instances                                          */
+#define SOC_MCBSP_PER_CNT                   2
+
+/** \brief Number of EDMA3 CC instances                                       */
+#define SOC_EDMA3CC_CNT                     2
+
+/** \brief Number of EDMA3 TC instances                                       */
+#define SOC_EDMA3TC_CNT                     3
+
+/** \brief Number of EMIFA instances                                          */
+#define SOC_EMIFA_PER_CNT                   1
+
+/** \brief Number of EMIFB instances                                          */
+#define SOC_EMIFB_PER_CNT                   1
+
+/** \brief Number of EMAC instances                                           */
+#define SOC_EMAC_PER_CNT                    1
+
+/** \brief Number of MDIO instances                                           */
+#define SOC_MDIO_PER_CNT                    1
+
+/** \brief Number of EHRPWM instances                                         */
+#define SOC_EHRPWM_PER_CNT                  2
+
+/** \brief Number of ECAP instances                                           */
+#define SOC_ECAP_PER_CNT                    3
+
+/** \brief Number of CPGMAC instances                                         */
+#define SOC_CPGMACSSR_PER_CNT               1
+
+/** \brief Number of CPPI instances                                           */
+#define SOC_CPPI_PER_CNT                    1
+
+/** \brief Number of USB instances                                            */
+#define SOC_USB_PER_CNT                     2
+
+/** \brief Number of VPIF instances                                           */
+#define SOC_VPIF_PER_CNT                    1
+
+/** \brief Number of INTC instances                                           */
+#define SOC_INTC_PER_CNT                    1
+
+/** \brief Number of AINTC instances                                          */
+#define SOC_AINTC_PER_CNT                   1
+
+/** \brief Number of SATA instances                                           */
+#define SOC_SATA_PER_CNT                    1
+
+/** \brief Number of RTC instances                                            */
+#define SOC_RTC_PER_CNT                     1
+
+/** \brief Number of GPIO instances                                           */
+#define SOC_GPIO_PER_CNT                    1
+
+/** \brief Number of SYSCFG instances                                         */
+#define SOC_SYSCFG_PER_CNT                  2
+/******************************************************************************
+**                      PERIPHERAL INSTANCE DEFINITIONS
+******************************************************************************/
+
+/** \brief Peripheral Instances of UHPI instances                             */
+#define SOC_HPI                             (0)
+
+/** \brief Peripheral Instances of McASP instances                            */
+#define SOC_MCASP_0                         (0)
+
+/** \brief Peripheral Instance of EDMA CC instances                           */
+#define SOC_EDMA3CC_0                       (0)
+#define SOC_EDMA3CC_1                       (1)
+
+/** \brief Peripheral Instance of EDMA TC instances                           */
+#define SOC_EDMA3TC_0                       (0)
+#define SOC_EDMA3TC_1                       (1)
+
+/** \brief Peripheral Instance of Timer 64 instances                          */
+#define SOC_TMR_0                           (0)
+#define SOC_TMR_1                           (1)
+#define SOC_TMR_2                           (2)
+#define SOC_TMR_3                           (3)
+
+/** \brief Peripheral Instances of PSC instances                              */
+#define SOC_PSC_0                           (0)
+#define SOC_PSC_1                           (1)
+
+/** \brief Peripheral Instances of UART instances                             */
+#define SOC_UART_0                          (0)
+#define SOC_UART_1                          (1)
+#define SOC_UART_2                          (2)
+
+/** \brief Peripheral Instances of SPI instances                              */
+#define SOC_SPI_0                           (0)
+#define SOC_SPI_1                           (1)
+
+/** \brief Peripheral Instances of I2C instances                              */
+#define SOC_I2C_0                           (0)
+#define SOC_I2C_1                           (1)
+
+/** \brief Peripheral Instances of MMCSD instances                            */
+#define SOC_MMCSD_0                         (0)
+#define SOC_MMCSD_1                         (1)
+
+/** \brief Peripheral Instances of LCDC instances                              */
+#define SOC_LCDC                            (0)
+
+/** \brief Instance number of PLL controller                                  */
+#define SOC_PLLC_0                          (0)
+#define SOC_PLLC_1                          (1)
+
+/** \brief Peripheral Instance of EMIFA instances                             */
+#define SOC_EMIFA                           (0)
+
+/** \brief Peripheral Instance of EMAC instances                              */
+#define SOC_EMAC                            (0)
+
+/** \brief Peripheral Instance of MDIO instances                              */
+#define SOC_MDIO                            (0)
+
+/** \brief Peripheral Instance of EHRPWM instances                            */
+#define SOC_EHRPWM_0                        (0)
+#define SOC_EHRPWM_1                        (1)
+
+/** \brief Peripheral Instance of ECAP instances                              */
+#define SOC_ECAP_0                          (0)
+#define SOC_ECAP_1                          (1)
+#define SOC_ECAP_2                          (2)
+
+/** \brief Peripheral Instance of USB instances                               */
+#define SOC_USB_0                           (0)
+#define SOC_USB_1                           (1)
+
+/** \brief Peripheral Instance of PRU CORE instances                          */
+#define SOC_PRUCORE_0                       (0)
+#define SOC_PRUCORE_1                       (1)
+
+/** \brief Peripheral Instance of PRUINTC instances                           */
+#define SOC_PRUINTC                         (0)
+
+/** \brief Peripheral Instances of VPIF instances                            */
+#define SOC_VPIF                            (0)
+
+/** \brief Peripheral Instance of INTC instances                              */
+#define SOC_INTC                            (0)
+
+/** \brief Peripheral Instance of AINTC instances                             */
+#define SOC_AINTC                           (0)
+
+/** \brief Peripheral Instance of RTC instances                               */
+#define SOC_RTC                             (0)
+
+/** \brief Peripheral Instance of GPIO instances                              */
+#define SOC_GPIO                            (0)
+/** \brief GPIO pin and bank information                                      */
+#define SOC_GPIO_NUM_PINS                   (144)
+#define SOC_GPIO_NUM_BANKS                  ((SOC_GPIO_NUM_PINS + 15)/16)
+
+/** \brief Peripheral Instance of ECTL instances                              */
+#define SOC_ECTL                            (0)
+
+/** \brief Peripheral Instance of SYSCFG instances                            */
+#define SOC_SYSCFG                          (2)
+
+/******************************************************************************
+**                      PERIPHERAL BASE ADDRESS
+******************************************************************************/
+
+/** \brief Base address of INTC memory mapped registers                       */
+#define SOC_INTC_0_REGS                     (0x01800000)
+
+/** \brief Base address of PDC memory mapped registers                        */
+#define SOC_PWRDWN_PDC_REGS                 (0x01810000)
+
+/** \brief Base address of SYS - Security ID register                         */
+#define SOC_SYS_0_SECURITY_ID_REGS          (0x01811000)
+
+/** \brief Base address of SYS - Revision ID register                         */
+#define SOC_SYS_0_REV_ID_REGS               (0x01812000)
+
+/** \brief IDMA Module memory mapped address  */
+#define SOC_IDMA_0_REGS                     (0x01820000)
+
+/** \brief EMC Module memory mapped address                                   */
+#define SOC_EMC_0_REGS                      (0x01820000)
+
+/** \brief Cache Module memory mapped address                                 */
+#define SOC_CACHE_0_REGS                    (0x01840000)
+
+/** \brief Base address of Channel controller  memory mapped registers        */
+#define SOC_EDMA30CC_0_REGS                 (0x01C00000)
+
+/** \brief Base address of Transfer controller  memory mapped registers       */
+#define SOC_EDMA30TC_0_REGS                 (0x01C08000)
+#define SOC_EDMA30TC_1_REGS                 (0x01C08400)
+
+/** \brief Base address of PSC memory mapped registers                        */
+#define SOC_PSC_0_REGS                      (0x01C10000)
+
+/** \brief PLL controller instance o module address                           */
+#define SOC_PLLC_0_REGS                     (0x01C11000)
+
+/** \brief Base address of DEV memory mapped registers                        */
+#define SOC_SYSCFG_0_REGS                   (0x01C14000)
+
+/** \brief Base address of TIMER memory mapped registers                      */
+#define SOC_TMR_0_REGS                      (0x01C20000)
+#define SOC_TMR_1_REGS                      (0x01C21000)
+
+/** \brief Base address of I2C memory mapped registers                        */
+#define SOC_I2C_0_REGS                      (0x01C22000)
+
+/** \brief Base address of RTC memory                                         */
+#define SOC_RTC_0_REGS                      (0x01C23000)
+
+/** \brief Base address of MMCSD memory mapped registers                      */
+#define SOC_MMCSD_0_REGS                    (0x01C40000)
+
+/** \brief Base address of SPI memory mapped registers                        */
+#define SOC_SPI_0_REGS                      (0x01C41000)
+
+/** \brief Base address of UART memory mapped registers                       */
+#define SOC_UART_0_REGS                     (0x01C42000)
+
+/** \brief Base address of McASP memory mapped registers                      */
+#define SOC_MCASP_0_CTRL_REGS               (0x01D00000)
+#define SOC_MCASP_0_FIFO_REGS               (0x01D01000)
+#define SOC_MCASP_0_DATA_REGS               (0x01D02000)
+
+/** \brief Base address of UART memory mapped registers                       */
+#define SOC_UART_1_REGS                     (0x01D0C000)
+#define SOC_UART_2_REGS                     (0x01D0D000)
+
+/** \brief Base address of McBSP memory mapped registers                      */
+#define SOC_MCBSP_0_CTRL_REGS               (0x01D10000)
+#define SOC_MCBSP_0_FIFO_REGS               (0x01D10800)
+#define SOC_MCBSP_0_DATA_REGS               (0x01F10000)
+
+/** \brief Base address of McASP memory mapped registers                      */
+#define SOC_MCBSP_1_CTRL_REGS               (0x01D11000)
+#define SOC_MCBSP_1_FIFO_REGS               (0x01D11800)
+#define SOC_MCBSP_1_DATA_REGS               (0x01F11000)
+
+#define SOC_MPU_0_REGS                      (0x01E14000)
+#define SOC_MPU_1_REGS                      (0x01E15000)
+
+/** \brief Base address of USB memory                                         */
+#define SOC_USB_0_REGS                      (0x01E00000)
+#define SOC_USB_1_REGS                      (0x01E25000)
+
+/** \brief Base address of HPI memory mapped registers                        */
+#define SOC_HPI_0_REGS                      (0x01E10000)
+
+/** \brief Base address of LCDC memory mapped registers                       */
+#define SOC_LCDC_0_REGS                     (0x01E13000)
+
+/** \brief Base address of UPP memory mapped registers                        */
+#define SOC_UPP_0_REGS                      (0x01E16000)
+
+/** \brief Base address of VPIF memory mapped registers                       */
+#define SOC_VPIF_0_REGS                     (0x01E17000)
+
+/** \brief Base address of SATA memory mapped registers                       */
+#define SOC_SATA_0_REGS                     (0x01E18000)
+
+/** \brief PLL controller instance 1 module address                           */
+#define SOC_PLLC_1_REGS                     (0X01E1A000)
+
+/** \brief Base address of MMCSD memory mapped registers                      */
+#define SOC_MMCSD_1_REGS                    (0x01E1B000)
+
+/** \brief Base address of EMAC memory                                        */
+#define SOC_EMAC_DSC_CTRL_MOD_RAM           (0x01E20000)
+#define SOC_EMAC_DSC_CTRL_MOD_REG           (0x01E22000)
+#define SOC_EMAC_DSC_CONTROL_REG            (0x01E23000)
+#define SOC_MDIO_0_REGS                     (0x01E24000)
+
+/** \brief Base address of PRU Core Regsiters                                 */
+#define SOC_PRUCORE_0_REGS                  (0x01C37000)
+#define SOC_PRUCORE_1_REGS                  (0x01C37800)
+
+/** \brief Base address of PRU Interrupt Controller Registers                 */
+#define SOC_PRUINTC_0_REGS                  (0x01C34000)
+
+/** \brief Base address of MUSB memmory mapped Registers                 */
+#define SOC_USB_0_BASE              		(0x01E00400)
+
+/** \brief Base address of  OTG  memmory mapped Registers                 */
+#define SOC_USB_0_OTG_BASE             		(0x01E00000)
+
+/** \brief USB 0 Phy regsister( CFGCHIP2 register) address				*/
+#define SOC_USB_0_PHY_REGS					(0x01C14184)
+
+/** \brief Base address of GPIO memory mapped registers                       */
+#define SOC_GPIO_0_REGS                     (0x01E26000)
+
+/** \brief Base address of PSC memory mapped registers                        */
+#define SOC_PSC_1_REGS                      (0x01E27000)
+
+/** \brief Base address of I2C memory mapped registers                        */
+#define SOC_I2C_1_REGS                      (0x01E28000)
+
+/** \brief Base address of syscfg registers                                   */
+#define SOC_SYSCFG_1_REGS                   (0x01E2C000)
+
+/** \brief Base address of Channel controller  memory mapped registers        */
+#define SOC_EDMA31CC_0_REGS                 (0x01E30000)
+
+/** \brief Base address of Transfer controller  memory mapped registers       */
+#define SOC_EDMA31TC_0_REGS                 (0x01E38000)
+
+/** \brief Base address of EPWM memory mapped registers                       */
+#define SOC_EHRPWM_0_REGS                   (0x01F00000)
+#define SOC_EHRPWM_1_REGS                   (0x01F02000)
+
+/** \brief Base address of EPWM memory mapped registers                       */
+#define SOC_HRPWM_0_REGS                    (0x01F01000)
+#define SOC_HRPWM_1_REGS                    (0x01F03000)
+
+/** \brief Base address of ECAP memory mapped registers                       */
+#define SOC_ECAP_0_REGS                     (0x01F06000)
+#define SOC_ECAP_1_REGS                     (0x01F07000)
+#define SOC_ECAP_2_REGS                     (0x01F08000)
+
+/** \brief Base address of TIMER memory mapped registers                      */
+#define SOC_TMR_2_REGS                      (0x01F0C000)
+#define SOC_TMR_3_REGS                      (0x01F0D000)
+
+/** \brief Base address of SPI memory mapped registers                        */
+#define SOC_SPI_1_REGS                      (0x01F0E000)
+
+/** \brief Base address of EMIFA memory mapped registers                      */
+#define SOC_EMIFA_0_REGS                    (0x68000000)
+
+/** \brief Base address of EMIFA_CS0 memory                                   */
+#define SOC_EMIFA_CS0_ADDR                  (0x40000000)
+
+/** \brief Base address of EMIFA_CS2 memory                                   */
+#define SOC_EMIFA_CS2_ADDR                  (0x60000000)
+
+/** \brief Base address of EMIFA_CS3 memory                                   */
+#define SOC_EMIFA_CS3_ADDR                  (0x62000000)
+
+/** \brief Base address of EMIFA_CS4 memory                                   */
+#define SOC_EMIFA_CS4_ADDR                  (0x64000000)
+
+/** \brief Base address of EMIFA_CS5 memory                                   */
+#define SOC_EMIFA_CS5_ADDR                  (0x66000000)
+
+/** \brief Base address of DDR memory mapped registers                        */
+#define SOC_DDR2_0_CTRL_REGS                (0xB0000000)
+#define SOC_DDR2_0_DATA_REGS                (0xC0000000)
+
+/** \brief Base address of AINTC memory mapped registers                      */
+#define SOC_AINTC_0_REGS                    (0xFFFEE000)
+
+/** \brief Base address of UMC Memory protection registers                    */
+#define SOC_MEMPROT_L2_REGS                 (0x00800000)
+
+/** \brief Base address of PMC memory Protection registers                    */
+#define SOC_MEMPROT_L1P_REGS                (0x00E00000)
+
+/** \brief Base address of DMC memory protection registers                    */
+#define SOC_MEMPROT_L1D_REGS                (0x00F00000)
+
+/******************************************************************************
+**                      EDMA RELATED DEFINITIONS
+******************************************************************************/
+
+/* Parameterizable Configuration: These are fed directly from the RTL
+ * parameters for the given SOC */
+
+#define SOC_EDMA3_NUM_DMACH                 32
+#define SOC_EDMA3_NUM_QDMACH                8
+#define SOC_EDMA3_NUM_PARAMSETS             128
+#define SOC_EDMA3_NUM_EVQUE                 2
+#define SOC_EDMA3_CHMAPEXIST                0
+#define SOC_EDMA3_NUM_REGIONS               4
+#define SOC_EDMA3_MEMPROTECT                0
+
+/******************************************************************************
+**                      CHANNEL INSTANCE COUNT
+******************************************************************************/
+#define SOC_EDMA3_CHA_CNT                   (SOC_EDMA3_NUM_DMACH + \
+                                             SOC_EDMA3_NUM_QDMACH)
+
+
+/* QDMA channels */
+#define    SOC_EDMA3_QCHA_BASE              SOC_EDMA3_NUM_DMACH         /* QDMA Channel Base */
+#define    SOC_EDMA3_QCHA_0                 (SOC_EDMA3_QCHA_BASE + 0)   /* QDMA Channel 0 */
+#define    SOC_EDMA3_QCHA_1                 (SOC_EDMA3_QCHA_BASE + 1)   /* QDMA Channel 1 */
+#define    SOC_EDMA3_QCHA_2                 (SOC_EDMA3_QCHA_BASE + 2)   /* QDMA Channel 2 */
+#define    SOC_EDMA3_QCHA_3                 (SOC_EDMA3_QCHA_BASE + 3)   /* QDMA Channel 3 */
+#define    SOC_EDMA3_QCHA_4                 (SOC_EDMA3_QCHA_BASE + 4)   /* QDMA Channel 4 */
+#define    SOC_EDMA3_QCHA_5                 (SOC_EDMA3_QCHA_BASE + 5)   /* QDMA Channel 5 */
+#define    SOC_EDMA3_QCHA_6                 (SOC_EDMA3_QCHA_BASE + 6)   /* QDMA Channel 6 */
+#define    SOC_EDMA3_QCHA_7                 (SOC_EDMA3_QCHA_BASE + 7)   /* QDMA Channel 7 */
+
+
+/* Enumerations for EDMA Controlleres */
+#define  SOC_EDMACC_ANY       -1 /* Any instance of EDMACC module*/
+#define  SOC_EDMACC_0          0 /* EDMACC Instance 0            */
+
+
+/* Enumerations for EDMA Event Queues */
+#define  SOC_EDMA3_QUE_0     0 /* Queue 0                     */
+#define  SOC_EDMA3_QUE_1     1 /* Queue 1                     */
+
+/* Enumerations for EDMA Transfer Controllers
+ *
+ * There are 2 Transfer Controllers. Typically a one to one mapping exists
+ * between Event Queues and Transfer Controllers. */
+#define  SOC_EDMATC_ANY  -1 /* Any instance of EDMATC                */
+#define  SOC_EDMATC_0    0  /* EDMATC Instance 0                     */
+#define  SOC_EDMATC_1    1  /* EDMATC Instance 1                     */
+
+
+#define SOC_EDMA3_REGION_GLOBAL            (-1)
+#define SOC_EDMA3_REGION_0                  0
+#define SOC_EDMA3_REGION_1                  1
+#define SOC_EDMA3_REGION_2                  2
+#define SOC_EDMA3_REGION_3                  3
+
+
+/******************************************************************************
+**                      DAT RELATED DEFINITIONS
+******************************************************************************/
+
+/* Parameterizable Configuration:- These are fed directly from the RTL
+ * parameters for the given SOC */
+
+ /******************************************************************************
+**                      CHANNEL INSTANCE COUNT
+******************************************************************************/
+/** \brief Number of Generic Channel instances                                */
+
+
+/** \brief Enumerations for EDMA channels
+ *
+ * There are 8 QDMA channels -
+ */
+
+#define    SOC_DAT_QCHA_0                   0 /**<   QDMA Channel 0           */
+#define    SOC_DAT_QCHA_1                   1 /**<   QDMA Channel 1           */
+#define    SOC_DAT_QCHA_2                   2 /**<   QDMA Channel 2           */
+#define    SOC_DAT_QCHA_3                   3 /**<   QDMA Channel 3           */
+#define    SOC_DAT_QCHA_4                   4 /**<   QDMA Channel 4           */
+#define    SOC_DAT_QCHA_5                   5 /**<   QDMA Channel 5           */
+#define    SOC_DAT_QCHA_6                   6 /**<   QDMA Channel 6           */
+#define    SOC_DAT_QCHA_7                   7 /**<   QDMA Channel 7           */
+
+/** \brief Enumerations for EDMA Event Queues
+*
+*  There are two Event Queues. Q0 is the highest priority and Q1 is the least
+*  priority
+*
+*/
+#define    SOC_DAT_PRI_DEFAULT    0 /* Queue 0 is default          */
+#define    SOC_DAT_PRI_0          0 /* Queue 0                     */
+#define    SOC_DAT_PRI_1          1 /* Queue 1                     */
+
+/** \brief Enumeration for EDMA Regions
+*
+*
+*/
+
+#define SOC_DAT_REGION_GLOBAL              (-1)       /* Global Region        */
+#define SOC_DAT_REGION_0                    0         /* EDMA Region 0        */
+#define SOC_DAT_REGION_1                    1         /* EDMA Region 1        */
+#define SOC_DAT_REGION_2                    2         /* EDMA Region 2        */
+#define SOC_DAT_REGION_3                    3         /* EDMA Region 3        */
+
+/** \brief Enumeration for peripheral frequencies
+*
+*
+*/
+
+#define SOC_SYSCLK_1_FREQ                   (300000000)
+#define SOC_SYSCLK_2_FREQ                   (SOC_SYSCLK_1_FREQ/2)
+#define SOC_SYSCLK_3_FREQ                   (SOC_SYSCLK_1_FREQ/3)
+#define SOC_SYSCLK_4_FREQ                   (SOC_SYSCLK_1_FREQ/4)
+
+#define SOC_ASYNC_2_FREQ                    (24000000)
+
+/** I2C      */
+#define SOC_I2C_0_MODULE_FREQ               (SOC_ASYNC_2_FREQ)
+#define SOC_I2C_1_MODULE_FREQ               (SOC_SYSCLK_4_FREQ)
+
+/** MCBSP    */
+#define SOC_MCBSP_0_MODULE_FREQ             (SOC_SYSCLK_2_FREQ)
+#define SOC_MCBSP_1_MODULE_FREQ             (SOC_SYSCLK_2_FREQ)
+
+/** LCDC     */
+#define SOC_LCDC_0_MODULE_FREQ              (SOC_SYSCLK_2_FREQ)
+
+/** SPI      */
+#define SOC_SPI_0_MODULE_FREQ               (SOC_SYSCLK_2_FREQ)
+#define SOC_SPI_1_MODULE_FREQ               (SOC_SYSCLK_2_FREQ)
+
+/** UART     */
+#define SOC_UART_0_MODULE_FREQ              (SOC_SYSCLK_2_FREQ)
+#define SOC_UART_1_MODULE_FREQ              (SOC_SYSCLK_2_FREQ)
+#define SOC_UART_2_MODULE_FREQ              (SOC_SYSCLK_2_FREQ)
+
+/** EHRPWM	*/
+#define SOC_EHRPWM_0_MODULE_FREQ	    (SOC_SYSCLK_2_FREQ)
+#define SOC_EHRPWM_1_MODULE_FREQ	    (SOC_SYSCLK_2_FREQ)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_OMAPL138_H_ */
diff --git a/src/spi.c b/src/spi.c
new file mode 100644
index 0000000..d7e4618
--- /dev/null
+++ b/src/spi.c
@@ -0,0 +1,198 @@
+/*
+ * spi.c
+ *
+ *  Created on: 19-12-2016
+ *      Author: K
+ */
+
+#include <ti/sysbios/hal/Timer.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Clock.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/MultiProc.h>
+#include <ti/ipc/MessageQ.h>
+#include <ti/ipc/Notify.h>
+
+#include "misc.h"
+#include "spi.h"
+#include "tdefs.h"
+#include "logic_elements/virt_in_drv.h"
+#include "logic_elements/leds_drv.h"
+#include "logic_elements/pkw.h"
+#include "logic_elements/cnt.h"
+#include "logic_elements/s_demux.h"
+#include "logic_elements/events_reg.h"
+#include "comm.h"
+
+u8 spi_fram_restored = 0;
+
+void spi_init()
+{
+	u32 psc;
+
+	PINMUX3=(PINMUX3 & ~(PINMUX3_3_0|PINMUX3_15_12|PINMUX3_11_8|PINMUX3_31_28)) | (1<<0) | (1<<12) | (1<<8) | (4<<28); // spi0 clk, mosi, miso, gp8_1 cs
+	DIR8&=~(1<<1); // GP8_1 as output
+
+	// enable psc
+	while(PTSTAT & 0x00000001);
+	MDCTL4=0x00000003;
+	PTCMD=0x00000001;
+
+	while(PTSTAT & 0x00000001);
+	while((MDSTAT4 & 0x0000003F) != 0x00000003);
+
+	SPI_DEASSERT();
+
+	SPIGCR0=0;
+	SPIGCR0=1;
+	SPIGCR1=0x00000003;
+	SPIPC0=0x00000E00;
+    SPIDAT1=0x04000000;
+
+    psc = 10;
+
+    SPIFMT0 = 0x00020008 | (psc << 8); //polarity 1
+    SPIGCR1 = 0x01000003;
+//    SPIINT0 = (1<<8); // RXINT
+//    SPILVL = (1<<8); // RXINT
+
+}
+
+
+void spi_putc_bl(u16 word)
+{
+	SPIDAT0=word;
+	while(!(SPIFLG & (1<<8)))
+		Task_sleep(1);
+	SPIFLG|=(1<<8);
+}
+
+void spi_wr_en_bl()
+{
+	SPI_ASSERT();
+	Task_sleep(1);
+	spi_putc_bl(0x06);
+	Task_sleep(1);
+	SPI_DEASSERT();
+	Task_sleep(1);
+}
+
+void spi_wr_buf_bl(u16 addr, u8 *buf, u16 len)
+{
+	u32 i;
+
+	spi_wr_en_bl();
+	SPI_ASSERT();
+	Task_sleep(1);
+	spi_putc_bl(0x02);
+	spi_putc_bl((addr & 0xFF00)>>8);
+	spi_putc_bl((addr & 0x00FF)>>0);
+	for(i=0;i<len;i++)
+		spi_putc_bl(buf[i]);
+	Task_sleep(1);
+	SPI_DEASSERT();
+}
+
+void spi_rd_buf_bl(u16 addr, u8 *buf, u16 len)
+{
+	u32 i;
+
+	SPI_ASSERT();
+	Task_sleep(1);
+	spi_putc_bl(0x03);
+	spi_putc_bl((addr & 0xFF00)>>8);
+	spi_putc_bl((addr & 0x00FF)>>0);
+	for(i=0;i<len;i++)
+	{
+		spi_putc_bl(0xFF);
+		buf[i]=SPIBUF&0xFF;
+	}
+	Task_sleep(1);
+	SPI_DEASSERT();
+}
+
+Void spiFxn(UArg a0, UArg a1)
+{
+	u8 buf[49+32+6+16+1];
+	u8 i;
+
+	spi_init();
+
+	spi_rd_buf_bl(0,buf,sizeof(buf));
+	if(buf[48+32+6+16+1]==(u8)(mod256_cksum(buf,sizeof(buf)-1)+CKSUM_IV))
+	{
+		virt_in_states=((u32)buf[3]<<24)|((u32)buf[2]<<16)|((u32)buf[1]<<8)|((u32)buf[0]<<0);
+		memcpy((char*)pkw_mem,(char*)&buf[4],sizeof(pkw_mem));
+		led_states=((u32)buf[39]<<24)|((u32)buf[38]<<16)|((u32)buf[37]<<8)|((u32)buf[36]<<0);
+		led_blink_states=((u32)buf[43]<<24)|((u32)buf[42]<<16)|((u32)buf[41]<<8)|((u32)buf[40]<<0);
+		virt_in2_states=((u32)buf[47]<<24)|((u32)buf[46]<<16)|((u32)buf[45]<<8)|((u32)buf[44]<<0);
+		memcpy((char*)cnt_mem,(char*)&buf[48],sizeof(cnt_mem));
+
+		comm_bits_act[0]=(u16)buf[48+32+0] | ((u16)buf[48+32+1]<<8);
+		comm_bits_act[1]=(u16)buf[48+32+2] | ((u16)buf[48+32+3]<<8);
+		comm_bits_act[2]=(u16)buf[48+32+4] | ((u16)buf[48+32+5]<<8);
+
+		memcpy((char*)saved_events,(char*)&buf[48+32+6],sizeof(saved_events));
+
+		saved_bank=buf[48+32+6+16];
+	}
+	else
+	{
+		saved_bank = 0;
+		led_states = 0;
+		led_blink_states = 0;
+		virt_in_states=0;
+		virt_in2_states=0;
+		for(i=0;i<8;i++)
+		{
+			pkw_mem[i]=0.0;
+			cnt_mem[i]=0.0;
+		}
+	}
+
+	spi_fram_restored=1;
+
+	for(;;)
+	{
+		if(Semaphore_pend(spi_semaphore,3000))
+		{
+		}
+		else
+		{
+        	if((log_manager.status & LOGMAN_STATUS_STARTED) && (log_manager.status & LOGMAN_STATUS_SOFT_STARTED))
+        	{
+				buf[0]=(virt_in_states>>0)&0xFF;
+				buf[1]=(virt_in_states>>8)&0xFF;
+				buf[2]=(virt_in_states>>16)&0xFF;
+				buf[3]=(virt_in_states>>24)&0xFF;
+				memcpy((char*)&buf[4],(char*)pkw_mem,sizeof(pkw_mem));
+				buf[36]=(led_states>>0)&0xFF;
+				buf[37]=(led_states>>8)&0xFF;
+				buf[38]=(led_states>>16)&0xFF;
+				buf[39]=(led_states>>24)&0xFF;
+				buf[40]=(led_blink_states>>0)&0xFF;
+				buf[41]=(led_blink_states>>8)&0xFF;
+				buf[42]=(led_blink_states>>16)&0xFF;
+				buf[43]=(led_blink_states>>24)&0xFF;
+				buf[44]=(virt_in2_states>>0)&0xFF;
+				buf[45]=(virt_in2_states>>8)&0xFF;
+				buf[46]=(virt_in2_states>>16)&0xFF;
+				buf[47]=(virt_in2_states>>24)&0xFF;
+				memcpy((char*)&buf[48],(char*)cnt_mem,sizeof(cnt_mem));
+				buf[48+32+0]=(comm_bits_act[0]>>0)&0xFF;
+				buf[48+32+1]=(comm_bits_act[0]>>8)&0xFF;
+				buf[48+32+2]=(comm_bits_act[1]>>0)&0xFF;
+				buf[48+32+3]=(comm_bits_act[1]>>8)&0xFF;
+				buf[48+32+4]=(comm_bits_act[2]>>0)&0xFF;
+				buf[48+32+5]=(comm_bits_act[2]>>8)&0xFF;
+				memcpy((char*)&buf[48+32+6],(char*)saved_events,sizeof(saved_events));
+				buf[48+32+6+16]=saved_bank;
+				buf[48+32+6+16+1]=(u8)(mod256_cksum(buf,sizeof(buf)-1)+CKSUM_IV);
+				spi_wr_buf_bl(0,buf,sizeof(buf));
+        	}
+        }
+	}
+}
diff --git a/src/spi.h b/src/spi.h
new file mode 100644
index 0000000..8ce951d
--- /dev/null
+++ b/src/spi.h
@@ -0,0 +1,23 @@
+/*
+ * spi.h
+ *
+ *  Created on: 19-12-2016
+ *      Author: K
+ */
+
+#ifndef SPI_H_
+#define SPI_H_
+
+#include "misc.h"
+
+#define SPI_DEASSERT()	SETDATA8|=(1<<1);
+#define SPI_ASSERT()	CLRDATA8|=(1<<1);
+
+extern u8 spi_fram_restored;
+
+extern void spi_init();
+extern void spi_putc(u16 word);
+
+Void spiFxn(UArg a0, UArg a1);
+
+#endif /* SPI_H_ */
diff --git a/src/tdefs.h b/src/tdefs.h
new file mode 100644
index 0000000..9583833
--- /dev/null
+++ b/src/tdefs.h
@@ -0,0 +1,16 @@
+/*
+ * tdefs.h
+ *
+ *  Created on: 06-12-2013
+ *      Author: Krzysztof Jakubczyk
+ */
+
+#ifndef TDEFS_H_
+#define TDEFS_H_
+
+typedef unsigned int u32;
+typedef short s16;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#endif /* TDEFS_H_ */
diff --git a/src/version.h b/src/version.h
new file mode 100644
index 0000000..16d7197
--- /dev/null
+++ b/src/version.h
@@ -0,0 +1,16 @@
+/*
+ * version.h
+ *
+ *  Created on: 06-02-2017
+ *      Author: K
+ */
+
+#ifndef VERSION_H_
+#define VERSION_H_
+
+#include "misc.h"
+
+#define SW_VER_NO			"DSP-3.0a " // 9 bytes
+#define SW_VER				SW_VER_NO" "__DATE__
+
+#endif /* VERSION_H_ */
diff --git a/test_result.png b/test_result.png
index b58ad95..b0be305 100644
Binary files a/test_result.png and b/test_result.png differ