220 lines
6.8 KiB
C
220 lines
6.8 KiB
C
/*
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* ddr.c
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*
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* Created on: 26-05-2014
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* Author: KJ
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*/
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#include "tdefs.h"
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#include "misc.h"
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#include <ti/ipc/Notify.h>
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#include <string.h>
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#include "ddr.h"
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#include "ddr_drv.h"
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#include "rec_an.h"
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#include "rec_bin.h"
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#include "comm.h"
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#include "misc.h"
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#include "config.h"
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#pragma LOCATION(ddr_bank0,0xc4000000) // @ non-cached memory above 128MB
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volatile u8 ddr_bank0[DDR_REG_BANK_SIZE];
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#pragma LOCATION(ddr_bank1,0xc4100000) // @ non-cached memory above 128MB
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volatile u8 ddr_bank1[DDR_REG_BANK_SIZE];
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#pragma LOCATION(ddr_bank2,0xc4200000) // @ non-cached memory above 128MB
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volatile u8 ddr_bank2[DDR_REG_BANK_SIZE];
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#pragma LOCATION(ddr_bank3,0xc4300000) // @ non-cached memory above 128MB
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volatile u8 ddr_bank3[DDR_REG_BANK_SIZE];
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volatile struct ddr_reg_inf ddr_regs = { .cur_reg_bank = 0,
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.bank[0].data = (void*) ddr_bank0,
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.bank[0].state = BANK_BUFFERING,
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.bank[0].addr_offset = 0,
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.bank[0].pre_trigger_cnt = 0,
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.bank[0].post_trigger_cnt = 0,
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.bank[0].total_cnt = 0,
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.bank[1].data = (void*) ddr_bank1,
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.bank[2].data = (void*) ddr_bank2,
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.bank[3].data = (void*) ddr_bank3,
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};
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int ddr_initlog(void *arguments, void *logic)
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{
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struct ddr_args *args = (struct ddr_args *)arguments;
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struct ddr_logic *log = (struct ddr_logic *)logic;
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log->trigger_ptr = log_manager.nets_data + (args->io.trigger_in >> 3);
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log->trigger_bit_no = args->io.trigger_in & 0x07;
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if(log->trigger_ptr >= (log_manager.nets_data+sizeof(log_manager.nets_data)))
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return -1;
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switch((enum ddr_fs)args->params.f_sampling)
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{
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case Fs_100Hz:
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log->decimation=10/LOOP_CYCLE_MS;
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break;
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case Fs_50Hz:
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log->decimation=20/LOOP_CYCLE_MS;
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break;
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case Fs_10Hz:
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log->decimation=100/LOOP_CYCLE_MS;
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break;
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case Fs_5Hz:
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log->decimation=200/LOOP_CYCLE_MS;
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break;
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case Fs_1Hz:
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log->decimation=1000/LOOP_CYCLE_MS;
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break;
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case Fs_0_5Hz:
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log->decimation=2000/LOOP_CYCLE_MS;
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break;
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case Fs_0_1Hz:
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log->decimation=10000/LOOP_CYCLE_MS;
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break;
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default:
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log->decimation=10/LOOP_CYCLE_MS;
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break;
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}
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log->pre_trigger_samples = args->params.pre_trigger_time / log->decimation;
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if(args->params.pre_trigger_time)
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log->pre_trigger_samples++;
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log->post_trigger_samples = args->params.post_trigger_time / log->decimation;
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if(args->params.post_trigger_time)
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log->post_trigger_samples++;
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log->max_reg_samples = args->params.max_reg_time / log->decimation;
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if(args->params.max_reg_time)
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log->max_reg_samples++;
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return 0;
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}
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void ddr(void *arguments, void *logic)
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{
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struct ddr_logic *log = (struct ddr_logic *)logic;
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//struct ddr_args *args = (struct ddr_args *)arguments;
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struct rec_an_logic *an_log;
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struct rec_bin_logic *bin_log;
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u16 sample_buf[(MAX_SAMPLE_SIZE/sizeof(u16)) + 8];
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int i,bit_cnt=0,pos=0;
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u8 new_sample=0;
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if(ddr_drv_log_ptr == NULL) // ddr driver not initialized?
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return;
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if(!log->decimation_cnt--)
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{
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log->decimation_cnt=log->decimation;
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new_sample=1;
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}
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switch(ddr_regs.bank[ddr_regs.cur_reg_bank].state)
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{
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case BANK_BUFFERING:
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if(*log->trigger_ptr & (1<<log->trigger_bit_no))
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{
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ddr_regs.bank[ddr_regs.cur_reg_bank].state=BANK_TRIGGERED;
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ddr_regs.bank[ddr_regs.cur_reg_bank].tr_time=(timesync_bits & CFG_TSYNC_USE_SWCLK)?cur_time_sw.tv_sec:cur_time.tv_sec;
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ddr_regs.bank[ddr_regs.cur_reg_bank].tr_time_ms=(timesync_bits & CFG_TSYNC_USE_SWCLK)?cur_time_sw.tv_usec:cur_time.tv_usec;
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ddr_regs.bank[ddr_regs.cur_reg_bank].sample_size=ddr_drv_log_ptr->sample_size;
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ddr_regs.bank[ddr_regs.cur_reg_bank].an_count=ddr_drv_log_ptr->an_count;
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ddr_regs.bank[ddr_regs.cur_reg_bank].bin_count=ddr_drv_log_ptr->bin_count;
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ddr_regs.bank[ddr_regs.cur_reg_bank].post_trigger_cnt=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].trigger_offset=ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset;
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ddr_regs.bank[ddr_regs.cur_reg_bank].total_cnt=ddr_regs.bank[ddr_regs.cur_reg_bank].pre_trigger_cnt;
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}
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else
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{
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if(new_sample && ddr_regs.bank[ddr_regs.cur_reg_bank].pre_trigger_cnt<log->pre_trigger_samples)
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ddr_regs.bank[ddr_regs.cur_reg_bank].pre_trigger_cnt++;
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}
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break;
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case BANK_TRIGGERED:
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if(new_sample)
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{
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if(ddr_regs.bank[ddr_regs.cur_reg_bank].total_cnt++>=log->max_reg_samples || ddr_regs.bank[ddr_regs.cur_reg_bank].post_trigger_cnt>=log->post_trigger_samples)
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{
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// send notify to ARM
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ddr_regs.bank[ddr_regs.cur_reg_bank].state=BANK_FILLED;
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ddr_regs.bank[ddr_regs.cur_reg_bank].decimation=log->decimation;
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ddr_regs.cur_reg_bank++;
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ddr_regs.cur_reg_bank%=DDR_MAX_REG_BANKS;
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ddr_regs.bank[ddr_regs.cur_reg_bank].state=BANK_BUFFERING;
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ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].post_trigger_cnt=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].pre_trigger_cnt=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].trigger_offset=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].total_cnt=0;
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logman_notify|=LOGMAN_NOTIFY_NEW_DDR;
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// Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_DDR_REG, TRUE);
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}
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else
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{
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if(*log->trigger_ptr & (1<<log->trigger_bit_no))
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ddr_regs.bank[ddr_regs.cur_reg_bank].post_trigger_cnt=0;
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else
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ddr_regs.bank[ddr_regs.cur_reg_bank].post_trigger_cnt++;
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}
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}
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break;
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case BANK_EMPTY:
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case BANK_FILLED:
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default:
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ddr_regs.bank[ddr_regs.cur_reg_bank].state=BANK_BUFFERING;
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ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].post_trigger_cnt=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].pre_trigger_cnt=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].trigger_offset=0;
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ddr_regs.bank[ddr_regs.cur_reg_bank].total_cnt=0;
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break;
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}
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//
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// will be overwritten by ARM
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// *((u32 *)&sample_buf[0]) = 0; // sample number 1..n
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// *((u32 *)&sample_buf[2]) = 0; // time stamp 0..n*1ms @ 1 kHz
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//
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if(new_sample)
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{
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pos = 4;
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for(i=0;i<ddr_drv_log_ptr->an_count;i++)
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{
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an_log = (struct rec_an_logic *)log_manager.log_element[ddr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
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sample_buf[pos]=*an_log->in_ptr;
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pos++;
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}
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sample_buf[pos]=0;
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for(;i<(ddr_drv_log_ptr->an_count+ddr_drv_log_ptr->bin_count);i++)
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{
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bin_log = (struct rec_bin_logic *)log_manager.log_element[ddr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
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if(*bin_log->in_ptr & bin_log->in_bit_mask)
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sample_buf[pos]|=(1<<(bit_cnt%16));
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if(!(++bit_cnt%16) && bit_cnt)
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{
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pos++;
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sample_buf[pos]=0;
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}
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}
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if(ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset + ddr_drv_log_ptr->sample_size > DDR_REG_BANK_SIZE)
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ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset=0;
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memcpy((u8*)ddr_regs.bank[ddr_regs.cur_reg_bank].data+ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset,(void *)sample_buf,ddr_drv_log_ptr->sample_size);
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ddr_regs.bank[ddr_regs.cur_reg_bank].addr_offset+=ddr_drv_log_ptr->sample_size;
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}
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}
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