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src/omapl138_eth_driver.h
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src/omapl138_eth_driver.h
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/**
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* @file omapl138_eth_driver.h
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* @brief OMAP-L138 Ethernet MAC controller
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*
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* @section License
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
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*
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* This file is part of CycloneTCP Open.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* @author Oryx Embedded SARL (www.oryx-embedded.com)
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* @version 1.9.6
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**/
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#ifndef _OMAPL138_ETH_DRIVER_H
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#define _OMAPL138_ETH_DRIVER_H
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//Dependencies
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//#include "core/nic.h"
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#include "soc_OMAPL138.h"
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//Number of TX buffers
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#ifndef OMAPL138_ETH_TX_BUFFER_COUNT
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#define OMAPL138_ETH_TX_BUFFER_COUNT 8
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#elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1)
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#error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid
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#endif
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//TX buffer size
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#ifndef OMAPL138_ETH_TX_BUFFER_SIZE
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#define OMAPL138_ETH_TX_BUFFER_SIZE 1536
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#elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536)
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#error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid
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#endif
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//Number of RX buffers
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#ifndef OMAPL138_ETH_RX_BUFFER_COUNT
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#define OMAPL138_ETH_RX_BUFFER_COUNT 8
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#elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1)
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#error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid
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#endif
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//RX buffer size
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#ifndef OMAPL138_ETH_RX_BUFFER_SIZE
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#define OMAPL138_ETH_RX_BUFFER_SIZE 1536
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#elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536)
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#error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid
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#endif
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//Channel number for the TX interrupt
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#ifndef OMAPL138_ETH_TX_IRQ_CHANNEL
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#define OMAPL138_ETH_TX_IRQ_CHANNEL 3
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#elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31)
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#error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid
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#endif
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//Channel number for the RX interrupt
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#ifndef OMAPL138_ETH_RX_IRQ_CHANNEL
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#define OMAPL138_ETH_RX_IRQ_CHANNEL 3
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#elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31)
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#error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid
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#endif
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//EMAC cores
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#define EMAC_CORE0 0
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#define EMAC_CORE1 1
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#define EMAC_CORE2 2
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//EMAC channels
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#define EMAC_CH0 0
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#define EMAC_CH1 1
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#define EMAC_CH2 2
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#define EMAC_CH3 3
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#define EMAC_CH4 4
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#define EMAC_CH5 5
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#define EMAC_CH6 6
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#define EMAC_CH7 7
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//SYSCFG0 registers
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#define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
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#define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
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//EMAC registers
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#define EMAC_TXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID)
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#define EMAC_TXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL)
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#define EMAC_TXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN)
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#define EMAC_RXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID)
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#define EMAC_RXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL)
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#define EMAC_RXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN)
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#define EMAC_TXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW)
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#define EMAC_TXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED)
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#define EMAC_TXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET)
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#define EMAC_TXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR)
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#define EMAC_MACINVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR)
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#define EMAC_MACEOIVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR)
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#define EMAC_RXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW)
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#define EMAC_RXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED)
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#define EMAC_RXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET)
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#define EMAC_RXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR)
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#define EMAC_MACINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW)
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#define EMAC_MACINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED)
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#define EMAC_MACINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET)
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#define EMAC_MACINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR)
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#define EMAC_RXMBPENABLE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE)
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#define EMAC_RXUNICASTSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET)
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#define EMAC_RXUNICASTCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR)
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#define EMAC_RXMAXLEN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN)
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#define EMAC_RXBUFFEROFFSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET)
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#define EMAC_RXFILTERLOWTHRESH_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH)
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#define EMAC_RXFLOWTHRESH_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n))
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#define EMAC_RXFREEBUFFER_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n))
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#define EMAC_MACCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL)
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#define EMAC_MACSTATUS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS)
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#define EMAC_EMCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL)
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#define EMAC_FIFOCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL)
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#define EMAC_MACCONFIG_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG)
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#define EMAC_SOFTRESET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET)
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#define EMAC_MACSRCADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO)
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#define EMAC_MACSRCADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI)
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#define EMAC_MACHASH1_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1)
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#define EMAC_MACHASH2_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2)
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#define EMAC_BOFFTEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST)
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#define EMAC_TPACETEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST)
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#define EMAC_RXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE)
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#define EMAC_TXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE)
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#define EMAC_RXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES)
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#define EMAC_RXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES)
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#define EMAC_RXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES)
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#define EMAC_RXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES)
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#define EMAC_RXCRCERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS)
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#define EMAC_RXALIGNCODEERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED)
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#define EMAC_RXJABBER_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER)
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#define EMAC_RXUNDERSIZED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED)
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#define EMAC_RXFRAGMENTS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS)
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#define EMAC_RXFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED)
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#define EMAC_RXQOSFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED)
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#define EMAC_RXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS)
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#define EMAC_TXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES)
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#define EMAC_TXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES)
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#define EMAC_TXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES)
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#define EMAC_TXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES)
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#define EMAC_TXDEFERRED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED)
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#define EMAC_TXCOLLISION_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION)
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#define EMAC_TXSINGLECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL)
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#define EMAC_TXMULTICOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL)
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#define EMAC_TXEXCESSIVECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL)
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#define EMAC_TXLATECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL)
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#define EMAC_TXUNDERRUN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN)
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#define EMAC_TXCARRIERSENSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE)
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#define EMAC_TXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS)
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#define EMAC_FRAME64_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64)
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#define EMAC_FRAME65T127_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127)
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#define EMAC_FRAME128T255_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255)
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#define EMAC_FRAME256T511_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511)
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#define EMAC_FRAME512T1023_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023)
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#define EMAC_FRAME1024TUP_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP)
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#define EMAC_NETOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS)
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#define EMAC_RXSOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS)
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#define EMAC_RXMOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS)
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#define EMAC_RXDMAOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS)
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#define EMAC_MACADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO)
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#define EMAC_MACADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI)
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#define EMAC_MACINDEX_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX)
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#define EMAC_TXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n))
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#define EMAC_RXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n))
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#define EMAC_TXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n))
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#define EMAC_RXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n))
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//EMAC control registers
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#define EMAC_CTRL_REVID_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID)
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#define EMAC_CTRL_SOFTRESET_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET)
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#define EMAC_CTRL_INTCONTRO_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL)
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#define EMAC_CTRL_C0RXTHRESHEN_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN)
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#define EMAC_CTRL_CnRXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n))
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#define EMAC_CTRL_CnTXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n))
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#define EMAC_CTRL_CnMISCEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n))
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#define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n))
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#define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT)
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#define EMAC_CTRL_C0RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT)
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#define EMAC_CTRL_C0TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT)
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#define EMAC_CTRL_C0MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT)
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#define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
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#define EMAC_CTRL_C1RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXSTAT)
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#define EMAC_CTRL_C1TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT)
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#define EMAC_CTRL_C1MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT)
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#define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT)
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#define EMAC_CTRL_C2RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT)
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#define EMAC_CTRL_C2TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT)
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#define EMAC_CTRL_C2MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT)
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#define EMAC_CTRL_C0RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX)
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#define EMAC_CTRL_C0TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX)
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#define EMAC_CTRL_C1RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX)
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#define EMAC_CTRL_C1TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX)
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#define EMAC_CTRL_C2RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX)
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#define EMAC_CTRL_C2TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX)
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//MDIO registers
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#define MDIO_REVID_R HWREG(SOC_MDIO_0_REGS + MDIO_REVID)
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#define MDIO_CONTROL_R HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL)
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#define MDIO_ALIVE_R HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE)
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#define MDIO_LINK_R HWREG(SOC_MDIO_0_REGS + MDIO_LINK)
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#define MDIO_LINKINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW)
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#define MDIO_LINKINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED)
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#define MDIO_USERINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW)
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#define MDIO_USERINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED)
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#define MDIO_USERINTMASKSET_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET)
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#define MDIO_USERINTMASKCLEAR_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR)
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#define MDIO_USERACCESS0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0)
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#define MDIO_USERPHYSEL0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0)
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#define MDIO_USERACCESS1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1)
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#define MDIO_USERPHYSEL1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1)
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//MACEOIVECTOR register
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#define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000
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#define EMAC_MACEOIVECTOR_C0RX 0x00000001
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#define EMAC_MACEOIVECTOR_C0TX 0x00000002
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#define EMAC_MACEOIVECTOR_C0MISC 0x00000003
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#define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004
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#define EMAC_MACEOIVECTOR_C1RX 0x00000005
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#define EMAC_MACEOIVECTOR_C1TX 0x00000006
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#define EMAC_MACEOIVECTOR_C1MISC 0x00000007
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#define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008
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#define EMAC_MACEOIVECTOR_C2RX 0x00000009
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#define EMAC_MACEOIVECTOR_C2TX 0x0000000A
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#define EMAC_MACEOIVECTOR_C2MISC 0x0000000B
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//TX buffer descriptor flags
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#define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
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#define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
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#define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
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#define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
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#define EMAC_TX_WORD3_SOP 0x80000000
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#define EMAC_TX_WORD3_EOP 0x40000000
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#define EMAC_TX_WORD3_OWNER 0x20000000
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#define EMAC_TX_WORD3_EOQ 0x10000000
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#define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000
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#define EMAC_TX_WORD3_PASSCRC 0x04000000
|
||||
#define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF
|
||||
|
||||
//RX buffer descriptor flags
|
||||
#define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
|
||||
#define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
|
||||
#define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000
|
||||
#define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF
|
||||
#define EMAC_RX_WORD3_SOP 0x80000000
|
||||
#define EMAC_RX_WORD3_EOP 0x40000000
|
||||
#define EMAC_RX_WORD3_OWNER 0x20000000
|
||||
#define EMAC_RX_WORD3_EOQ 0x10000000
|
||||
#define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000
|
||||
#define EMAC_RX_WORD3_PASSCRC 0x04000000
|
||||
#define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000
|
||||
#define EMAC_RX_WORD3_JABBER 0x02000000
|
||||
#define EMAC_RX_WORD3_OVERSIZE 0x01000000
|
||||
#define EMAC_RX_WORD3_FRAGMENT 0x00800000
|
||||
#define EMAC_RX_WORD3_UNDERSIZED 0x00400000
|
||||
#define EMAC_RX_WORD3_CONTROL 0x00200000
|
||||
#define EMAC_RX_WORD3_OVERRUN 0x00100000
|
||||
#define EMAC_RX_WORD3_CODEERROR 0x00080000
|
||||
#define EMAC_RX_WORD3_ALIGNERROR 0x00040000
|
||||
#define EMAC_RX_WORD3_CRCERROR 0x00020000
|
||||
#define EMAC_RX_WORD3_NOMATCH 0x00010000
|
||||
#define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF
|
||||
|
||||
//C++ guard
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief TX buffer descriptor
|
||||
**/
|
||||
|
||||
typedef struct _Omapl138TxBufferDesc
|
||||
{
|
||||
uint32_t word0;
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
uint32_t word3;
|
||||
struct _Omapl138TxBufferDesc *next;
|
||||
struct _Omapl138TxBufferDesc *prev;
|
||||
} Omapl138TxBufferDesc;
|
||||
|
||||
|
||||
/**
|
||||
* @brief RX buffer descriptor
|
||||
**/
|
||||
|
||||
typedef struct _Omapl138RxBufferDesc
|
||||
{
|
||||
uint32_t word0;
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
uint32_t word3;
|
||||
struct _Omapl138RxBufferDesc *next;
|
||||
struct _Omapl138RxBufferDesc *prev;
|
||||
} Omapl138RxBufferDesc;
|
||||
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
|
||||
//AM335x Ethernet MAC driver
|
||||
//extern const NicDriver omapl138EthDriver;
|
||||
|
||||
//AM335x Ethernet MAC related functions
|
||||
/*error_t omapl138EthInit(NetInterface *interface);
|
||||
void omapl138EthInitGpio(NetInterface *interface);
|
||||
void omapl138EthInitBufferDesc(NetInterface *interface);
|
||||
|
||||
void omapl138EthTick(NetInterface *interface);
|
||||
|
||||
void omapl138EthEnableIrq(NetInterface *interface);
|
||||
void omapl138EthDisableIrq(NetInterface *interface);
|
||||
void omapl138EthTxIrqHandler(void);
|
||||
void omapl138EthRxIrqHandler(void);
|
||||
void omapl138EthEventHandler(NetInterface *interface);
|
||||
|
||||
error_t omapl138EthSendPacket(NetInterface *interface,
|
||||
const NetBuffer *buffer, size_t offset);
|
||||
|
||||
error_t omapl138EthReceivePacket(NetInterface *interface);
|
||||
|
||||
error_t omapl138EthUpdateMacAddrFilter(NetInterface *interface);
|
||||
error_t omapl138EthUpdateMacConfig(NetInterface *interface);
|
||||
*/
|
||||
void omapl138EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
|
||||
uint8_t regAddr, uint16_t data);
|
||||
|
||||
uint16_t omapl138EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
|
||||
uint8_t regAddr);
|
||||
|
||||
//C++ guard
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user