Pierwsza wersja wygenerowana automatycznie przez SI minmax-m2.5
This commit is contained in:
@@ -3,7 +3,20 @@
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"allow": [
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"Bash(pip install:*)",
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"Bash(python:*)",
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"Bash(taskkill:*)"
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"Bash(taskkill:*)",
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"Bash(git add:*)",
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"Bash(git commit:*)",
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"Bash(ls:*)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance status)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance ls-files)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance check-ignore D:/Mirek/ZPrAE/Distance/tester.py D:/Mirek/ZPrAE/Distance/distance_algorithm.py)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance status:*)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance ls-files:*)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance add tester.py distance_algorithm.py)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance log --oneline -3)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance log --oneline -5)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance show --stat HEAD)",
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"Bash(git -C D:/Mirek/ZPrAE/Distance show --stat 46a3283)"
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]
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}
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}
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1994
ZDistA_komp.c
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1994
ZDistA_komp.c
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File diff suppressed because it is too large
Load Diff
465
ZDistA_komp.h
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465
ZDistA_komp.h
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@@ -0,0 +1,465 @@
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/*
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* ZDistA.h
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*
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*
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* Created on: 21-07-2023
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* Author: PS
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*/
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#ifndef ZDISTA_H_KOMP
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#define ZDISTA_H_KOMP
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//#include "pawel_usun_to.h"
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#include "../tdefs.h"
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#include "helper.h"
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#include "ZDistL.h"
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struct impedancja_ZDistA_komp
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{
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float R[9]; // czesc rzeczywista impedancji
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float X[9]; // czesc urojona impedancji
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float Z[9]; //kwadrat impedancji
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float absR[9]; // wartosc bezwzgledna impedancji czesc rzeczywista
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float absX[9]; // wartosc bezwzgledna impedancji czesc urojona
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float XRtanfi2[9]; // abs(X+R*tan(fi2))
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// float XRtanfi1[9]; // abs(X-R*tan(fi1))
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//[0] petla L1-E strefa 1
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//[1] petla L2-E strefa 1
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//[2] petla L3-E strefa 1
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//[3] petla L1-E strefa 2,3,4,5
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//[4] petla L2-E strefa 2,3,4,5
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//[5] petla L3-E strefa 2,3,4,5
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//[6] petla L1-L2
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//[7] petla L2-L3
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//[8] petla L3-L1
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float XRtanfi1_noabs[9];
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//float E[9];
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};
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struct dane_wewnetrzne_ZDistA_komp
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{
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struct impedancja_ZDistA_komp Z;
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u8 Km;
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u8 Kp;
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u8 Igr[6]; // przekroczenie wartosci granicznej pradu
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u8 Iogr; // zwarcie z udzialem ziemi
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u8 P_s[6][6];//pobudzenie kryterium impedacyjnego (obszar) [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1]
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u8 P_sss[6][6];
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u8 Pbk[6][6];//pobudzenie w strefie [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1] bezkierunkowe
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u8 P[6][6];//pobudzenie w strefie [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1]
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u8 BL_Load[9]; ///< impedancja w obszrze pradow roboczych
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u8 XKp[6][9]; ///< impedancyjne kryterium kierunku "do przodu"
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u8 XKm[6][9]; ///< impedancyjne kryterium kierunku "do tylu"
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u8 Zm[9];///< impedancyjne kryterium bardzo bliskiego zwarcia
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short liczp10[9]; /// licznik pobudzen
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short liczp11[6][9]; /// licznik pobudzen
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short liczp12[6][9]; /// licznik pobudzen
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//[0] petla L1-E strefa 1
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//[1] petla L2-E strefa 1
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//[2] petla L3-E strefa 1
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//[3] petla L1-E strefa 2,3,4,5
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//[4] petla L2-E strefa 2,3,4,5
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//[5] petla L3-E strefa 2,3,4,5
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//[6] petla L1-L2
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//[7] petla L2-L3
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//[8] petla L3-L1
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short liczps[6][6]; //liczniki pobudzen dla pobudzen stref [numer strefy][L1E,L2E,L3E,L1L2,L2L3,L3L1]
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short liczpIo; //licznik pobudzen dla identyfikacji zwarc z udzialem ziemi
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short liczKdod;
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float U1;
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float U2;
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float U3;
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float I1;
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float I2;
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float I3;
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struct ZDistA_komp_logic *log_ptr;
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//wyliczenie dl wektora
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float modul_zf[6];
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float modul_zmf[6];
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float Z_min;
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float Z_min_mf;
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};
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struct nast_w_poligon_komp
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{
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float Xr; // zasieg dla poligonu i srodek okregu dla kolowej wspolrzedna X
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float Rr; // zasieg dla dla poligonu i srodek okregu dla kolowej wspolrzedna R
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float Z; // srednica kola charakterystyki kolowej
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float Xp; // zasieg dla poligonu i srodek okregu dla kolowej wspolrzedna X dla powrotu
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float Rp; // zasieg dla dla poligonu i srodek okregu dla kolowej wspolrzedna R dla powrotu
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float Zp; // srednica kola charakterystyki kolowej dla powrotu
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float Rrtanfi1;// wartość rozruchowa prostej nachylonej kątem linii
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float Rptanfi1;// wartość powrotowa prostej nachylonej kątem linii
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};
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struct Wyjscia_ZDistA_komp // struktura wyjsc przekaznika
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{
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struct dane_wewnetrzne_ZDistA_komp *Zdist_dw;
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float przekladnia;
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u8 *on;
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u8 SOTF_zwrotnie;
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};
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struct Nastawy_przeliczone_ZDistA_komp
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{
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struct Wyjscia_ZDistA_komp wyjscie;
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u8 on_;
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u8 bl_;
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u8 z6_kolo;
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u8 Bl_L[6];
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u8 typ[6];// typ charakterystyki 0 - poligonalna, 1- kolowa
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float ReK1; // skladowa rzeczywista wspolczynnika kompensacji ziemnozwarciowej dla strefy 1
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float ImK1;// skladowa urojona wspolczynnika kompensacji ziemnozwarciowej dla strefy 1
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float ReKr;// skladowa rzeczywista wspolczynnika kompensacji ziemnozwarciowej dla stref 2,3,4,5
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float ImKr;// skladowa urojona wspolczynnika kompensacji ziemnozwarciowej dla stref 2,3,4,5
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struct nast_w_poligon_komp n_pol[6][2]; // nastawy stref dla charakterystyki poligonalnej [numer strefy][LE/LL]
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float tanfi1; // tangens kata linii
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float tanfi2; //tangens kata dodatkowej prostej dla charakterystyki poligonalnej strefa 1
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float Xr1f; // wartosc rozruchowa dodatkowej prostej dla charakterystyki poligonalnej
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float Xr1fp; // wartosc powrotowa dodatkowej prostej dla charakterystyki poligonalnej
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float Xr1Wf; // wartosc rozruchowa dodatkowej prostej dla charakterystyki poligonalnej
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float Xr1Wfp; // wartosc powrotowa dodatkowej prostej dla charakterystyki poligonalnej
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float Igr; // wartosc kwadratu pradu granicznego warunku dzialania przekaznika
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float Igrp; // wartosc kwadratu pradu granicznego warunku dzialania przekaznika (powrot)
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float Zgr;// minimalna wartosc impedancji kryteriunkierunkowego w kwadracie
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float kp;//współczynnik powrotu dla niedomiarówek
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float kpp;//współczynnik powrotu dla nadmiarówek
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float kpk; //kwadrat współczynnika powrotu
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short kierunek[6];
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//A2
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float XKR; // wspolczynnik prostej R kierunku kryterium impedancyjnego
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float XKX; // wspolczynnik prostej R kierunku kryterium impedancyjnego
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float KL;//wspolczynnik prostej dla blokady od obszaru obciażenia
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float RLf; // wartosc rozruchowa blokady Load do przodu
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float RLr; // wartosc rozruchowa blokady Load do tylu
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float Iogr; // wartosc graniczna skladowej zerowej identyfikacji zwarc z udzialem ziemi
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float khio; // wspolczynnik stabilizacji dla przekaznika identyfikacji zwarc z udzialem ziemi
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float Uomin; ///< minimalna wartość napięcia składowej zerowej
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float ReKrown; // skladowa rzeczywista wspolczynnika dla linii rownoleglej
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float ImKrown;// skladowa urojona wspolczynnika dla linii rownoleglej
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float Krown_ignac;
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float kp_obc; //wspolczynnik powrotu krzywych obciazenia
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float kpp_obc; //kwadrat współczynnika powrotu krzywych obciazenia
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};
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struct ZDistA_komp_logic
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{
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struct binary_io stan_bl;
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struct binary_io Bl_K;
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float *I1_orta; ///< Skladowa ortogonalna a pradu faza L1
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float *I1_ortb; ///< Skladowa ortogonalna b pradu faza L1
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float *I1; ///< Prad mierzony faza 1
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float *I2_orta; ///< Skladowa ortogonalna a pradu faza L2
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float *I2_ortb; ///< Skladowa ortogonalna b pradu faza L2
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float *I2; ///< Prad mierzony faza 2
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float *I3_orta; ///< Skladowa ortogonalna a pradu faza L3
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float *I3_ortb; ///< Skladowa ortogonalna b pradu faza L3
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float *I3; ///< Prad mierzony faza 3
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float *U1_orta; ///< Skladowa ortogonalna a napiecia faza L1
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float *U1_ortb; ///< Skladowa ortogonalna b napiecia faza L1
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float *U1; ///< Napiecie mierzone faza 1
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float *U2_orta; ///< Skladowa ortogonalna a napiecia faza L2
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float *U2_ortb; ///< Skladowa ortogonalna b napiecia faza L2
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float *U2; ///< Napiecie mierzone faza 2
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float *U3_orta; ///< Skladowa ortogonalna a napiecia faza L3
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float *U3_ortb; ///< Skladowa ortogonalna b napiecia faza L3
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float *U3; ///< Napiecie mierzone faza 3
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float *U12_orta; ///< Skladowa ortogonalna a napiecia L1-L2
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float *U12_ortb; ///< Skladowa ortogonalna b napiecia L1-L2
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float *U12; ///< Napiecie mierzone L1-L2
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float *U23_orta; ///< Skladowa ortogonalna a napiecia L2-L3
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float *U23_ortb; ///< Skladowa ortogonalna b napiecia L2-L3
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float *U23; ///< Napiecie mierzone L2-L3
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float *U31_orta; ///< Skladowa ortogonalna a napiecia L3-L1
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float *U31_ortb; ///< Skladowa ortogonalna b napiecia L3-L1
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float *U31; ///< Napiecie mierzone L3-L1
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float *sI1_orta; ///< Skladowa ortogonalna a skladowej zgodnej pradu
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float *sI1_ortb; ///< Skladowa ortogonalna b skladowej zgodnej pradu
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float *sI1; ///< Skladowa zgodna pradu
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float *sI2_orta; ///< Skladowa ortogonalna a skladowej przeciwnej pradu
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float *sI2_ortb; ///< Skladowa ortogonalna b skladowej przeciwnej pradu
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float *sI2; ///< Skladowa przeciwna pradu
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float *sI0_orta; ///< Skladowa ortogonalna a skladowej zerowej pradu
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float *sI0_ortb; ///< Skladowa ortogonalna b skladowej zerowej pradu
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float *sI0; ///< Skladowa zerowa pradu
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float *sU1_orta; ///< Skladowa ortogonalna a skladowej zgodnej napiecia
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float *sU1_ortb; ///< Skladowa ortogonalna b skladowej zgodnej napiecia
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float *sU1; ///< Skladowa zgodna napiecia
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float *sU2_orta; ///< Skladowa ortogonalna a skladowej przeciwnej napiecia
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float *sU2_ortb; ///< Skladowa ortogonalna b skladowej przeciwnej napiecia
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float *sU2; ///< Skladowa przeciwna napiecia
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float *sU0_orta; ///< Skladowa ortogonalna a skladowej zerowej napiecia
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float *sU0_ortb; ///< Skladowa ortogonalna b skladowej zerowej napiecia
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float *sU0; ///< Skladowa zerowa napiecia
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struct analog_in_params *param_I; ///< Parametry wejscia pradowego
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struct analog_in_params *param_U; /// < Parametry kanalu napieciowego
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struct binary_io test;
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struct binary_io P1W_L1E; ///< Pobudzenie strefy 1W zwarcie L1-E
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struct binary_io P1W_L2E; ///< Pobudzenie strefy 1W zwarcie L2-E
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struct binary_io P1W_L3E; ///< Pobudzenie strefy 1W zwarcie L3-E
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struct binary_io P1W_L1L2; ///< Pobudzenie strefy 1W zwarcie L1-L2
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struct binary_io P1W_L2L3; ///< Pobudzenie strefy 1W zwarcie L2-L3
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struct binary_io P1W_L3L1; ///< Pobudzenie strefy 1W zwarcie L3-L1
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struct binary_io P1_L1E; ///< Pobudzenie strefy 1 zwarcie L1-E
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struct binary_io P1_L2E; ///< Pobudzenie strefy 1 zwarcie L2-E
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struct binary_io P1_L3E; ///< Pobudzenie strefy 1 zwarcie L3-E
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struct binary_io P1_L1L2; ///< Pobudzenie strefy 1 zwarcie L1-L2
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struct binary_io P1_L2L3; ///< Pobudzenie strefy 1 zwarcie L2-L3
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struct binary_io P1_L3L1; ///< Pobudzenie strefy 1 zwarcie L3-L1
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struct binary_io P2_L1E; ///< Pobudzenie strefy 2 zwarcie L1-E
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struct binary_io P2_L2E; ///< Pobudzenie strefy 2 zwarcie L2-E
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struct binary_io P2_L3E; ///< Pobudzenie strefy 2 zwarcie L3-E
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struct binary_io P2_L1L2; ///< Pobudzenie strefy 2 zwarcie L1-L2
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struct binary_io P2_L2L3; ///< Pobudzenie strefy 2 zwarcie L2-L3
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struct binary_io P2_L3L1; ///< Pobudzenie strefy 2 zwarcie L3-L1
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struct binary_io P3_L1E; ///< Pobudzenie strefy 3 zwarcie L1-E
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struct binary_io P3_L2E; ///< Pobudzenie strefy 3 zwarcie L2-E
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struct binary_io P3_L3E; ///< Pobudzenie strefy 3 zwarcie L3-E
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struct binary_io P3_L1L2; ///< Pobudzenie strefy 3 zwarcie L1-L2
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struct binary_io P3_L2L3; ///< Pobudzenie strefy 3 zwarcie L2-L3
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struct binary_io P3_L3L1; ///< Pobudzenie strefy 3 zwarcie L3-L1
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struct binary_io P4_L1E; ///< Pobudzenie strefy 4 zwarcie L1-E
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struct binary_io P4_L2E; ///< Pobudzenie strefy 4 zwarcie L2-E
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struct binary_io P4_L3E; ///< Pobudzenie strefy 4 zwarcie L3-E
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struct binary_io P4_L1L2; ///< Pobudzenie strefy 4 zwarcie L1-L2
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struct binary_io P4_L2L3; ///< Pobudzenie strefy 4 zwarcie L2-L3
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struct binary_io P4_L3L1; ///< Pobudzenie strefy 4 zwarcie L3-L1
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struct binary_io P5_L1E; ///< Pobudzenie strefy 5 zwarcie L1-E
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struct binary_io P5_L2E; ///< Pobudzenie strefy 5 zwarcie L2-E
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struct binary_io P5_L3E; ///< Pobudzenie strefy 5 zwarcie L3-E
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struct binary_io P5_L1L2; ///< Pobudzenie strefy 5 zwarcie L1-L2
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struct binary_io P5_L2L3; ///< Pobudzenie strefy 5 zwarcie L2-L3
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struct binary_io P5_L3L1; ///< Pobudzenie strefy 5 zwarcie L3-L1
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struct binary_io deakt; /// deaktywacja
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struct binary_io wyl; ///wejscie zwrotne info o wylacenia
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float *I_row_orta; ///< Skladowa ortogonalna a skladowej zgodnej napiecia
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float *I_row_ortb; ///< Skladowa ortogonalna a skladowej zgodnej napiecia
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struct analog_in_params *param_I_rown; ///< Parametry wejscia pradowego
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struct dane_wewnetrzne_ZDistA_komp dw;
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struct Nastawy_przeliczone_ZDistA_komp nast_;// struktura z parametrami
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u8 l_nieustalony;
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float *z[6]; /// debug
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};
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struct ZDistA_komp_io
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{
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u32 bl_in;
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u32 bl_k_in;
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u32 i1_orta_float_in;
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u32 i1_ortb_float_in;
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u32 i1_float_in;
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u32 i2_orta_float_in;
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u32 i2_ortb_float_in;
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u32 i2_float_in;
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u32 i3_orta_float_in;
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u32 i3_ortb_float_in;
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u32 i3_float_in;
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u32 u1_orta_float_in;
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u32 u1_ortb_float_in;
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u32 u1_float_in;
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u32 u2_orta_float_in;
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u32 u2_ortb_float_in;
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u32 u2_float_in;
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u32 u3_orta_float_in;
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u32 u3_ortb_float_in;
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u32 u3_float_in;
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u32 u12_orta_float_in;
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u32 u12_ortb_float_in;
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u32 u12_float_in;
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u32 u23_orta_float_in;
|
||||
u32 u23_ortb_float_in;
|
||||
u32 u23_float_in;
|
||||
u32 u31_orta_float_in;
|
||||
u32 u31_ortb_float_in;
|
||||
u32 u31_float_in;
|
||||
u32 i1_zg_orta_float_in;
|
||||
u32 i1_zg_ortb_float_in;
|
||||
u32 i1_zg_float_in;
|
||||
u32 i2_pr_orta_float_in;
|
||||
u32 i2_pr_ortb_float_in;
|
||||
u32 i2_pr_float_in;
|
||||
u32 io_orta_float_in;
|
||||
u32 io_ortb_float_in;
|
||||
u32 io_float_in;
|
||||
u32 u1_zg_orta_float_in;
|
||||
u32 u1_zg_ortb_float_in;
|
||||
u32 u1_zg_float_in;
|
||||
u32 u2_pr_orta_float_in;
|
||||
u32 u2_pr_ortb_float_in;
|
||||
u32 u2_pr_float_in;
|
||||
u32 uo_orta_float_in;
|
||||
u32 uo_ortb_float_in;
|
||||
u32 uo_float_in;
|
||||
u32 i_param_an_ptr_in;
|
||||
u32 u_param_an_ptr_in;
|
||||
u32 test_in;
|
||||
u32 deakt_in;
|
||||
u32 wyl_in;
|
||||
|
||||
u32 i_rown_orta_float_in;
|
||||
u32 i_rown_ortb_float_in;
|
||||
u32 i_rown_an_ptr_in;
|
||||
|
||||
u32 wy_ptr_out; //zainicjowac
|
||||
u32 P1W_L1E_out;
|
||||
u32 P1W_L2E_out;
|
||||
u32 P1W_L3E_out;
|
||||
u32 P1W_L1L2_out;
|
||||
u32 P1W_L2L3_out;
|
||||
u32 P1W_L3L1_out;
|
||||
u32 P1_L1E_out;
|
||||
u32 P1_L2E_out;
|
||||
u32 P1_L3E_out;
|
||||
u32 P1_L1L2_out;
|
||||
u32 P1_L2L3_out;
|
||||
u32 P1_L3L1_out;
|
||||
u32 P2_L1E_out;
|
||||
u32 P2_L2E_out;
|
||||
u32 P2_L3E_out;
|
||||
u32 P2_L1L2_out;
|
||||
u32 P2_L2L3_out;
|
||||
u32 P2_L3L1_out;
|
||||
u32 P3_L1E_out;
|
||||
u32 P3_L2E_out;
|
||||
u32 P3_L3E_out;
|
||||
u32 P3_L1L2_out;
|
||||
u32 P3_L2L3_out;
|
||||
u32 P3_L3L1_out;
|
||||
u32 P4_L1E_out;
|
||||
u32 P4_L2E_out;
|
||||
u32 P4_L3E_out;
|
||||
u32 P4_L1L2_out;
|
||||
u32 P4_L2L3_out;
|
||||
u32 P4_L3L1_out;
|
||||
u32 P5_L1E_out;
|
||||
u32 P5_L2E_out;
|
||||
u32 P5_L3E_out;
|
||||
u32 P5_L1L2_out;
|
||||
u32 P5_L2L3_out;
|
||||
u32 P5_L3L1_out;
|
||||
|
||||
//debug
|
||||
u32 z1_float_out;
|
||||
u32 z2_float_out;
|
||||
u32 z3_float_out;
|
||||
u32 z4_float_out;
|
||||
u32 z5_float_out;
|
||||
u32 z6_float_out;
|
||||
|
||||
}__attribute__((__packed__));
|
||||
|
||||
struct ZDistA_komp_params
|
||||
{
|
||||
u32 bity; ///< nastawy bitowe;
|
||||
|
||||
long Typ1; ///< Typ charakterystyki strefa 1
|
||||
long Typ2; ///< Typ charakterystyki strefa 2
|
||||
long Typ3; ///< Typ charakterystyki strefa 3
|
||||
long Typ4; ///< Typ charakterystyki strefa 4
|
||||
long Typ5; ///< Typ charakterystyki strefa 5
|
||||
long K1; ///< Kierunek dzialania strefa 1
|
||||
long K2; ///< Kierunek dzialania strefa 2
|
||||
long K3; ///< Kierunek dzialania strefa 3
|
||||
long K4; ///< Kierunek dzialania strefa 4
|
||||
long K5; ///< Kierunek dzialania strefa 5
|
||||
|
||||
double I_min; ///< Graniczna wartosc pradu
|
||||
double Kk1; ///< Wspolczynnik kompensacji ziemnozwarciowej strefa 1
|
||||
double Kk1_kat; ///< Kat wektora kompensacji ziemnozwarciowej strefa 1
|
||||
double KkC; ///< Wspolczynnik kompensacji ziemnozwarciowej stref 2,3,4,5
|
||||
double KkC_kat; ///< Kat wektora kompensacji ziemnozwarciowej stref 2,3,4,5
|
||||
double fi1; ///< Kat linii
|
||||
double fi2; ///< Kat nachylenia prostej korekcji strefy pierwszej dla zwarc jednofazowych z ziemia
|
||||
double R1W_Zf1W_LE; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do przodu” wydluzenie strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double R1W_Zf1W_LL; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do przodu” wyduzenie strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double R1_Zf1_LE; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do przodu” strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double R1_Zf1_LL; ///< Zasieg rezystancyjny strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do przodu” strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double R2_Zf2_LE; ///< Zasieg rezystancyjny strefy 2 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do przodu” strefy 2 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double R2_Zf2_LL; ///< Zasieg rezystancyjny strefy 2 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do przodu” strefy 2 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double R3_Zf3_LE; ///< Zasieg rezystancyjny strefy 3 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do przodu” strefy 3 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double R3_Zf3_LL; ///< Zasieg rezystancyjny strefy 3 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do przodu” strefy 3 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double R4_Zf4_LE; ///< Zasieg rezystancyjny strefy 4 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do przodu” strefy 4 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double R4_Zf4_LL; ///< Zasieg rezystancyjny strefy 4 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do przodu” strefy 4 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double R5_Zf5_LE; ///< Zasieg rezystancyjny strefy 5 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do przodu” strefy 5 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double R5_Zf5_LL; ///< Zasieg rezystancyjny strefy 5 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do przodu” strefy 5 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double X1W_Zr1W_LE; ///< Zasieg reaktancyjny wydluzenie strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do tylu” wydluzenie strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double X1W_Zr1W_LL; ///< Zasieg reaktancyjny wydluzenie strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do tylu” wydluzenie strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double X1_Zr1_LE; ///< Zasieg reaktancyjny strefy 1 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do tylu” strefy 1 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double X1_Zr1_LL; ///< Zasieg reaktancyjny strefy 1 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do tylu” strefy 1 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double X2_Zr2_LE; ///< Zasieg reaktancyjny strefy 2 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do tylu” strefy 2 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double X2_Zr2_LL; ///< Zasieg reaktancyjny strefy 2 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do tylu” strefy 2 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double X3_Zr3_LE; ///< Zasieg reaktancyjny strefy 3 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do tylu” strefy 3 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double X3_Zr3_LL; ///< Zasieg reaktancyjny strefy 3 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do tylu” strefy 3 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double X4_Zr4_LE; ///< Zasieg reaktancyjny strefy 4 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do tylu” strefy 4 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double X4_Zr4_LL; ///< Zasieg reaktancyjny strefy 4 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do tylu” strefy 4 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double X5_Zr5_LE; ///< Zasieg reaktancyjny strefy 5 dla charakterystyki poligonalnej zwarcie jednofazowe z ziemia
|
||||
///< Zasieg „do tylu” strefy 5 charakterystyki kolowej zwarcie jednofazowe z ziemia
|
||||
double X5_Zr5_LL; ///< Zasieg reaktancyjny strefy 5 dla charakterystyki poligonalnej zwarcie miedzyfazowe
|
||||
///< Zasieg „do tylu” strefy 5 charakterystyki kolowej zwarcie miedzyfazowe
|
||||
double kp; ///< wspolczynnik powrotu
|
||||
//A2
|
||||
// double U_min; ///< Minimalna wartosc napiecia
|
||||
double fi3; ///< Kat kierunkowy od osi X impedancyjnego kryterium kierunku
|
||||
double fi4; ///< Kat kierunkowy od osi R impedancyjnego kryterium kierunku
|
||||
double RLf; ///< Zasieg „ do przodu” kryterium blokady dzialania w zakresie pradow obciażenia
|
||||
double RLr; ///< Zasieg „ do tylu” kryterium blokady dzialania w zakresie pradow obciażenia
|
||||
double fi5; ///< Kat kierunkowy blokady dzialania w zakresie pradow obciażenia
|
||||
double Iomin; ///< Minimalna wartosc rozruchowa pradu zerowego przekaznika identyfikacji zwarc z udzialem ziemi
|
||||
double Iokh; ///< Wspolczynnik stabilizacji charakterystyki przekaznika identyfikacji zwarc z udzialem ziemi
|
||||
double Uomin; ///< minimalna wartość napięcia składowej zerowej
|
||||
|
||||
long Typ0; ///< Typ charakterystyki strefa 1W
|
||||
long K0; ///< Kierunek dzialania strefa 1W
|
||||
|
||||
double Krown; ///< Wspolczynnik kompensacji linii rown
|
||||
double Krown_kat; ///< Kat wektora kompensacji lnii rown
|
||||
|
||||
double kp_obc; ///< Współczynnik powrotu dla blokady od prądu obciążenia
|
||||
|
||||
}__attribute__((__packed__));
|
||||
|
||||
struct ZDistA_komp_args
|
||||
{
|
||||
struct ZDistA_komp_io io;
|
||||
struct ZDistA_komp_params params;
|
||||
// u16 crc;
|
||||
}__attribute__((__packed__));
|
||||
|
||||
extern void ZDistA_komp(void *args, void *logic);
|
||||
extern int ZDistA_komp_initlog(void *arguments, void *logic);
|
||||
|
||||
#endif /* ZDISTA_H_KOMP */
|
||||
1589
ZDistL_komp.c
Normal file
1589
ZDistL_komp.c
Normal file
File diff suppressed because it is too large
Load Diff
413
ZDistL_komp.h
Normal file
413
ZDistL_komp.h
Normal file
@@ -0,0 +1,413 @@
|
||||
/*
|
||||
* ZDistL.h
|
||||
*
|
||||
*
|
||||
* Created on: 29-11-2016
|
||||
* Author: KJ
|
||||
*/
|
||||
|
||||
#ifndef ZDISTL_H_KOMP_
|
||||
#define ZDISTL_H_KOMP_
|
||||
//#include "pawel_usun_to.h"
|
||||
|
||||
#include "../tdefs.h"
|
||||
#include "helper.h"
|
||||
#include "ZDistL.h"
|
||||
|
||||
|
||||
struct Wyjscie1_zdistl_komp
|
||||
{
|
||||
u8 dbl_Com[7]; ///deblokowanie działania stref w zależności od stanu łącza
|
||||
u8 PSPZ;//pobudzenie SPZ
|
||||
};
|
||||
|
||||
struct dane_wewnetrzne_ZDistL_komp
|
||||
{
|
||||
u8 blok_lacza[6];
|
||||
u8 wydl_czas;
|
||||
u8 wylacz_od_lacza;
|
||||
u8 wylacz_od_echa;
|
||||
u8 wylacz_od_lacza_suma;
|
||||
//lacze nad
|
||||
u16 t_lacze_nad;
|
||||
u8 lacze_nad;
|
||||
|
||||
u16 trwanie_nad;
|
||||
u8 skrocil_strefa;
|
||||
u8 skrocil_echo;
|
||||
|
||||
|
||||
//logika pradu wstecznego
|
||||
u8 blokada_pradu_wstecznego;
|
||||
u16 t_pod_blok_wst;
|
||||
u8 kopia_lacze_ok;
|
||||
u8 lacze_odb_old;
|
||||
|
||||
|
||||
//logika odblokowania
|
||||
u8 logika_dblokowania;
|
||||
u16 t_log_odblokowania;
|
||||
|
||||
u8 blok_LRC[6];
|
||||
|
||||
|
||||
u16 t_wyl_od_echa;
|
||||
|
||||
float RL1Em; ///< Rezystancja pętli zwarciowej fazy L1 z ziemia (rejestracja)
|
||||
float XL1Em; ///< Rezaktancja pętli zwarciowej fazy L1 z ziemia (rejestracja)
|
||||
float RL2Em; ///< Rezystancja pętli zwarciowej fazy L2 z ziemia (rejestracja)
|
||||
float XL2Em; ///< Rezaktancja pętli zwarciowej fazy L2 z ziemia (rejestracja)
|
||||
float RL3Em; ///< Rezystancja pętli zwarciowej fazy L3 z ziemia (rejestracja)
|
||||
float XL3Em; ///< Rezaktancja pętli zwarciowej fazy L3 z ziemia (rejestracja)
|
||||
float RL1L2m; ///< Rezystancja pętli zwarciowej fazy L1 z L2 (rejestracja)
|
||||
float XL1L2m; ///< Rezaktancja pętli zwarciowej fazy L1 z L2 (rejestracja)
|
||||
float RL2L3m; ///< Rezystancja pętli zwarciowej fazy L2 z L3 (rejestracja)
|
||||
float XL2L3m; ///< Rezaktancja pętli zwarciowej fazy L2 z L3 (rejestracja)
|
||||
float RL3L1m; ///< Rezystancja pętli zwarciowej fazy L3 z L1 (rejestracja)
|
||||
float XL3L1m; ///< Rezaktancja pętli zwarciowej fazy L3 z L1 (rejestracja)
|
||||
short liczts[6][2]; ///<licznik czasu czas opoznienia dzialania strefy
|
||||
|
||||
short liczt_eldz[6][2]; ///<licznik czasu czas opoznienia dzialania strefy
|
||||
|
||||
short licznik_ZZwa;///< licznik do automatyki załączenia na zwarcie
|
||||
short licznik_PIU;///< licznik pobudzeń sprawdzania obecności napiecia i prądu
|
||||
|
||||
short licznik_Uecho;
|
||||
|
||||
//Wyjscia_rejestratora Rej; ///< dane ostatniego zaklocenia
|
||||
//Time czas_; // moment wystapienia zaklocenia (rejestr tymczasowy - przed zapisem)
|
||||
u32 dl_; // dlugosc czasu trwania zaklocenia (rejestr tymczasowy - przed zapisem)
|
||||
u8 wsk_rej; // nowy zapis rejestracji parametrow zaklocenia (spelnienie kryterium identyfikacji)
|
||||
u8 Pf[6][2]; // pobudzenia stref P[nr strefy][fazowe,miedzyfazowe]
|
||||
u8 Pzf[6]; //pobudzenie stref
|
||||
u8 P;// pobudzenie zbiorcze
|
||||
u8 Zf[6][2]; // zadzialanie strefy
|
||||
u8 Z[6]; // zadzialanie strefy
|
||||
u8 Ws[6]; // wyłaczenie od strefy
|
||||
u8 Zz; // Zadzialanie sygnal zbiorczy
|
||||
u8 W; // wylaczenie sygnal zbiorczy
|
||||
u8 W1; // wylaczenie faza L1
|
||||
u8 W2; // wylaczenie faza L2
|
||||
u8 W3; // wylaczenie faza L3
|
||||
u8 R;//zwarcie z udziałem fazy L1
|
||||
u8 S;//zwarcie z udziałem fazy L2
|
||||
u8 T;//zwarcie z udziałem fazy L3
|
||||
u8 Rbk;//zwarcie z udziałem fazy L1(bezkierunkowo)
|
||||
u8 Sbk;//zwarcie z udziałem fazy L2(bezkierunkowo)
|
||||
u8 Tbk;//zwarcie z udziałem fazy L3(bezkierunkowo)
|
||||
u8 E;//zwarcie z udziałem ziemi
|
||||
u8 jedfaz;//zwarcie jednofazowe
|
||||
u8 W_ON;//wyłącznik zamkniety
|
||||
u8 W1_ON;//wyłącznik zamkniety faza L1
|
||||
u8 W2_ON;//wyłącznik zamkniety faza L2
|
||||
u8 W3_ON;//wyłącznik zamkniety faza L3
|
||||
u8 W_OFF;//wyłącznik otwarty
|
||||
u8 W1_OFF;//wyłącznik otwarty faza L1
|
||||
u8 W2_OFF;//wyłącznik otwarty faza L2
|
||||
u8 W3_OFF;//wyłącznik otwarty faza L3
|
||||
u8 ZZw; //aktywna automatyka załączenia na zwarcie
|
||||
u8 ZZw_start; //spełnienie warunków uruchomienia automatyki załączenia na zwarcie
|
||||
u8 ZZw_PIU; //pobudzenie kryterium napięcie/prąd zamknięcia wyłącznika
|
||||
u8 pob_echo;
|
||||
u8 bl_WSPZ;//zezwolenie na wyłącz od SPZ
|
||||
u8 R1;
|
||||
u8 S1;
|
||||
u8 T1;
|
||||
u8 ZZwP;//wyłączenie od automatyki załączenia na zwarcie
|
||||
u8 wy_blk_lacz;
|
||||
|
||||
u8 wy_bl_LRC;
|
||||
u8 wy_log_odbl;
|
||||
u8 wy_lacze_nad;
|
||||
|
||||
u8 wy_zadz_echa;
|
||||
u8 wy_zezw_lacz;
|
||||
u8 wy_skr_czas_lacz;
|
||||
u8 wy_wyl_lacz;
|
||||
u8 wy_blok_lacz;
|
||||
u8 wy_wydl_czas_lacz;
|
||||
|
||||
u8 wyl_1f;
|
||||
|
||||
u8 Zf_rozwij[6];
|
||||
short liczts_rozwij[6];
|
||||
short liczt_eldz_rozwij[6];
|
||||
short dodaj_rozw[6];
|
||||
|
||||
};
|
||||
|
||||
struct Nastawy_przeliczone_ZDistL_komp
|
||||
{
|
||||
struct Wyjscie1_zdistl_komp wy;
|
||||
|
||||
struct Wyjscia_ZDistA_komp *ZdistA;
|
||||
|
||||
u16 ZZw_st; ///< strefa współpracy z automatyką załączenia na zwarcie
|
||||
u16 adr_PZZw;///< adres zmiennej pobudzenia strefy współpracujacej z automatyką ZZw
|
||||
u16 adr_ZZZw;///< adres zmiennej zadziałania strefy współpracujacej z automatyką ZZw
|
||||
|
||||
u8 echo_on;
|
||||
u8 wyl_od_echa;
|
||||
u8 log_odbl_on;
|
||||
u8 LCR_on;
|
||||
u8 lacze_on;
|
||||
u8 LRC_s[6];
|
||||
u8 zgoda_1faz_s[6];
|
||||
|
||||
u8 Bl_PS[6];
|
||||
u8 ZZw_ON; ///< włączenie automatyki załączenia na zwarcie
|
||||
u8 bl_; ///< wartosc nastawy aktywnosci blokady dzialania 1- blokada aktywna
|
||||
|
||||
u8 rozwij;
|
||||
u8 kryt_IU_ZZW;
|
||||
|
||||
enum _tryb_zezwalajacy tryb_zezw;
|
||||
enum _tryb_blokujacy tryb_blok;
|
||||
enum _tryb_lacza tryb_lacza;
|
||||
|
||||
u8 ktora_strefa;
|
||||
u8 ktora_strefa_nad;
|
||||
u8 strefa_pradu_wstecznego;
|
||||
|
||||
short t_stf[6][2]; ///< czas dzialania strefy
|
||||
float ZZw_ta;///< Czas działania funkcji po zamknięciu wyłącznika
|
||||
float ZZw_Ir;///< Prąd identyfikacji otwarcia wyłącznika
|
||||
float ZZw_Ur;///< Napięcie identyfikacji otwarcia wyłacznika
|
||||
short ZZw_to;///< Czas identyfikacji otwarcia wyłącznika
|
||||
|
||||
short t_LRC;///< Czas podtrzymania w logice odwroconego pradu
|
||||
short t_pod_odbl;///< Czas podtrzymania odblokowania w logice odblokowania
|
||||
short t_lacze_nad;///< Czas przerwy beznapięciowej dla wyłączenia jednofazowego
|
||||
short ts_plus;
|
||||
|
||||
short max_t_nadawania;
|
||||
short czas_wyl_echa;
|
||||
|
||||
float Uecho_pob;
|
||||
float Uecho_odp;
|
||||
|
||||
u8 Zbz[6][2]; ///< zadziałanie bezzwloczne strefy
|
||||
u8 Stf_ON[6]; ///< wlaczenie/odstawienie strefy
|
||||
u8 Stf_W[6]; ///< działanie na wylaczenie/sygnalizacje strefy
|
||||
|
||||
};
|
||||
|
||||
struct ZDistL_logic_komp
|
||||
{
|
||||
|
||||
struct binary_io stan_bl;
|
||||
struct Wyjscia_ZDistA_komp *WE_Zdist;
|
||||
struct binary_io Bl_PS;
|
||||
struct binary_io lacze_OK;
|
||||
struct binary_io lacze_odb;
|
||||
struct binary_io W_ON;
|
||||
struct binary_io zgoda_1f;
|
||||
struct binary_io Z;
|
||||
struct binary_io test;
|
||||
struct binary_io blok_1;
|
||||
struct binary_io blok_1W;
|
||||
struct binary_io blok_2;
|
||||
struct binary_io blok_3;
|
||||
struct binary_io blok_4;
|
||||
struct binary_io blok_5;
|
||||
|
||||
struct binary_io P;
|
||||
struct binary_io P1W;
|
||||
struct binary_io P1;
|
||||
struct binary_io P2;
|
||||
struct binary_io P3;
|
||||
struct binary_io P4;
|
||||
struct binary_io P5;
|
||||
struct binary_io R;
|
||||
struct binary_io S;
|
||||
struct binary_io T;
|
||||
struct binary_io E;
|
||||
struct binary_io Z1W;
|
||||
struct binary_io Z1;
|
||||
struct binary_io Z2;
|
||||
struct binary_io Z3;
|
||||
struct binary_io Z4;
|
||||
struct binary_io Z5;
|
||||
struct binary_io W;
|
||||
struct binary_io W1;
|
||||
struct binary_io W2;
|
||||
struct binary_io W3;
|
||||
struct binary_io bl_LRC;
|
||||
struct binary_io log_odbl;
|
||||
struct binary_io lacze_nad;
|
||||
struct binary_io zzw_akt;
|
||||
struct binary_io blk_lacz;
|
||||
|
||||
struct binary_io deakt;
|
||||
|
||||
//nowe
|
||||
struct binary_io zadz_echa;
|
||||
struct binary_io zezw_lacz;
|
||||
struct binary_io skr_czas_lacz;
|
||||
struct binary_io wyl_lacz;
|
||||
struct binary_io blok_lacz;
|
||||
struct binary_io wydl_czas_lacz;
|
||||
struct binary_io z_zwarcie;
|
||||
|
||||
struct binary_io PZZw;
|
||||
struct binary_io ZZZw;
|
||||
|
||||
struct binary_io P_L1; ///< Pobudzenie sfazy L1
|
||||
struct binary_io P_L2; ///< Pobudzenie sfazy L1
|
||||
struct binary_io P_L3; ///< Pobudzenie sfazy L1
|
||||
struct binary_io P_E; ///< Pobudzenie sfazy L1
|
||||
|
||||
struct binary_io WS1W;
|
||||
struct binary_io WS1;
|
||||
struct binary_io WS2;
|
||||
struct binary_io WS3;
|
||||
struct binary_io WS4;
|
||||
struct binary_io WS5;
|
||||
|
||||
struct binary_io W_1f;
|
||||
|
||||
struct Nastawy_przeliczone_ZDistL_komp nast_;
|
||||
struct dane_wewnetrzne_ZDistL_komp dw;
|
||||
u8 pobudzenia[6][6];
|
||||
u8 P_L1_lub_L2[6];
|
||||
u8 P_L2_lub_L3[6];
|
||||
u8 P_L3_lub_L1[6];
|
||||
|
||||
u8 pob1_flt;
|
||||
short pob1_flt_cnt;
|
||||
u8 pob2_flt;
|
||||
short pob2_flt_cnt;
|
||||
u8 pob3_flt;
|
||||
short pob3_flt_cnt;
|
||||
u8 pob4_flt;
|
||||
short pob4_flt_cnt;
|
||||
|
||||
};
|
||||
|
||||
struct ZDistL_io_komp
|
||||
{
|
||||
u32 stan_bl_in;
|
||||
u32 we_zdist_ptr_in;
|
||||
u32 Bl_PS_in;
|
||||
u32 lacze_OK_in;
|
||||
u32 lacze_odb_in;
|
||||
u32 W_ON_in;
|
||||
u32 zgoda_1f_in;
|
||||
u32 Z_in;
|
||||
u32 test_in;
|
||||
u32 blok_1_in;
|
||||
u32 blok_1W_in;
|
||||
u32 blok_2_in;
|
||||
u32 blok_3_in;
|
||||
u32 blok_4_in;
|
||||
u32 blok_5_in;
|
||||
u32 deakt_in;
|
||||
|
||||
u32 P_out;
|
||||
u32 P1W_out;
|
||||
u32 P1_out;
|
||||
u32 P2_out;
|
||||
u32 P3_out;
|
||||
u32 P4_out;
|
||||
u32 P5_out;
|
||||
u32 R_out;
|
||||
u32 S_out;
|
||||
u32 T_out;
|
||||
u32 E_out;
|
||||
u32 Z1W_out;
|
||||
u32 Z1_out;
|
||||
u32 Z2_out;
|
||||
u32 Z3_out;
|
||||
u32 Z4_out;
|
||||
u32 Z5_out;
|
||||
u32 W_out;
|
||||
u32 W1_out;
|
||||
u32 W2_out;
|
||||
u32 W3_out;
|
||||
u32 bl_LRC_out;
|
||||
u32 log_odbl_out;
|
||||
u32 lacze_nad_out;
|
||||
u32 zzw_akt_out;
|
||||
u32 blk_lacz_out;
|
||||
|
||||
//nowe
|
||||
u32 zadz_echa_out;
|
||||
u32 zezw_lacz_out;
|
||||
u32 skr_czas_lacz_out;
|
||||
u32 wyl_lacz_out;
|
||||
u32 blok_lacz_out;
|
||||
u32 wydl_czas_lacz_out;
|
||||
u32 z_zwarcie_out;
|
||||
|
||||
u32 P_L1_out;
|
||||
u32 P_L2_out;
|
||||
u32 P_L3_out;
|
||||
u32 P_E_out;
|
||||
|
||||
u32 WS1W_out;
|
||||
u32 WS1_out;
|
||||
u32 WS2_out;
|
||||
u32 WS3_out;
|
||||
u32 WS4_out;
|
||||
u32 WS5_out;
|
||||
|
||||
u32 W_1f_out;
|
||||
|
||||
}__attribute__((__packed__));
|
||||
|
||||
struct ZDistL_params_komp
|
||||
{
|
||||
long bity; ///< nastawy bitowe;
|
||||
long Stf1; ///< Sposób działania strefy 1
|
||||
long Stf2; ///< Sposób działania strefy 2
|
||||
long Stf3; ///< Sposób działania strefy 3
|
||||
long Stf4; ///< Sposób działania strefy 4
|
||||
long Stf5; ///< Sposób działania strefy 5
|
||||
long tryb_lacza; ///< tryb lacza
|
||||
long ZZw_st; ///< strefa współpracy z automatyką załączenia na zwarcie
|
||||
long tryb_zezw; ///<tryb zezwalajacy
|
||||
long tryb_blokujacy; ///<tryb blokujacy
|
||||
long strefa_nad;///<wybor strefy do nadawania
|
||||
long strefa_dzial; //<działanie na strefę
|
||||
long lrc_strefa; //<strefa logiku prądu wstecznego
|
||||
|
||||
double ts1LE;///< Czas wyłączenia strefy 1 zwarcia jednofazowe z ziemią
|
||||
double ts1LL;///< Czas wyłączenia strefy 1 zwarcia miedzyfazowe
|
||||
double ts2LE;///< Czas wyłączenia strefy 2 zwarcia jednofazowe z ziemią
|
||||
double ts2LL;///< Czas wyłączenia strefy 2 zwarcia miedzyfazowe
|
||||
double ts3LE;///< Czas wyłączenia strefy 3 zwarcia jednofazowe z ziemią
|
||||
double ts3LL;///< Czas wyłączenia strefy 3 zwarcia miedzyfazowe
|
||||
double ts4LE;///< Czas wyłączenia strefy 4 zwarcia jednofazowe z ziemią
|
||||
double ts4LL;///< Czas wyłączenia strefy 4 zwarcia miedzyfazowe
|
||||
double ts5LE;///< Czas wyłączenia strefy 5 zwarcia jednofazowe z ziemią
|
||||
double ts5LL;///< Czas wyłączenia strefy 5 zwarcia miedzyfazowe
|
||||
double t_LRC;///< Czas podtrzymania w logice odwroconego pradu
|
||||
double t_pod_odbl;///< Czas podtrzymania odblokowania w logice odblokowania
|
||||
double t_lacze_nad;///< Czas przerwy beznapięciowej dla wyłączenia jednofazowego
|
||||
double ZZw_ta;///< Czas działania funkcji po zamknięciu wyłącznika
|
||||
double ZZw_Ir;///< Prąd identyfikacji otwarcia wyłącznika
|
||||
double ZZw_Ur;///< Napięcie identyfikacji otwarcia wyłacznika
|
||||
double ZZw_to;///< Czas identyfikacji otwarcia wyłącznika
|
||||
double U_echa;
|
||||
double ts_plus;
|
||||
double max_t_nadawania;
|
||||
double czas_wyl_echa;
|
||||
|
||||
long Stf0; ///< Sposób działania strefy 1
|
||||
double ts0LE;///< Czas wyłączenia strefy 1 zwarcia jednofazowe z ziemią
|
||||
double ts0LL;///< Czas wyłączenia strefy 1 zwarcia miedzyfazowe
|
||||
|
||||
}__attribute__((__packed__));
|
||||
|
||||
struct ZDistL_args_komp
|
||||
{
|
||||
struct ZDistL_io_komp io;
|
||||
struct ZDistL_params_komp params;
|
||||
// u16 crc;
|
||||
}__attribute__((__packed__));
|
||||
|
||||
extern void ZDistL_komp(void *args, void *logic);
|
||||
extern void ZDistL_100hz_komp(void *args, void *logic);
|
||||
extern int ZDistL_initlog_komp(void *arguments, void *logic);
|
||||
|
||||
#endif /* ZDISTL_H_KOMP_ */
|
||||
17
rezultat.md
Normal file
17
rezultat.md
Normal file
@@ -0,0 +1,17 @@
|
||||
# Wynik analizy zabezpieczenia odleglosciowego
|
||||
|
||||
## Parametry zabezpieczenia
|
||||
- Impedancja linii: R=0.00 Ohm, X=-0.01 Ohm
|
||||
- Kat linii: -76.9 st.
|
||||
- Strefa 1: R=0.00 Ohm, X=-0.01 Ohm (natychmiast)
|
||||
- Strefa 2: R=0.00 Ohm, X=-0.02 Ohm (300ms)
|
||||
- Strefa 3: R=0.01 Ohm, X=-0.03 Ohm (600ms)
|
||||
|
||||
## Wykrycie zwarcia
|
||||
|
||||
**Brak wykrycia zwarcia**
|
||||
|
||||
Zabezpieczenie nie zadzialalo w okresie rejestracji.
|
||||
|
||||
---
|
||||
*Wygenerowano automatycznie przez tester zabezpieczenia odleglosciowego*
|
||||
35
src/cfg_var.c
Normal file
35
src/cfg_var.c
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* cfg_var.c
|
||||
*
|
||||
* Created on: 10-09-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#include "cfg_var.h"
|
||||
#include "misc.h"
|
||||
|
||||
|
||||
const struct config_lookup_table cfg_lut[]=
|
||||
{
|
||||
/* var name, var type, var addr, var size, bit mask, flags */
|
||||
{"klapacz_enabled", ARG_TYPE_BOOL, &dev_cfg.bits, sizeof(dev_cfg.bits), CFG_BIT_KLAPACZ_ENABLED },
|
||||
{"device_bits", ARG_TYPE_LONG, &dev_cfg.bits, sizeof(dev_cfg.bits)},
|
||||
{"mwd0_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[0],sizeof(dev_cfg.mwd_ac_mask[0]), 0, NEED_RELOAD_IC},
|
||||
{"mwd1_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[1],sizeof(dev_cfg.mwd_ac_mask[1]), 0, NEED_RELOAD_IC},
|
||||
{"mwd2_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[2],sizeof(dev_cfg.mwd_ac_mask[2]), 0, NEED_RELOAD_IC},
|
||||
{"mwd3_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[3],sizeof(dev_cfg.mwd_ac_mask[3]), 0, NEED_RELOAD_IC},
|
||||
{"mwd4_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[4],sizeof(dev_cfg.mwd_ac_mask[4]), 0, NEED_RELOAD_IC},
|
||||
{"mwd5_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[5],sizeof(dev_cfg.mwd_ac_mask[5]), 0, NEED_RELOAD_IC},
|
||||
{"mwd6_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[6],sizeof(dev_cfg.mwd_ac_mask[6]), 0, NEED_RELOAD_IC},
|
||||
{"mwd7_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[7],sizeof(dev_cfg.mwd_ac_mask[7]), 0, NEED_RELOAD_IC},
|
||||
{"mwd8_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[8],sizeof(dev_cfg.mwd_ac_mask[8]), 0, NEED_RELOAD_IC},
|
||||
{"mwd9_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[9],sizeof(dev_cfg.mwd_ac_mask[9]), 0, NEED_RELOAD_IC},
|
||||
{"mwd10_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[10],sizeof(dev_cfg.mwd_ac_mask[10]), 0, NEED_RELOAD_IC},
|
||||
{"mwd11_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[11],sizeof(dev_cfg.mwd_ac_mask[11]), 0, NEED_RELOAD_IC},
|
||||
{"mwd12_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[12],sizeof(dev_cfg.mwd_ac_mask[12]), 0, NEED_RELOAD_IC},
|
||||
{"mwd13_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[13],sizeof(dev_cfg.mwd_ac_mask[13]), 0, NEED_RELOAD_IC},
|
||||
{"mwd14_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[14],sizeof(dev_cfg.mwd_ac_mask[14]), 0, NEED_RELOAD_IC},
|
||||
{"mwd15_ac_bits", ARG_TYPE_LONG,&dev_cfg.mwd_ac_mask[15],sizeof(dev_cfg.mwd_ac_mask[15]), 0, NEED_RELOAD_IC},
|
||||
};
|
||||
|
||||
const unsigned int cfg_lut_elements = sizeof(cfg_lut)/sizeof(struct config_lookup_table);
|
||||
14
src/cfg_var.h
Normal file
14
src/cfg_var.h
Normal file
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* cfg_var.h
|
||||
*
|
||||
* Created on: 10-09-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#ifndef CFG_VAR_H_
|
||||
#define CFG_VAR_H_
|
||||
|
||||
extern const struct config_lookup_table cfg_lut[];
|
||||
extern const unsigned int cfg_lut_elements;
|
||||
|
||||
#endif /* CFG_VAR_H_ */
|
||||
790
src/comm.c
Normal file
790
src/comm.c
Normal file
@@ -0,0 +1,790 @@
|
||||
/*
|
||||
* comm.c
|
||||
*
|
||||
* Created on: 01-08-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
|
||||
#include <xdc/std.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <xdc/runtime/Error.h>
|
||||
#include <xdc/runtime/System.h>
|
||||
|
||||
#include <ti/sysbios/hal/Timer.h>
|
||||
#include <ti/sysbios/BIOS.h>
|
||||
#include <ti/sysbios/knl/Task.h>
|
||||
#include <ti/sysbios/knl/Clock.h>
|
||||
#include <ti/sysbios/knl/Semaphore.h>
|
||||
|
||||
#include <ti/ipc/Ipc.h>
|
||||
#include <ti/ipc/MultiProc.h>
|
||||
#include <ti/ipc/MessageQ.h>
|
||||
#include <ti/ipc/Notify.h>
|
||||
|
||||
#include "version.h"
|
||||
#include "comm.h"
|
||||
#include "misc.h"
|
||||
#include "cfg_var.h"
|
||||
#include "tdefs.h"
|
||||
#include "logman.h"
|
||||
#include "spi.h"
|
||||
#include "logic_elements/elements.h"
|
||||
#include "logic_elements/events_reg.h"
|
||||
#include "logic_elements/dfr.h"
|
||||
#include "logic_elements/ddr.h"
|
||||
#include "logic_elements/measurand.h"
|
||||
#include "logic_elements/leds_drv.h"
|
||||
#include "logic_elements/virt_in_drv.h"
|
||||
#include "logic_elements/dfr_drv.h"
|
||||
#include "logic_elements/ddr_drv.h"
|
||||
#include "logic_elements/rec_float.h"
|
||||
#include "logic_elements/rec_an.h"
|
||||
#include "logic_elements/rec_buf.h"
|
||||
#include "logic_elements/analog_in.h"
|
||||
#include "logic_elements/event.h"
|
||||
#include "logic_elements/events_reg.h"
|
||||
#include "logic_elements/dev_ctrl.h"
|
||||
#include "logic_elements/an_gen.h"
|
||||
#include "logic_elements/events_reg.h"
|
||||
#include "logic_elements/mki7.h"
|
||||
#include "logic_elements/mki7_2.h"
|
||||
#include "config.h"
|
||||
/// ethernet
|
||||
#include "ethernet/ports/am1808/include/lwiplib.h"
|
||||
#include "ethernet/emac.h"
|
||||
#include "ports/am1808/include/netif/sitaraif.h"
|
||||
#include <ti/sysbios/hal/Hwi.h>
|
||||
///
|
||||
|
||||
Timer_Handle tick_timer_handle;
|
||||
u32 tick_timer_period;
|
||||
static MessageQ_Handle msgqueue_local;
|
||||
struct notify_data notify;
|
||||
struct broadcast_info bcast_nfo;
|
||||
volatile struct ping_info ping_nfo;
|
||||
|
||||
struct eth_data eth = { .flags = 0 };
|
||||
|
||||
volatile u8 saved_bank = 0;
|
||||
|
||||
//u8 time_good=0;
|
||||
|
||||
Void commFxn(UArg a0, UArg a1)
|
||||
{
|
||||
struct timeval cur_time_old;
|
||||
int status = 0;
|
||||
UInt16 remoteProcId;
|
||||
MessageQ_Params msgqParams;
|
||||
struct msg_data *msg;
|
||||
int ret;
|
||||
u8 may_sync_hw;
|
||||
u8 may_sync_sw;
|
||||
MessageQ_QueueId msgqueue_id_remote;
|
||||
int offset;
|
||||
struct parsed_cfg_transport_line *line = (struct parsed_cfg_transport_line *)shared_buf;
|
||||
int i;
|
||||
float tmp;
|
||||
int tmpstate;
|
||||
u8 *off;
|
||||
char firm_ver[40];
|
||||
u8 first_tsync=1;
|
||||
u16 kob_bin=0;
|
||||
|
||||
snprintf(firm_ver,sizeof(firm_ver),SW_VER" %u",(u32)ic->fpga_verl|((u32)ic->fpga_verh<<16));
|
||||
|
||||
tick_timer_handle = Clock_getTimerHandle();
|
||||
tick_timer_period = Timer_getPeriod(tick_timer_handle);
|
||||
dbg.tick_period = tick_timer_period;
|
||||
dbg.logman_buf_capacity = sizeof(log_manager.buf);
|
||||
|
||||
do
|
||||
{
|
||||
Task_sleep(1);
|
||||
status = Ipc_start();
|
||||
}
|
||||
while(status == Ipc_E_NOTREADY);
|
||||
|
||||
remoteProcId = MultiProc_getId("HOST");
|
||||
|
||||
do
|
||||
{
|
||||
Task_sleep(1);
|
||||
status = Ipc_attach(remoteProcId);
|
||||
} while(status == Ipc_E_NOTREADY);
|
||||
|
||||
MessageQ_Params_init(&msgqParams);
|
||||
|
||||
msgqueue_local = MessageQ_create("MsgQdsp", &msgqParams);
|
||||
|
||||
if(msgqueue_local == NULL)
|
||||
System_printf("queue failed\n");
|
||||
else
|
||||
System_printf("queue succ\n");
|
||||
|
||||
// notify subsystem from dsp to arm
|
||||
|
||||
notify.lineId = 0;
|
||||
notify.eventId = 7;
|
||||
notify.remoteProcId = remoteProcId;
|
||||
|
||||
do
|
||||
{
|
||||
status = Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_INIT, TRUE);
|
||||
|
||||
if (status == Notify_E_EVTNOTREGISTERED)
|
||||
Task_sleep(10);
|
||||
|
||||
} while (status == Notify_E_EVTNOTREGISTERED);
|
||||
|
||||
for(;;)
|
||||
{
|
||||
status = MessageQ_get(msgqueue_local, (MessageQ_Msg *)&msg, MessageQ_FOREVER);
|
||||
if(status == 0)
|
||||
{
|
||||
msgqueue_id_remote = MessageQ_getReplyQueue(msg);
|
||||
switch(msg->cmd)
|
||||
{
|
||||
case DSP_CMD_INIT_COMM:
|
||||
msg->p1 = CMD_ACK;
|
||||
if(msg->p2 == 0xAA55AA55) // neg pps
|
||||
ic->sync_reg=0;
|
||||
|
||||
while(!spi_fram_restored)
|
||||
Task_sleep(100); // wait for spi first read
|
||||
|
||||
msg->p3 = saved_bank;
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_ANALOG_BUF:
|
||||
analog_buf_card = msg->p1;
|
||||
analog_buf_channel = msg->p2;
|
||||
|
||||
for(i=0;i<127;i++)
|
||||
analog_buf[i]=(short)bus_an_samples_buf[analog_buf_card][analog_buf_channel][(bus_an_cur_sample_num+i)%(SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2)] - 32767;
|
||||
|
||||
memcpy((char*)shared_buf,(char*)analog_buf,sizeof(analog_buf));
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = sizeof(analog_buf);
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_MEASURANDS:
|
||||
|
||||
switch(msg->p1)
|
||||
{
|
||||
case 0:
|
||||
for(i=0;i<measurands.count;i++)
|
||||
{
|
||||
*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
|
||||
/* if(i<=6)
|
||||
tmp=debug_size[i];
|
||||
else*/
|
||||
tmp=*(measurands.value[i]);
|
||||
memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
for(i=0;i<measurands.count;i++)
|
||||
{
|
||||
*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
|
||||
tmp=*(measurands.value_pri[i]);
|
||||
memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
for(i=0;i<measurands.count;i++)
|
||||
{
|
||||
*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
|
||||
tmp=*(measurands.value_sec[i]);
|
||||
memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
for(i=0;i<measurands.count;i++)
|
||||
{
|
||||
*((char *)shared_buf+(i<<2)+i) = measurands.id[i];
|
||||
tmp=*(measurands.value[i]);
|
||||
memcpy((char *)shared_buf+(i<<2)+i+1,(char *)&tmp,sizeof(float));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
msg->p2 = sizeof(shared_buf);
|
||||
msg->p3 = measurands.count;
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_FWVER:
|
||||
memcpy((char *)shared_buf,firm_ver,40);
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = sizeof(shared_buf);
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_NET_BUF:
|
||||
offset=0;
|
||||
// maybe use semaphore to avoid race condition
|
||||
memcpy((char*)shared_buf,(char*)&log_manager.nets_data[msg->p1],256);
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = offset;
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_IO_BUF:
|
||||
offset=0;
|
||||
// maybe use semaphore to avoid race condition
|
||||
//memcpy((char*)shared_buf,(char*)ic->bin_in,sizeof(ic->bin_in));
|
||||
//offset=sizeof(ic->bin_in);
|
||||
memcpy((char*)shared_buf,(char*)bus_bin_data,sizeof(bus_bin_data));
|
||||
offset=sizeof(bus_bin_data);
|
||||
memcpy((char*)shared_buf+offset,(char *)ic->out_set,sizeof(ic->out_set));
|
||||
offset+=sizeof(ic->out_set);
|
||||
memcpy((char*)shared_buf+offset,(char *)&ic->kob_an,12); // kobs and errs
|
||||
offset+=2;
|
||||
|
||||
kob_bin=ic->kob_bin;
|
||||
for(i=0;i<8;i++)
|
||||
{
|
||||
if(mwd32_mask & (1<<i))
|
||||
{
|
||||
if(kob_bin & (1<<i))
|
||||
kob_bin|=(1<<(i+8));
|
||||
else
|
||||
kob_bin&=~(1<<(i+8));
|
||||
}
|
||||
}
|
||||
|
||||
memcpy((char*)shared_buf+offset,(char *)&kob_bin,2); // kobs and errs
|
||||
offset+=2;
|
||||
|
||||
memcpy((char*)shared_buf+offset,(char *)&ic->kob_out,8); // kobs and errs
|
||||
offset+=8;
|
||||
|
||||
|
||||
|
||||
|
||||
memcpy((char*)shared_buf+offset,(char *)&samples_dropped,2);
|
||||
offset+=2;
|
||||
memcpy((char*)shared_buf+offset,(char*)bus_bin_data_ench,sizeof(bus_bin_data_ench));
|
||||
offset+=sizeof(bus_bin_data_ench);
|
||||
|
||||
|
||||
for(i=0;i<8;i++)
|
||||
{
|
||||
if(mwd32_mask & (1<<i))
|
||||
{
|
||||
if(ic->kob_bin & (1<<i))
|
||||
kob_bin_ench|=(1<<i) | (1<<(i+8));
|
||||
else
|
||||
kob_bin_ench&=~((1<<i) | (1<<(i+8)));
|
||||
}
|
||||
else
|
||||
kob_bin_ench&=~((1<<i) | (1<<(i+8)));
|
||||
}
|
||||
|
||||
memcpy((char*)shared_buf+offset,(char*)&kob_bin_ench,sizeof(kob_bin_ench));
|
||||
offset+=sizeof(kob_bin_ench);
|
||||
|
||||
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = offset;
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_LEDS_VIRT_IN:
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = 16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2)+8;//+MAX_BIN_CARDS;
|
||||
memcpy((char*)shared_buf+0,(char *)&led_states,4);
|
||||
memcpy((char*)shared_buf+4,(char *)&led_blink_states,4);
|
||||
memcpy((char*)shared_buf+8,(char *)&virt_in_mask,4);
|
||||
memcpy((char*)shared_buf+12,(char *)&virt_in_states,4);
|
||||
memcpy((u8*)shared_buf+16,(u8*)force_bus_bin_data,MAX_BIN_CARDS);
|
||||
memcpy((u8*)shared_buf+16+MAX_BIN_CARDS,(u8*)force_bus_out_data,MAX_OUT_CARDS*2);
|
||||
memcpy((char*)shared_buf+16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2),(char *)&virt_in2_mask,4);
|
||||
memcpy((char*)shared_buf+16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2)+4,(char *)&virt_in2_states,4);
|
||||
|
||||
// memcpy((char*)shared_buf+16+MAX_BIN_CARDS+(MAX_OUT_CARDS*2)+4+4,(char *)&force_bus_bin_data_ench,MAX_BIN_CARDS);
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_GI:
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = sizeof(shared_buf);
|
||||
|
||||
if(ev_reg_log==NULL)
|
||||
{
|
||||
msg->p3 = 0;
|
||||
break;
|
||||
}
|
||||
else
|
||||
msg->p3 = ev_reg_log->events_count;
|
||||
|
||||
if(msg->p3>1024)
|
||||
msg->p3=1024;
|
||||
|
||||
for(i=0;i<msg->p3;i++)
|
||||
{
|
||||
struct event_args *ev_args;
|
||||
struct event_logic *ev_log;
|
||||
u32 data;
|
||||
|
||||
ev_args = (struct event_args *)log_manager.log_element[ev_reg_log->element_num[i]].fun_args_ptr;
|
||||
ev_log = (struct event_logic *)log_manager.log_element[ev_reg_log->element_num[i]].fun_log_ptr;
|
||||
|
||||
data=((u32)ev_args->params.fun<<16)|((u32)ev_args->params.inf<<8)|ev_log->prev_state;
|
||||
memcpy((char*)shared_buf+(i<<2),(char *)&data,4);
|
||||
}
|
||||
break;
|
||||
|
||||
case DSP_CMD_SET_VIRT_IN:
|
||||
tmpstate=virt_in_states & ~msg->p1;
|
||||
virt_in_states = tmpstate|(msg->p1 & msg->p2);
|
||||
break;
|
||||
|
||||
case DSP_CMD_SET_VIRT_IN2:
|
||||
tmpstate=virt_in2_states & ~msg->p1;
|
||||
virt_in2_states = tmpstate|(msg->p1 & msg->p2);
|
||||
break;
|
||||
|
||||
case DSP_CMD_FORCE_OUT_STATES:
|
||||
msg->p1 = CMD_ACK;
|
||||
msg->p2 = dev_ctrl_state;
|
||||
memcpy((u8*)force_bus_out_data,(u8*)shared_buf,MAX_OUT_CARDS*2);
|
||||
break;
|
||||
|
||||
case DSP_CMD_FORCE_BIN_STATES:
|
||||
memcpy((u8*)force_bus_bin_data,(u8*)shared_buf,MAX_BIN_CARDS);
|
||||
if(msg->p1==0xBEEF)
|
||||
memcpy((u8*)force_bus_bin_data_ench,(u8*)shared_buf+MAX_BIN_CARDS,MAX_BIN_CARDS);
|
||||
msg->p1 = CMD_ACK;
|
||||
msg->p2 = dev_ctrl_state;
|
||||
break;
|
||||
|
||||
case DSP_CMD_FORCE_AN_STATES:
|
||||
msg->p1 = CMD_ACK;
|
||||
msg->p2 = dev_ctrl_state;
|
||||
memcpy((u8*)&genpar,(u8*)shared_buf,sizeof(genpar));
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_AN_STATES:
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = sizeof(genpar);
|
||||
memcpy((u8*)shared_buf,(u8*)&genpar,sizeof(genpar));
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_SHARED_BUF:
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = sizeof(shared_buf);
|
||||
break;
|
||||
|
||||
case DSP_CMD_UPDATE_CFG:
|
||||
msg->p1 = CMD_ERR;
|
||||
|
||||
for(i=0;i<cfg_lut_elements;i++)
|
||||
{
|
||||
if(!strcmp(cfg_lut[i].name,line->name))
|
||||
{
|
||||
if(cfg_lut[i].type == line->type)
|
||||
{
|
||||
switch(line->type)
|
||||
{
|
||||
case ARG_TYPE_BOOL:
|
||||
switch(cfg_lut[i].size)
|
||||
{
|
||||
case sizeof(unsigned char):
|
||||
if(line->bool_val)
|
||||
*((unsigned char*)cfg_lut[i].addr)|=cfg_lut[i].bit_mask;
|
||||
else
|
||||
*((unsigned char*)cfg_lut[i].addr)&=~cfg_lut[i].bit_mask;
|
||||
msg->p1=CMD_ACK;
|
||||
break;
|
||||
|
||||
case sizeof(unsigned short):
|
||||
if(line->bool_val)
|
||||
*((unsigned short*)cfg_lut[i].addr)|=cfg_lut[i].bit_mask;
|
||||
else
|
||||
*((unsigned short*)cfg_lut[i].addr)&=~cfg_lut[i].bit_mask;
|
||||
msg->p1=CMD_ACK;
|
||||
break;
|
||||
|
||||
case sizeof(unsigned int):
|
||||
if(line->bool_val)
|
||||
*((unsigned int*)cfg_lut[i].addr)|=cfg_lut[i].bit_mask;
|
||||
else
|
||||
*((unsigned int*)cfg_lut[i].addr)&=~cfg_lut[i].bit_mask;
|
||||
msg->p1=CMD_ACK;
|
||||
break;
|
||||
|
||||
default:
|
||||
msg->p1=CMD_ERR;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARG_TYPE_DOUBLE:
|
||||
msg->p1=CMD_ACK;
|
||||
memcpy((char *)cfg_lut[i].addr,(char *)&line->double_val,cfg_lut[i].size);
|
||||
break;
|
||||
case ARG_TYPE_LONG:
|
||||
msg->p1=CMD_ACK;
|
||||
memcpy((char *)cfg_lut[i].addr,(char *)&line->long_val,cfg_lut[i].size);
|
||||
break;
|
||||
case ARG_TYPE_TEXT:
|
||||
msg->p1=CMD_ACK;
|
||||
memcpy((char *)cfg_lut[i].addr,(char *)line->text_val,cfg_lut[i].size);
|
||||
break;
|
||||
default:
|
||||
msg->p1=CMD_ERR;
|
||||
break;
|
||||
}
|
||||
|
||||
if(msg->p1==CMD_ACK && (cfg_lut[i].flags & NEED_RELOAD_IC))
|
||||
reload_ic_cfg();
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
msg->p1=CMD_ERR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_REG_INF:
|
||||
memcpy((u8*)shared_buf,(u8*)®s,sizeof(regs));
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = offset;
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_DDR_REG_INF:
|
||||
memcpy((u8*)shared_buf,(u8*)&ddr_regs,sizeof(ddr_regs));
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
msg->p2 = offset;
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_REG_MULTIPLIERS:
|
||||
if(dfr_drv_log_ptr == NULL) // dfr driver not initialized?
|
||||
{
|
||||
msg->p1 = CMD_ERR;
|
||||
break;
|
||||
}
|
||||
|
||||
msg->p1 = CMD_ACK;
|
||||
off = (u8 *)shared_buf;
|
||||
|
||||
msg->p2 = dfr_drv_log_ptr->an_count;
|
||||
|
||||
|
||||
for(i=0;i<dfr_drv_log_ptr->an_count;i++)
|
||||
{
|
||||
struct rec_an_logic *an_log;
|
||||
struct rec_buf_logic *an_buf_log;
|
||||
struct rec_float_args *float_args;
|
||||
struct rec_float_logic *float_log;
|
||||
struct dfr_an_comtrade_params an_comtrade_params;
|
||||
|
||||
if(dfr_drv_log_ptr->element_num[i] & ELEMENT_IS_REC_FLOAT)
|
||||
{
|
||||
float_args = (struct rec_float_args *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_args_ptr;
|
||||
float_log = (struct rec_float_logic *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
|
||||
an_comtrade_params.multiplier=float_log->mul;
|
||||
an_comtrade_params.primary=float_args->params.pierw;
|
||||
an_comtrade_params.secondary=float_args->params.wtor;
|
||||
an_comtrade_params.unit=float_args->params.jednostka | AN_IS_FLOAT;
|
||||
}
|
||||
else if(dfr_drv_log_ptr->element_num[i] & ELEMENT_IS_REC_BUF)
|
||||
{
|
||||
an_buf_log = (struct rec_buf_logic *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
|
||||
an_comtrade_params.multiplier=an_buf_log->an_params->multiplier;
|
||||
an_comtrade_params.primary=an_buf_log->an_params->znam_pierw;
|
||||
an_comtrade_params.secondary=an_buf_log->an_params->znam_wtor;
|
||||
an_comtrade_params.unit=an_buf_log->an_params->jednostka & 0x7FFFFFFF;
|
||||
}
|
||||
else
|
||||
{
|
||||
an_log = (struct rec_an_logic *)log_manager.log_element[dfr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
|
||||
an_comtrade_params.multiplier=an_log->an_params->multiplier;
|
||||
an_comtrade_params.primary=an_log->an_params->znam_pierw;
|
||||
an_comtrade_params.secondary=an_log->an_params->znam_wtor;
|
||||
an_comtrade_params.unit=an_log->an_params->jednostka & 0x7FFFFFFF;
|
||||
}
|
||||
|
||||
memcpy(off,(u8 *)&an_comtrade_params,sizeof(an_comtrade_params));
|
||||
off+=sizeof(an_comtrade_params);
|
||||
}
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_REG_MULTIPLIERS_DDR:
|
||||
if(ddr_drv_log_ptr == NULL) // ddr driver not initialized?
|
||||
{
|
||||
msg->p1 = CMD_ERR;
|
||||
break;
|
||||
}
|
||||
|
||||
msg->p1 = CMD_ACK;
|
||||
off = (u8 *)shared_buf;
|
||||
|
||||
msg->p2 = ddr_drv_log_ptr->an_count;
|
||||
|
||||
for(i=0;i<ddr_drv_log_ptr->an_count;i++)
|
||||
{
|
||||
struct rec_float_args *float_args;
|
||||
struct rec_float_logic *float_log;
|
||||
struct dfr_an_comtrade_params an_comtrade_params;
|
||||
|
||||
if(ddr_drv_log_ptr->element_num[i] & ELEMENT_IS_REC_FLOAT)
|
||||
{
|
||||
float_args = (struct rec_float_args *)log_manager.log_element[ddr_drv_log_ptr->element_num[i] & 0x3FFF].fun_args_ptr;
|
||||
float_log = (struct rec_float_logic *)log_manager.log_element[ddr_drv_log_ptr->element_num[i] & 0x3FFF].fun_log_ptr;
|
||||
an_comtrade_params.multiplier=float_log->mul;
|
||||
an_comtrade_params.primary=float_args->params.pierw;
|
||||
an_comtrade_params.secondary=float_args->params.wtor;
|
||||
an_comtrade_params.unit=float_args->params.jednostka | AN_IS_FLOAT;
|
||||
}
|
||||
memcpy(off,(u8 *)&an_comtrade_params,sizeof(an_comtrade_params));
|
||||
off+=sizeof(an_comtrade_params);
|
||||
}
|
||||
break;
|
||||
|
||||
case DSP_CMD_ACK_REG:
|
||||
if(msg->p1<MAX_REG_BANKS)
|
||||
{
|
||||
if(regs.bank[msg->p1].state == BANK_FILLED)
|
||||
regs.bank[msg->p1].state = BANK_EMPTY;
|
||||
}
|
||||
break;
|
||||
|
||||
case DSP_CMD_ACK_DDR_REG:
|
||||
if(msg->p1<DDR_MAX_REG_BANKS)
|
||||
{
|
||||
if(ddr_regs.bank[msg->p1].state == BANK_FILLED)
|
||||
ddr_regs.bank[msg->p1].state = BANK_EMPTY;
|
||||
}
|
||||
break;
|
||||
|
||||
case DSP_CMD_CLEAR_RELAYS:
|
||||
for(i=0;i<MAX_OUT_CARDS;i++)
|
||||
ic->out_set[i]=0;
|
||||
msg->p1 = CMD_ACK;
|
||||
break;
|
||||
|
||||
case DSP_CMD_TIME_SYNC:
|
||||
may_sync_hw = (first_tsync || (msg->p2<=950000 && msg->p2>=50000 && cur_time.tv_usec>=10 && cur_time.tv_usec<=990))?1:0;
|
||||
may_sync_sw = (first_tsync || (msg->p2<=950000 && msg->p2>=50000 && cur_time_sw.tv_usec>=10 && cur_time_sw.tv_usec<=990))?1:0;
|
||||
|
||||
timesync_method=msg->p3 & 0xFF;
|
||||
timesync_bits=(msg->p3>>8) & 0xFF;
|
||||
|
||||
if(timesync_bits & CFG_TSYNC_USE_SWCLK)
|
||||
cur_time_old = cur_time_sw;
|
||||
else
|
||||
cur_time_old = cur_time;
|
||||
|
||||
if((timesync_method!=SYNC_METHOD_IRIG_B && timesync_method!=SYNC_METHOD_IRIG_B_ZPRAE && (timesync_method!=SYNC_METHOD_CUSTOM || !(timesync_bits & CFG_TSYNC_FROM_DSP)))||first_tsync)
|
||||
{
|
||||
if(may_sync_sw)
|
||||
{
|
||||
cur_time_sw.tv_sec = msg->p1;
|
||||
if(!(timesync_bits & CFG_TSYNC_USE_SWPPS) || pps3_timeout_cnt>60000)
|
||||
cur_time_sw.tv_usec = msg->p2 / 1000;
|
||||
}
|
||||
|
||||
if(may_sync_hw)
|
||||
{
|
||||
cur_time.tv_sec=msg->p1;
|
||||
first_tsync=0;
|
||||
if(!ext_sync)
|
||||
cur_time.tv_usec=msg->p2 / 1000;
|
||||
}
|
||||
}
|
||||
|
||||
msg->p1=cur_time_old.tv_sec;
|
||||
msg->p2=cur_time_old.tv_usec;
|
||||
msg->p3=(dev_ctrl_state&DEV_CTRL_STATE_IRIGB_FIX_OK)?1:0;
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_CFG_STATE:
|
||||
if(msg->p1==SET_CFG_CHANGE)
|
||||
dev_ctrl_state|=DEV_CTRL_STATE_CFG_CHANGE;
|
||||
else if(msg->p1==SET_CFG_ERR)
|
||||
dev_ctrl_state|=DEV_CTRL_STATE_CFG_ERR;
|
||||
else if(msg->p1==SET_CFG_OK)
|
||||
dev_ctrl_state&=~DEV_CTRL_STATE_CFG_ERR;
|
||||
|
||||
if(msg->p2 & 0x01)
|
||||
dev_ctrl_state|=DEV_CTRL_STATE_PTP_OK;
|
||||
else
|
||||
dev_ctrl_state&=~DEV_CTRL_STATE_PTP_OK;
|
||||
if(msg->p2 & 0x02)
|
||||
dev_ctrl_state|=DEV_CTRL_STATE_NTP_OK;
|
||||
else
|
||||
dev_ctrl_state&=~DEV_CTRL_STATE_NTP_OK;
|
||||
|
||||
mki7_sfplinks=msg->p3;
|
||||
mki7_2_sfplinks=msg->p3>>8;
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_SET_EVENT_FILTER:
|
||||
events_reg_filter_act = msg->p1 ? 1 : 0;
|
||||
events_reg_filter_period = msg->p2 > 65535 ? 65535 : msg->p2;
|
||||
events_reg_filter_trans_limit = msg->p3 > 127 ? 127 : msg->p3;
|
||||
break;
|
||||
|
||||
case DSP_CMD_LOGMAN_STOP:
|
||||
logman_stop();
|
||||
msg->p1 = CMD_ACK;
|
||||
break;
|
||||
|
||||
case DSP_CMD_LOGMAN_RESET:
|
||||
logman_reset();
|
||||
msg->p1 = CMD_ACK;
|
||||
break;
|
||||
|
||||
case DSP_CMD_LOGMAN_PUSHFUN:
|
||||
if(!(ret=logman_pushfunc(msg->p2,(void*)shared_buf,msg->p3)))
|
||||
msg->p1 = CMD_ACK;
|
||||
else
|
||||
{
|
||||
msg->p1 = CMD_ERR;
|
||||
msg->p2 = ret;
|
||||
}
|
||||
|
||||
msg->p3 = (u32)log_manager.cur_buf_ptr;
|
||||
break;
|
||||
|
||||
case DSP_CMD_LOGMAN_START:
|
||||
saved_bank = msg->p1>5?0:msg->p1;
|
||||
if(!(ret = logman_start()))
|
||||
msg->p1 = CMD_ACK;
|
||||
else
|
||||
{
|
||||
msg->p1 = CMD_ERR;
|
||||
msg->p2 = ret;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_DEBUGLOG:
|
||||
if(msg->p1)
|
||||
dev_ctrl_state|=DEV_CTRL_STATE_SD_ERR;
|
||||
else if(dev_ctrl_state & DEV_CTRL_STATE_SD_ERR)
|
||||
dev_ctrl_state&=~DEV_CTRL_STATE_SD_ERR;
|
||||
|
||||
dev_ctrl_state&=0x0000FFFF;
|
||||
dev_ctrl_state|=(msg->p2&0xFFFF)<<16;
|
||||
|
||||
msg->p1 = CMD_ACK;
|
||||
dbg.delta_period = ic->delta_period_50M;
|
||||
dbg.phase_corr = ic->phase_corr;
|
||||
dbg.sync_reg = ic->sync_reg;
|
||||
dbg.max_elements = MAX_LOG_ELEMENTS;
|
||||
dbg.nets_bufsize = LOGMAN_NETSDATA_SIZE;
|
||||
memcpy((u8*)shared_buf,(u8*)&dbg,sizeof(dbg));
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_EV_BUF:
|
||||
msg->p1 = CMD_ACK;
|
||||
memcpy((u8*)shared_buf,(u8*)&ev_db,sizeof(ev_db));
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_PROFILE_BUF:
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
memcpy((u8*)shared_buf,(u8*)&log_profile,sizeof(log_profile));
|
||||
break;
|
||||
|
||||
case DSP_CMD_GET_LOGIC_EL_PARAMS:
|
||||
msg->p1 = (Uint32)shared_buf;
|
||||
|
||||
i=0;
|
||||
while(log_elements[i].id!=EOF_ELEMENT && log_elements[i].id<1024 && i<2048)
|
||||
{
|
||||
shared_buf[i]=((u32)log_elements[i].log_size<<16) |(u32)log_elements[i].args_size;
|
||||
i++;
|
||||
}
|
||||
|
||||
msg->p2=i;
|
||||
break;
|
||||
|
||||
case DSP_CMD_START_PROFILER:
|
||||
memset(&log_profile,0,sizeof(log_profile));
|
||||
dbg.logman_cycle_time_max=0;
|
||||
log_manager.status|=LOGMAN_STATUS_PROFILING;
|
||||
msg->p1 = CMD_ACK;
|
||||
break;
|
||||
|
||||
case DSP_CMD_STOP_PROFILER:
|
||||
log_manager.status&=~LOGMAN_STATUS_PROFILING;
|
||||
msg->p1 = CMD_ACK;
|
||||
break;
|
||||
|
||||
case DSP_CMD_ETH_ON:
|
||||
memcpy(eth.hwaddr,(char*)shared_buf,sizeof(eth.hwaddr));
|
||||
memcpy(eth.name,(char*)shared_buf+sizeof(eth.hwaddr),sizeof(eth.name));
|
||||
memcpy((char *)ð.dev_no,(char*)shared_buf+sizeof(eth.hwaddr)+sizeof(eth.name),sizeof(eth.dev_no));
|
||||
memcpy((char *)ð.unicast_ip,(char*)shared_buf+sizeof(eth.hwaddr)+sizeof(eth.name)+sizeof(eth.dev_no),sizeof(eth.unicast_ip));
|
||||
|
||||
eth.ip=msg->p1;
|
||||
eth.netmask=msg->p2;
|
||||
eth.gateway=msg->p3;
|
||||
eth.flags|=ETH_GOT_SETTINGS;
|
||||
|
||||
lwIPInit(0, eth.hwaddr, eth.ip, eth.netmask, eth.gateway, IPADDR_USE_STATIC);
|
||||
|
||||
memcpy((u8 *)bcast_nfo.id,"ZP6",3);
|
||||
memcpy((u8 *)bcast_nfo.dev_name,"DSP ",4);
|
||||
memcpy((u8 *)bcast_nfo.dev_name+4,eth.name,16);
|
||||
bcast_nfo.dev_name[20]=0;
|
||||
bcast_nfo.mlb_type=ZPRAE_MLB12_TYPE;
|
||||
bcast_nfo.dev_type=0;
|
||||
bcast_nfo.dev_num=eth.dev_no;
|
||||
memcpy((u8 *)bcast_nfo.mac,eth.hwaddr,6);
|
||||
|
||||
eth.flags|=ETH_INITIALIZED;
|
||||
Hwi_enableInterrupt(10);
|
||||
Hwi_enableInterrupt(11);
|
||||
/*
|
||||
EMACTxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 0, 0);
|
||||
EMACRxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 0, 0);
|
||||
Hwi_disableInterrupt(10);
|
||||
Hwi_disableInterrupt(11);
|
||||
sitaraif_save_descriptors();
|
||||
*/
|
||||
msg->p1 = CMD_ACK;
|
||||
break;
|
||||
|
||||
case DSP_CMD_ETH_OFF:
|
||||
msg->p1 = CMD_ACK;
|
||||
//if(eth.flags & ETH_ACTIVE)
|
||||
{
|
||||
//EMACTxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 1, 1);
|
||||
//EMACRxIntPulseDisable(EMAC_0_BASE, EMAC_CTRL_0_BASE, 1, 1);
|
||||
Hwi_disableInterrupt(10);
|
||||
Hwi_disableInterrupt(11);
|
||||
eth.flags&=~ETH_ACTIVE;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case DSP_CMD_ETH_OFF_ACK:
|
||||
msg->p1 = CMD_ACK;
|
||||
eth.flags|=ETH_OFF_ACK;
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
msg->cmd = CMD_ERR;
|
||||
msg->p1 = CMD_ERR;
|
||||
break;
|
||||
}
|
||||
|
||||
MessageQ_put(msgqueue_id_remote, (MessageQ_Msg)msg);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
150
src/comm.h
Normal file
150
src/comm.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* comm.h
|
||||
*
|
||||
* Created on: 01-08-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#ifndef COMM_H_
|
||||
#define COMM_H_
|
||||
|
||||
#include <ti/ipc/MessageQ.h>
|
||||
#include <ti/sysbios/hal/Timer.h>
|
||||
#include "tdefs.h"
|
||||
|
||||
#define DSP_CMD_INIT_COMM 0x01
|
||||
#define DSP_CMD_GET_ANALOG_BUF 0x02
|
||||
#define DSP_CMD_GET_IO_BUF 0x03
|
||||
#define DSP_CMD_GET_SHARED_BUF 0x04
|
||||
#define DSP_CMD_UPDATE_CFG 0x05
|
||||
#define DSP_CMD_GET_REG_INF 0x06
|
||||
#define DSP_CMD_ACK_REG 0x07
|
||||
#define DSP_CMD_TIME_SYNC 0x08
|
||||
#define DSP_CMD_LOGMAN_STOP 0x09
|
||||
#define DSP_CMD_LOGMAN_RESET 0x0A
|
||||
#define DSP_CMD_LOGMAN_PUSHFUN 0x0B
|
||||
#define DSP_CMD_LOGMAN_START 0x0C
|
||||
#define DSP_CMD_LOGMAN_STATS 0x0D
|
||||
#define DSP_CMD_GET_REG_MULTIPLIERS 0x0E
|
||||
#define DSP_CMD_GET_REG_MULTIPLIERS_DDR 0x0F
|
||||
#define DSP_CMD_GET_EV_BUF 0x10
|
||||
#define DSP_CMD_GET_MEASURANDS 0x11
|
||||
#define DSP_CMD_GET_LEDS_VIRT_IN 0x12
|
||||
#define DSP_CMD_SET_VIRT_IN 0x13
|
||||
#define DSP_CMD_GET_NET_BUF 0x14
|
||||
#define DSP_CMD_GET_GI 0x15
|
||||
#define DSP_CMD_GET_FWVER 0x16
|
||||
#define DSP_CMD_FORCE_OUT_STATES 0x17
|
||||
#define DSP_CMD_FORCE_BIN_STATES 0x18
|
||||
#define DSP_CMD_GET_DDR_REG_INF 0x19
|
||||
#define DSP_CMD_ACK_DDR_REG 0x1A
|
||||
#define DSP_CMD_FORCE_AN_STATES 0x1B
|
||||
#define DSP_CMD_GET_AN_STATES 0x1C
|
||||
#define DSP_CMD_SET_EVENT_FILTER 0x1D
|
||||
#define DSP_CMD_CFG_STATE 0x1E
|
||||
#define DSP_CMD_CLEAR_RELAYS 0x1F
|
||||
#define DSP_CMD_SET_VIRT_IN2 0x20
|
||||
#define DSP_CMD_ETH_ON 0x21
|
||||
#define DSP_CMD_ETH_OFF 0x22
|
||||
#define DSP_CMD_GET_PROFILE_BUF 0x23
|
||||
#define DSP_CMD_START_PROFILER 0x24
|
||||
#define DSP_CMD_STOP_PROFILER 0x25
|
||||
#define DSP_CMD_ETH_OFF_ACK 0x26
|
||||
#define DSP_CMD_GET_LOGIC_EL_PARAMS 0x27
|
||||
#define DSP_CMD_DEBUGLOG 0xFE
|
||||
|
||||
#define SET_CFG_CHANGE 0x01
|
||||
#define SET_CFG_OK 0x02
|
||||
#define SET_CFG_ERR 0x03
|
||||
|
||||
#define CMD_ACK 0xD5
|
||||
#define CMD_ERR 0xE0
|
||||
|
||||
struct msg_data
|
||||
{
|
||||
MessageQ_MsgHeader hdr;
|
||||
UInt32 cmd;
|
||||
UInt32 p1;
|
||||
UInt32 p2;
|
||||
UInt32 p3;
|
||||
};
|
||||
|
||||
struct notify_data
|
||||
{
|
||||
UInt16 remoteProcId;
|
||||
UInt16 lineId;
|
||||
UInt32 eventId;
|
||||
};
|
||||
|
||||
struct dfr_an_comtrade_params
|
||||
{
|
||||
double multiplier;
|
||||
double primary;
|
||||
double secondary;
|
||||
long unit;
|
||||
}__attribute__((__packed__));
|
||||
|
||||
extern struct notify_data notify;
|
||||
extern struct broadcast_info bcast_nfo;
|
||||
extern volatile struct ping_info ping_nfo;
|
||||
extern volatile u8 saved_bank;
|
||||
|
||||
#define ZPRAE_MLB12_TYPE 43
|
||||
|
||||
struct broadcast_info {
|
||||
u8 id[3];
|
||||
u8 mlb_type;
|
||||
u8 dev_name[21];
|
||||
u8 dev_type;
|
||||
u16 dev_num;
|
||||
u8 mac[6];
|
||||
}__attribute__((__packed__));
|
||||
|
||||
struct ping_info {
|
||||
u8 adr;
|
||||
u8 seq;
|
||||
u16 tstamp;
|
||||
u32 pwmval;
|
||||
}__attribute__((__packed__));
|
||||
|
||||
struct eth_data
|
||||
{
|
||||
u32 ip;
|
||||
u32 netmask;
|
||||
u32 gateway;
|
||||
u8 hwaddr[6];
|
||||
u32 flags;
|
||||
u8 name[21];
|
||||
u16 dev_no;
|
||||
u32 unicast_ip;
|
||||
}__attribute__((__packed__));
|
||||
|
||||
// eth flags
|
||||
#define ETH_NOT_INITIALIZED 0x00
|
||||
#define ETH_INITIALIZED 0x01
|
||||
#define ETH_ACTIVE 0x02
|
||||
#define ETH_GOT_SETTINGS 0x04
|
||||
#define ETH_UDP_INITIALIZED 0x08
|
||||
#define ETH_OFF_ACK 0x10
|
||||
|
||||
extern struct eth_data eth;
|
||||
|
||||
#define NOTIFY_INIT 0x00000001
|
||||
#define NOTIFY_NEW_EVENTS 0x00000002
|
||||
#define NOTIFY_NEW_DFR_REG 0x00000003
|
||||
#define NOTIFY_SEL_BANK0 0x00000004
|
||||
#define NOTIFY_SEL_BANK1 0x00000005
|
||||
#define NOTIFY_SEL_BANK2 0x00000006
|
||||
#define NOTIFY_SEL_BANK3 0x00000007
|
||||
#define NOTIFY_SEL_BANK4 0x00000008
|
||||
#define NOTIFY_NEW_DDR_REG 0x00000009
|
||||
#define NOTIFY_ETH_ON 0x0000000a
|
||||
#define NOTIFY_ETH_OFF 0x0000000b
|
||||
#define NOTIFY_SEL_BANK5 0x0000000c
|
||||
|
||||
extern Timer_Handle tick_timer_handle;
|
||||
extern u32 tick_timer_period;
|
||||
|
||||
extern Void commFxn(UArg a0, UArg a1);
|
||||
|
||||
#endif /* COMM_H_ */
|
||||
41
src/config.h
Normal file
41
src/config.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* config.h
|
||||
*
|
||||
* Created on: 12-01-2021
|
||||
* Author: kjakubczyk
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_H_
|
||||
#define CONFIG_H_
|
||||
|
||||
#define MAX_LOG_ELEMENTS 1050+10+20 // max logman elements // 20 dodano 26.08.2024 przy TZL
|
||||
|
||||
#define LOOP_CYCLE_MS 2 // how many ms between main logman loops
|
||||
#define SAMPLES_PER_MS 4 // samples per ms -> 3 = 3kHz
|
||||
#define MAIN_FREQ_PERIOD_MS 20
|
||||
#define SAMPLES_INTERPOLATION 1 // middle samples config in DFR => 0=sample_duplication, 1=linear interpolation, 2=NAN between
|
||||
// WARNING! linear interpolation needs disable extmem caching for DFR in app.cfg
|
||||
|
||||
#define IEC61850_ACTIVE 1 // activate IEC61850 recv GOOSE/SV
|
||||
#define SV_I_CARD_ADDR 14
|
||||
#define SV_U_CARD_ADDR 15
|
||||
#define SV_WAIT_LOOP_CYCLES 1 // delay by x main loop cycles to wait for SV samples
|
||||
#if IEC61850_ACTIVE==1
|
||||
#define IEC61850_MIN_FR_SIZE 64
|
||||
#define GOOSE_MAX_FR_SIZE 1100//bylo 1024 przed KAE
|
||||
#define GOOSE_MAX_FR_OUT_SIZE 256
|
||||
#define GOOSE_QUEUE_DEPTH 16
|
||||
#define SV_MIN_FR_SIZE 64
|
||||
#define SV_MAX_FR_SIZE 256
|
||||
#define SV_QUEUE_DEPTH 16
|
||||
#else
|
||||
#define IEC61850_MIN_FR_SIZE 1
|
||||
#define GOOSE_MAX_FR_SIZE 1
|
||||
#define GOOSE_QUEUE_DEPTH 1
|
||||
#define SV_MIN_FR_SIZE 1
|
||||
#define SV_MAX_FR_SIZE 1
|
||||
#define SV_QUEUE_DEPTH 1
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* CONFIG_H_ */
|
||||
285
src/hw_psc_OMAPL138.h
Normal file
285
src/hw_psc_OMAPL138.h
Normal file
@@ -0,0 +1,285 @@
|
||||
/**
|
||||
* \file hw_psc_OMAPL138.h
|
||||
*
|
||||
* \brief Hardware definitions for OMAPL138
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
/*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HW_PSC_H_
|
||||
#define _HW_PSC_H_
|
||||
|
||||
/* NOTE1
|
||||
* The actual number of MDCTL and MDSTAT register depend on number of
|
||||
* LPSC modules in a PSC. The number of MDCTL/MDSTAT registers defined
|
||||
* here would be a superset
|
||||
* e.g. PSC0 has 16 MDCTL/MDSTAT register, PSC1 has 32 MDCTL/MDSTAT
|
||||
* registers */
|
||||
|
||||
|
||||
/* NOTE2
|
||||
* Please refer to the device specific PSC user guide to see what
|
||||
* register bit fields apply to individual registers
|
||||
* e.g. For PSC0 MERRPR0 bits 14,15 exist but for PSC1 MERRPR0
|
||||
* these bits are RESERVED */
|
||||
|
||||
typedef enum {
|
||||
HW_PSC_CC0 = 0,
|
||||
HW_PSC_TC0 = 1,
|
||||
HW_PSC_TC1 = 2,
|
||||
HW_PSC_EMIFA = 3,
|
||||
HW_PSC_SPI0 = 4,
|
||||
HW_PSC_MMCSD0 = 5,
|
||||
HW_PSC_AINTC = 6,
|
||||
HW_PSC_ARM_RAMROM = 7,
|
||||
HW_PSC_UART0 = 9,
|
||||
HW_PSC_SCR0_SS = 10,
|
||||
HW_PSC_SCR1_SS = 11,
|
||||
HW_PSC_SCR2_SS = 12,
|
||||
HW_PSC_PRU = 13,
|
||||
HW_PSC_ARM = 14,
|
||||
HW_PSC_DSP = 15
|
||||
|
||||
} Psc0Peripheral;
|
||||
|
||||
typedef enum {
|
||||
HW_PSC_CC1 = 0,
|
||||
HW_PSC_USB0 = 1,
|
||||
HW_PSC_USB1 = 2,
|
||||
HW_PSC_GPIO = 3,
|
||||
HW_PSC_UHPI = 4,
|
||||
HW_PSC_EMAC = 5,
|
||||
HW_PSC_DDR2_MDDR = 6,
|
||||
HW_PSC_MCASP0 = 7,
|
||||
HW_PSC_SATA = 8,
|
||||
HW_PSC_VPIF = 9,
|
||||
HW_PSC_SPI1 = 10,
|
||||
HW_PSC_I2C1 = 11,
|
||||
HW_PSC_UART1 = 12,
|
||||
HW_PSC_UART2 = 13,
|
||||
HW_PSC_MCBSP0 = 14,
|
||||
HW_PSC_MCBSP1 = 15,
|
||||
HW_PSC_LCDC = 16,
|
||||
HW_PSC_EHRPWM = 17,
|
||||
HW_PSC_MMCSD1 = 18,
|
||||
HW_PSC_UPP = 19,
|
||||
HW_PSC_ECAP0_1_2 = 20,
|
||||
HW_PSC_TC2 = 21,
|
||||
HW_PSC_SCRF0_SS = 24,
|
||||
HW_PSC_SCRF1_SS = 25,
|
||||
HW_PSC_SCRF2_SS = 26,
|
||||
HW_PSC_SCRF6_SS = 27,
|
||||
HW_PSC_SCRF7_SS = 28,
|
||||
HW_PSC_SCRF8_SS = 29,
|
||||
HW_PSC_BR_F7 = 30,
|
||||
HW_PSC_SHRAM = 31
|
||||
} Psc1Peripheral;
|
||||
|
||||
#define PSC_POWERDOMAIN_ALWAYS_ON 0
|
||||
#define PSC_POWERDOMAIN_PD_DSP 1
|
||||
|
||||
#define PSC_REVID (0x0)
|
||||
#define PSC_INTEVAL (0x18)
|
||||
#define PSC_MERRPR0 (0x40)
|
||||
#define PSC_MERRCR0 (0x50)
|
||||
#define PSC_PERRPR (0x60)
|
||||
#define PSC_PERRCR (0x68)
|
||||
#define PSC_PTCMD (0x120)
|
||||
#define PSC_PTSTAT (0x128)
|
||||
#define PSC_PDSTAT0 (0x200)
|
||||
#define PSC_PDSTAT1 (0x204)
|
||||
#define PSC_PDCTL0 (0x300)
|
||||
#define PSC_PDCTL1 (0x304)
|
||||
#define PSC_PDCFG0 (0x400)
|
||||
#define PSC_PDCFG1 (0x404)
|
||||
#define PSC_MDSTAT(n) (0x800 + (n * 4))
|
||||
#define PSC_MDCTL(n) (0xA00 + (n * 4))
|
||||
|
||||
/**************************************************************************\
|
||||
* Field Definition Macros
|
||||
\**************************************************************************/
|
||||
|
||||
/* REVID */
|
||||
|
||||
#define PSC_REVID_REV (0xFFFFFFFFu)
|
||||
#define PSC_REVID_REV_SHIFT (0x00000000u)
|
||||
|
||||
/* INTEVAL */
|
||||
|
||||
#define PSC_INTEVAL_ALLEV (0x00000001u)
|
||||
#define PSC_INTEVAL_ALLEV_SHIFT (0x00000000u)
|
||||
|
||||
/* MERRPR0 */
|
||||
#define PSC_MERRPR0_M15 (0x0000C000u)
|
||||
#define PSC_MERRPR0_M15_SHIFT (0x0000000Eu)
|
||||
#define PSC_MERRPR0_M14 (0x00006000u)
|
||||
#define PSC_MERRPR0_M14_SHIFT (0x0000000Du)
|
||||
|
||||
/* MERRCR0 */
|
||||
#define PSC_MERRCR0_M15 (0x0000C000u)
|
||||
#define PSC_MERRCR0_M15_SHIFT (0x0000000Eu)
|
||||
#define PSC_MERRCR0_M14 (0x00006000u)
|
||||
#define PSC_MERRCR0_M14_SHIFT (0x0000000Du)
|
||||
|
||||
/* PERRPR */
|
||||
#define PSC_PERRPR_P1 (0x00000002u)
|
||||
#define PSC_PERRPR_P1_SHIFT (0x00000001u)
|
||||
#define PSC_PERRPR_P0 (0x00000001u)
|
||||
#define PSC_PERRPR_P0_SHIFT (0x00000000u)
|
||||
|
||||
/* PERRCR */
|
||||
#define PSC_PERRCR_P1 (0x00000002u)
|
||||
#define PSC_PERRCR_P1_SHIFT (0x00000001u)
|
||||
#define PSC_PERRCR_P0 (0x00000001u)
|
||||
#define PSC_PERRCR_P0_SHIFT (0x00000000u)
|
||||
|
||||
/* PTCMD */
|
||||
#define PSC_PTCMD_GO1 (0x00000002u)
|
||||
#define PSC_PTCMD_GO1_SHIFT (0x00000001u)
|
||||
#define PSC_PTCMD_GO0 (0x00000001u)
|
||||
#define PSC_PTCMD_GO0_SHIFT (0x00000000u)
|
||||
|
||||
/* PTSTAT */
|
||||
#define PSC_PTSTAT_GOSTAT1 (0x00000002u)
|
||||
#define PSC_PTSTAT_GOSTAT1_SHIFT (0x00000001u)
|
||||
#define PSC_PTSTAT_GOSTAT0 (0x00000001u)
|
||||
#define PSC_PTSTAT_GOSTAT0_SHIFT (0x00000000u)
|
||||
|
||||
/* PDSTAT0 */
|
||||
#define PSC_PDSTAT0_EMUIHB (0x00000800u)
|
||||
#define PSC_PDSTAT0_EMUIHB_SHIFT (0x0000000Bu)
|
||||
#define PSC_PDSTAT0_STATE (0x0000001Fu)
|
||||
#define PSC_PDSTAT0_STATE_SHIFT (0x00000000u)
|
||||
|
||||
/* PDSTAT1 */
|
||||
#define PSC_PDSTAT1_EMUIHB (0x00000800u)
|
||||
#define PSC_PDSTAT1_EMUIHB_SHIFT (0x0000000Bu)
|
||||
#define PSC_PDSTAT1_STATE (0x0000001Fu)
|
||||
#define PSC_PDSTAT1_STATE_SHIFT (0x00000000u)
|
||||
|
||||
/* PDCTL0 */
|
||||
#define PSC_PDCTL0_WAKECNT (0x00FF0000u)
|
||||
#define PSC_PDCTL0_WAKECNT_SHIFT (0x00000010u)
|
||||
#define PSC_PDCTL0_PDMODE (0x0000F000u)
|
||||
#define PSC_PDCTL0_PDMODE_SHIFT (0x0000000Cu)
|
||||
#define PSC_PDCTL0_EMUIHBIE (0x00000200u)
|
||||
#define PSC_PDCTL0_EMUIHBIE_SHIFT (0x00000009u)
|
||||
#define PSC_PDCTL0_NEXT (0x00000001u)
|
||||
#define PSC_PDCTL0_NEXT_SHIFT (0x00000000u)
|
||||
|
||||
/* PDCTL1 */
|
||||
#define PSC_PDCTL1_WAKECNT (0x00FF0000u)
|
||||
#define PSC_PDCTL1_WAKECNT_SHIFT (0x00000010u)
|
||||
#define PSC_PDCTL1_PDMODE (0x0000F000u)
|
||||
#define PSC_PDCTL1_PDMODE_SHIFT (0x0000000Cu)
|
||||
/*----PDMODE Tokens----*/
|
||||
#define PSC_PDCTL1_PDMODE_OFF (0x00000000u)
|
||||
#define PSC_PDCTL1_PDMODE_RAM_OFF (0x00000008u)
|
||||
#define PSC_PDCTL1_PDMODE_DEEP_SLEEP (0x00000009u)
|
||||
#define PSC_PDCTL1_PDMODE_LIGHT_SLEEP (0x0000000Au)
|
||||
#define PSC_PDCTL1_PDMODE_RETENTION (0x0000000Bu)
|
||||
#define PSC_PDCTL1_PDMODE_ON (0x0000000Fu)
|
||||
|
||||
#define PSC_PDCTL1_EMUIHBIE (0x00000200u)
|
||||
#define PSC_PDCTL1_EMUIHBIE_SHIFT (0x00000009u)
|
||||
#define PSC_PDCTL1_NEXT (0x00000001u)
|
||||
#define PSC_PDCTL1_NEXT_SHIFT (0x00000000u)
|
||||
|
||||
/* PDCFG0 */
|
||||
#define PSC_PDCFG0_PDLOCK (0x00000008u)
|
||||
#define PSC_PDCFG0_PDLOCK_SHIFT (0x00000003u)
|
||||
#define PSC_PDCFG0_ICEPICK (0x00000004u)
|
||||
#define PSC_PDCFG0_ICEPICK_SHIFT (0x00000002u)
|
||||
#define PSC_PDCFG0_RAM_PSM (0x00000002u)
|
||||
#define PSC_PDCFG0_RAM_PSM_SHIFT (0x00000001u)
|
||||
#define PSC_PDCFG0_ALWAYSON (0x00000001u)
|
||||
#define PSC_PDCFG0_ALWAYSON_SHIFT (0x00000000u)
|
||||
|
||||
/* PDCFG1 */
|
||||
#define PSC_PDCFG1_PDLOCK (0x00000008u)
|
||||
#define PSC_PDCFG1_PDLOCK_SHIFT (0x00000003u)
|
||||
#define PSC_PDCFG1_ICEPICK (0x00000004u)
|
||||
#define PSC_PDCFG1_ICEPICK_SHIFT (0x00000002u)
|
||||
#define PSC_PDCFG1_RAM_PSM (0x00000002u)
|
||||
#define PSC_PDCFG1_RAM_PSM_SHIFT (0x00000001u)
|
||||
#define PSC_PDCFG1_ALWAYSON (0x00000001u)
|
||||
#define PSC_PDCFG1_ALWAYSON_SHIFT (0x00000000u)
|
||||
|
||||
/* MDSTAT */
|
||||
#define PSC_MDSTAT_EMUIHB (0x00020000u)
|
||||
#define PSC_MDSTAT_EMUIHB_SHIFT (0x00000011u)
|
||||
#define PSC_MDSTAT_EMURST (0x00010000u)
|
||||
#define PSC_MDSTAT_EMURST_SHIFT (0x00000010u)
|
||||
#define PSC_MDSTAT_MCKOUT (0x00001000u)
|
||||
#define PSC_MDSTAT_MCKOUT_SHIFT (0x0000000Cu)
|
||||
#define PSC_MDSTAT_MRSTDONE (0x00000800u)
|
||||
#define PSC_MDSTAT_MRSTDONE_SHIFT (0x0000000Bu)
|
||||
#define PSC_MDSTAT_MRST (0x00000400u)
|
||||
#define PSC_MDSTAT_MRST_SHIFT (0x0000000Au)
|
||||
#define PSC_MDSTAT_LRSTDONE (0x00000200u)
|
||||
#define PSC_MDSTAT_LRSTDONE_SHIFT (0x00000009u)
|
||||
#define PSC_MDSTAT_LRST (0x00000100u)
|
||||
#define PSC_MDSTAT_LRST_SHIFT (0x00000008u)
|
||||
#define PSC_MDSTAT_STATE (0x0000003Fu)
|
||||
#define PSC_MDSTAT_STATE_SHIFT (0x00000000u)
|
||||
/*----STATE Tokens----*/
|
||||
#define PSC_MDSTAT_STATE_SWRSTDISABLE (0x00000000u)
|
||||
#define PSC_MDSTAT_STATE_SYNCRST (0x00000001u)
|
||||
#define PSC_MDSTAT_STATE_AUTOSLEEP (0x00000004u)
|
||||
#define PSC_MDSTAT_STATE_AUTOWAKE (0x00000005u)
|
||||
|
||||
/* MDCTL */
|
||||
#define PSC_MDCTL_FORCE (0x80000000u)
|
||||
#define PSC_MDCTL_FORCE_SHIFT (0x0000001Fu)
|
||||
|
||||
#define PSC_MDCTL_EMUIHBIE (0x00000400u)
|
||||
#define PSC_MDCTL_EMUIHBIE_SHIFT (0x0000000Au)
|
||||
|
||||
#define PSC_MDCTL_EMURSTIE (0x00000200u)
|
||||
#define PSC_MDCTL_EMURSTIE_SHIFT (0x00000009u)
|
||||
|
||||
#define PSC_MDCTL_LRST (0x00000100u)
|
||||
#define PSC_MDCTL_LRST_SHIFT (0x00000008u)
|
||||
#define PSC_MDCTL_NEXT (0x0000001Fu)
|
||||
#define PSC_MDCTL_NEXT_SHIFT (0x00000000u)
|
||||
/*----NEXT Tokens----*/
|
||||
#define PSC_MDCTL_NEXT_SWRSTDISABLE (0x00000000u)
|
||||
#define PSC_MDCTL_NEXT_SYNCRST (0x00000001u)
|
||||
#define PSC_MDCTL_NEXT_DISABLE (0x00000002u)
|
||||
#define PSC_MDCTL_NEXT_ENABLE (0x00000003u)
|
||||
#define PSC_MDCTL_NEXT_AUTOWAKE (0x00000005u)
|
||||
|
||||
#endif
|
||||
2167
src/hw_syscfg0_OMAPL138.h
Normal file
2167
src/hw_syscfg0_OMAPL138.h
Normal file
File diff suppressed because it is too large
Load Diff
430
src/logman.c
Normal file
430
src/logman.c
Normal file
@@ -0,0 +1,430 @@
|
||||
/*
|
||||
* logman.c
|
||||
*
|
||||
* Created on: 08-04-2014
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <ti/sysbios/knl/Task.h>
|
||||
#include <ti/sysbios/knl/Clock.h>
|
||||
#include <ti/sysbios/hal/Timer.h>
|
||||
|
||||
#include "tdefs.h"
|
||||
#include "logman.h"
|
||||
#include "misc.h"
|
||||
#include "comm.h"
|
||||
|
||||
#include "logic_elements/elements.h"
|
||||
#include "logic_elements/eth.h"
|
||||
#include "ports/am1808/include/netif/sitaraif.h"
|
||||
|
||||
struct logic_manager log_manager;
|
||||
struct logman_profiler log_profile[MAX_LOG_ELEMENTS];
|
||||
//u32 debug_size[8];
|
||||
|
||||
#pragma LOCATION(log_profile,0xc5400000) // @ non-cached memory above 128MB
|
||||
|
||||
void logman_reset()
|
||||
{
|
||||
u32 i;
|
||||
memset((void *)&measurands,0,sizeof(measurands));
|
||||
memset(&log_manager,0,sizeof(log_manager));
|
||||
memset(&log_profile,0,sizeof(log_profile));
|
||||
|
||||
dbg.logman_cycle_time_max=0;
|
||||
dbg.logman_cycle_time=0;
|
||||
ev_reg_log=NULL;
|
||||
// led_blink_states=0;
|
||||
// led_states=0;
|
||||
// virt_in_states=0;
|
||||
virt_in_mask=0;
|
||||
virt_in2_mask=0;
|
||||
dfr_drv_log_ptr=NULL;
|
||||
ddr_drv_log_ptr=NULL;
|
||||
dev_ctrl_state=0;
|
||||
memset((u8*)force_bus_bin_data,0,sizeof(force_bus_bin_data));
|
||||
memset((u8*)force_bus_out_data,0,sizeof(force_bus_out_data));
|
||||
memset((u8*)bus_an_samples_neg,0,sizeof(bus_an_samples_neg));
|
||||
// memset((u8*)ic->out_set,0,sizeof(ic->out_set));
|
||||
for(i=0;i<MAX_REG_BANKS;i++)
|
||||
regs.bank[i].state=BANK_EMPTY;
|
||||
|
||||
log_manager.cur_buf_ptr = log_manager.buf;
|
||||
log_manager.nets_data[0]&=~0x01; // all unused inputs will be pulled down
|
||||
log_manager.nets_data[0]|=0x02;
|
||||
logman_notify=0;
|
||||
|
||||
mwd32_mask=0;
|
||||
ic->mwd32_present=0;
|
||||
|
||||
emac_hash_clear(EMAC_0_BASE);
|
||||
}
|
||||
|
||||
int logman_pushfunc(u16 fun_id,void *args, u32 args_size)
|
||||
{
|
||||
u32 i=0;
|
||||
u32 fun_index=0;
|
||||
// u32 dbgg;
|
||||
|
||||
void *argsptr,*logptr;
|
||||
|
||||
if(log_manager.cur_element_num>=MAX_LOG_ELEMENTS)
|
||||
return -5;
|
||||
|
||||
while(log_elements[i].id!=EOF_ELEMENT)
|
||||
{
|
||||
if(log_elements[i].id == fun_id)
|
||||
break;
|
||||
i++;
|
||||
}
|
||||
|
||||
if(log_elements[i].id==EOF_ELEMENT)
|
||||
return -1;
|
||||
|
||||
fun_index=i;
|
||||
|
||||
if(log_elements[fun_index].args_size != args_size && ((fun_id != GOOSE_FUN_ID && fun_id != SV_FUN_ID && fun_id != GOOSE_OUT_FUN_ID) || args_size<log_elements[fun_index].args_size) )
|
||||
return -2;
|
||||
|
||||
if((log_manager.cur_buf_ptr + args_size) > (log_manager.buf + LOGMAN_BUFSIZE))
|
||||
return -3;
|
||||
|
||||
log_manager.log_element[log_manager.cur_element_num].el_num = fun_index;
|
||||
// log_manager.log_element[log_manager.cur_element_num].fun_main_ptr = log_elements[fun_index].fun_ptr;
|
||||
// log_manager.log_element[log_manager.cur_element_num].fun_100hz_ptr = log_elements[fun_index].fun_100hz_ptr;
|
||||
// log_manager.log_element[log_manager.cur_element_num].fun_20hz_ptr = log_elements[fun_index].fun_20hz_ptr;
|
||||
|
||||
// dbgg=(u32)(log_manager.cur_buf_ptr);
|
||||
|
||||
memcpy(log_manager.cur_buf_ptr,args,args_size);
|
||||
log_manager.log_element[log_manager.cur_element_num].fun_args_ptr = log_manager.cur_buf_ptr;
|
||||
argsptr=log_manager.cur_buf_ptr;
|
||||
log_manager.cur_buf_ptr+=args_size;
|
||||
|
||||
if((log_manager.cur_buf_ptr + log_elements[fun_index].log_size) > (log_manager.buf + LOGMAN_BUFSIZE))
|
||||
return -4;
|
||||
|
||||
log_manager.log_element[log_manager.cur_element_num].fun_log_ptr = log_manager.cur_buf_ptr;
|
||||
logptr=log_manager.cur_buf_ptr;
|
||||
|
||||
log_manager.cur_buf_ptr+=log_elements[fun_index].log_size;
|
||||
|
||||
if(log_elements[fun_index].initlog_ptr)
|
||||
if(log_elements[fun_index].initlog_ptr(argsptr,logptr))
|
||||
return -6;
|
||||
|
||||
if(fun_id == EVENTS_REG_FUN_ID)
|
||||
{
|
||||
struct events_reg_logic *evreg_l = (struct events_reg_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&evreg_l->element_num[evreg_l->events_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[0]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == OUT_DRV_FUN_ID)
|
||||
{
|
||||
struct out_drv_logic *out_drv_l = (struct out_drv_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&out_drv_l->element_num[out_drv_l->out_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[1]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == DFR_DRV_FUN_ID)
|
||||
{
|
||||
struct dfr_drv_logic *dfr_l = (struct dfr_drv_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&dfr_l->element_num[dfr_l->an_count+dfr_l->bin_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[2]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == DDR_DRV_FUN_ID)
|
||||
{
|
||||
struct ddr_drv_logic *ddr_l = (struct ddr_drv_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&ddr_l->element_num[ddr_l->an_count+ddr_l->bin_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[3]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == LEDS_DRV_FUN_ID)
|
||||
{
|
||||
struct leds_drv_logic *leds_l = (struct leds_drv_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&leds_l->element_num[leds_l->leds_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[4]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == VIRT_IN_DRV_FUN_ID)
|
||||
{
|
||||
struct virt_in_drv_logic *virt_l = (struct virt_in_drv_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&virt_l->element_num[virt_l->virt_in_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[5]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == GOOSE_DRV_FUN_ID)
|
||||
{
|
||||
struct goose_drv_logic *g = (struct goose_drv_logic *)logptr;
|
||||
log_manager.cur_buf_ptr=(u8*)&g->element_num[g->gooses_count+1];
|
||||
log_manager.cur_buf_ptr+=(u32)(log_manager.cur_buf_ptr)%4;
|
||||
// debug_size[6]=(u32)(log_manager.cur_buf_ptr)-dbgg;
|
||||
}
|
||||
else if(fun_id == AN_GEN_FUN_ID)
|
||||
{
|
||||
// struct an_gen_logic *an_gen_l = (struct an_gen_logic *)logptr;
|
||||
// log_manager.cur_buf_ptr=(u8*)&an_gen_l->element_num[an_gen_l->an_count+1];
|
||||
}
|
||||
|
||||
log_manager.log_element[log_manager.cur_element_num].flags = FUNCTION_ENABLED;
|
||||
|
||||
if(fun_id == EVENT_FUN_ID)
|
||||
{
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_EVENT;
|
||||
log_manager.status|=LOGMAN_USING_EVENTS;
|
||||
}
|
||||
else if(fun_id == REC_AN_FUN_ID)
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_AN;
|
||||
else if(fun_id == REC_BUF_FUN_ID)
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_BUF;
|
||||
else if(fun_id == REC_FLOAT_FUN_ID)
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_FLOAT;
|
||||
else if(fun_id == REC_BIN_FUN_ID)
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REC_BIN;
|
||||
else if(fun_id == REL_OUT_FUN_ID)
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_REL_OUT;
|
||||
else if(fun_id == SV_FUN_ID)
|
||||
log_manager.status|= LOGMAN_USING_IEC_SV;
|
||||
else if(fun_id == GOOSE_FUN_ID)
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_GOOSE;
|
||||
else if(fun_id == DFR_FUN_ID)
|
||||
{
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_DFR;
|
||||
log_manager.status|=LOGMAN_USING_DFR;
|
||||
}
|
||||
else if(fun_id == DDR_FUN_ID)
|
||||
{
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_DDR;
|
||||
log_manager.status|=LOGMAN_USING_DDR;
|
||||
}
|
||||
else if(fun_id == LED_FUN_ID || fun_id == BUZZER_FUN_ID)
|
||||
{
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_LED;
|
||||
log_manager.status|=LOGMAN_USING_LEDS;
|
||||
}
|
||||
else if(fun_id == VIRT_IN_FUN_ID)
|
||||
{
|
||||
log_manager.log_element[log_manager.cur_element_num].flags |= FUNCTION_IS_VIRT_IN;
|
||||
log_manager.status|=LOGMAN_USING_VIRT_IN;
|
||||
}
|
||||
|
||||
log_manager.cur_element_num++;
|
||||
|
||||
dbg.logman_buf_size_cur = log_manager.cur_buf_ptr - log_manager.buf;
|
||||
|
||||
log_manager.status|=LOGMAN_USING_AN_GEN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void logman_stop()
|
||||
{
|
||||
log_manager.requests|=LOGMAN_REQUEST_STOP;
|
||||
while(log_manager.status & LOGMAN_STATUS_STARTED)
|
||||
Task_sleep(1);
|
||||
}
|
||||
|
||||
int logman_start()
|
||||
{
|
||||
int ret;
|
||||
|
||||
log_manager.soft_start_cnt=0;
|
||||
|
||||
ret=logman_pushfunc(OUT_DRV_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -7;
|
||||
|
||||
if(log_manager.status & LOGMAN_USING_EVENTS)
|
||||
{
|
||||
ret=logman_pushfunc(EVENTS_REG_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -1;
|
||||
log_manager.status&=~LOGMAN_USING_EVENTS;
|
||||
}
|
||||
if(log_manager.status & LOGMAN_USING_LEDS)
|
||||
{
|
||||
ret=logman_pushfunc(LEDS_DRV_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -2;
|
||||
log_manager.status&=~LOGMAN_USING_LEDS;
|
||||
}
|
||||
if(log_manager.status & LOGMAN_USING_VIRT_IN)
|
||||
{
|
||||
ret=logman_pushfunc(VIRT_IN_DRV_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -3;
|
||||
log_manager.status&=~LOGMAN_USING_VIRT_IN;
|
||||
}
|
||||
if(log_manager.status & LOGMAN_USING_DFR)
|
||||
{
|
||||
ret=logman_pushfunc(DFR_DRV_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -4;
|
||||
log_manager.status&=~LOGMAN_USING_DFR;
|
||||
}
|
||||
if(log_manager.status & LOGMAN_USING_DDR)
|
||||
{
|
||||
ret=logman_pushfunc(DDR_DRV_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -5;
|
||||
log_manager.status&=~LOGMAN_USING_DDR;
|
||||
}
|
||||
|
||||
if(log_manager.status & LOGMAN_USING_AN_GEN)
|
||||
{
|
||||
ret=logman_pushfunc(AN_GEN_FUN_ID,NULL,0);
|
||||
if(ret)
|
||||
return -6;
|
||||
log_manager.status&=~LOGMAN_USING_AN_GEN;
|
||||
}
|
||||
|
||||
log_manager.requests|=LOGMAN_REQUEST_START;
|
||||
while(!(log_manager.status & LOGMAN_STATUS_STARTED))
|
||||
Task_sleep(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void logman_init()
|
||||
{
|
||||
logman_reset();
|
||||
}
|
||||
|
||||
void logman_xkhz()
|
||||
{
|
||||
u32 i;
|
||||
u32 t_pre,t_post,t;
|
||||
|
||||
if(log_manager.status & LOGMAN_STATUS_SOFT_STARTED && !(dev_ctrl_state & DEV_CTRL_STATE_TEST_OUT))
|
||||
memcpy((void*)bus_out_data,(void*)ic->out_set,MAX_OUT_CARDS);
|
||||
|
||||
memcpy((void*)bus_bin_data,(void*)ic->bin_in,MAX_BIN_CARDS);
|
||||
memcpy((void*)bus_bin_data_ench,(void*)ic->bin_in_ench,MAX_BIN_CARDS);
|
||||
if(dev_ctrl_state & DEV_CTRL_STATE_TEST_IN)
|
||||
{
|
||||
for(i=0;i<MAX_BIN_CARDS;i++)
|
||||
{
|
||||
bus_bin_data[i]^=force_bus_bin_data[i];
|
||||
bus_bin_data_ench[i]^=force_bus_bin_data_ench[i];
|
||||
}
|
||||
}
|
||||
|
||||
if(log_manager.requests & LOGMAN_REQUEST_STOP)
|
||||
{
|
||||
log_manager.status&=~LOGMAN_STATUS_STARTED;
|
||||
log_manager.requests&=~LOGMAN_REQUEST_STOP;
|
||||
}
|
||||
|
||||
if(log_manager.requests & LOGMAN_REQUEST_START)
|
||||
{
|
||||
log_manager.status|=LOGMAN_STATUS_STARTED;
|
||||
log_manager.requests&=~LOGMAN_REQUEST_START;
|
||||
}
|
||||
|
||||
if(log_manager.status & LOGMAN_STATUS_STARTED)
|
||||
{
|
||||
//logman_notify=0;
|
||||
|
||||
if(log_manager.soft_start_cnt<LOGMAN_SOFT_START_TIME)
|
||||
log_manager.soft_start_cnt++;
|
||||
else
|
||||
{
|
||||
if(!(log_manager.status & LOGMAN_STATUS_SOFT_STARTED))
|
||||
log_manager.status|=LOGMAN_STATUS_SOFT_STARTED;
|
||||
}
|
||||
if(!(log_manager.status & LOGMAN_STATUS_PROFILING))
|
||||
{
|
||||
for(i=0;i<MAX_LOG_ELEMENTS;i++)
|
||||
{
|
||||
if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_main_ptr)
|
||||
log_elements[log_manager.log_element[i].el_num].fun_main_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
|
||||
else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
|
||||
{
|
||||
dbg.used_elements=i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
else // profiling
|
||||
{
|
||||
for(i=0;i<MAX_LOG_ELEMENTS;i++)
|
||||
{
|
||||
if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_main_ptr)
|
||||
{
|
||||
t_pre=PWM1_GET(PWM1_TBCNT);
|
||||
log_elements[log_manager.log_element[i].el_num].fun_main_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
|
||||
t_post=PWM1_GET(PWM1_TBCNT);
|
||||
if(t_post>=t_pre)
|
||||
t = t_post-t_pre;
|
||||
else
|
||||
t = t_post+65536-t_pre;
|
||||
|
||||
log_profile[i].t_cur=t;
|
||||
|
||||
if(t>log_profile[i].t_max)
|
||||
log_profile[i].t_max=t;
|
||||
}
|
||||
else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(logman_notify)
|
||||
Swi_post(swi_notify);
|
||||
}
|
||||
|
||||
if(log_manager.status & LOGMAN_STATUS_SOFT_STARTED)
|
||||
{
|
||||
if(dev_ctrl_state & DEV_CTRL_STATE_TEST_OUT)
|
||||
{
|
||||
for(i=0;i<MAX_OUT_CARDS;i++)
|
||||
bus_out_data_test[i]=force_bus_out_data[i]^bus_out_data[i];
|
||||
|
||||
if(!(dev_ctrl_state & DEV_CTRL_STATE_BLOCK_OUT))
|
||||
memcpy((void*)ic->out_set,(void*)bus_out_data_test,MAX_OUT_CARDS*2);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(!(dev_ctrl_state & DEV_CTRL_STATE_BLOCK_OUT))
|
||||
memcpy((void*)ic->out_set,(void*)bus_out_data,MAX_OUT_CARDS*2);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void logman_100hz()
|
||||
{
|
||||
u32 i;
|
||||
|
||||
if(log_manager.status & LOGMAN_STATUS_STARTED)
|
||||
{
|
||||
for(i=0;i<MAX_LOG_ELEMENTS;i++)
|
||||
{
|
||||
if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_100hz_ptr)
|
||||
log_elements[log_manager.log_element[i].el_num].fun_100hz_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
|
||||
else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void logman_20hz()
|
||||
{
|
||||
u32 i;
|
||||
|
||||
if(log_manager.status & LOGMAN_STATUS_STARTED)
|
||||
{
|
||||
for(i=0;i<MAX_LOG_ELEMENTS;i++)
|
||||
{
|
||||
if((log_manager.log_element[i].flags & FUNCTION_ENABLED) && log_elements[log_manager.log_element[i].el_num].fun_20hz_ptr)
|
||||
log_elements[log_manager.log_element[i].el_num].fun_20hz_ptr(log_manager.log_element[i].fun_args_ptr,log_manager.log_element[i].fun_log_ptr);
|
||||
else if(log_manager.log_element[i].flags == FUNCTION_NOT_INITIALIZED)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
94
src/logman.h
Normal file
94
src/logman.h
Normal file
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* logman.h
|
||||
*
|
||||
* Created on: 08-04-2014
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#ifndef LOGMAN_H_
|
||||
#define LOGMAN_H_
|
||||
|
||||
#include "config.h"
|
||||
|
||||
// logic manager function flags
|
||||
#define FUNCTION_NOT_INITIALIZED 0x0000
|
||||
#define FUNCTION_ENABLED 0x0001
|
||||
#define FUNCTION_IS_DDR 0x8000
|
||||
#define FUNCTION_IS_REC_FLOAT 0x4000
|
||||
#define FUNCTION_IS_DFR 0x2000
|
||||
#define FUNCTION_IS_VIRT_IN 0x1000
|
||||
#define FUNCTION_IS_LED 0x0800
|
||||
#define FUNCTION_IS_MEASURAND 0x0400
|
||||
#define FUNCTION_IS_REC_AN 0x0200
|
||||
#define FUNCTION_IS_REC_BIN 0x0100
|
||||
#define FUNCTION_IS_EVENT 0x0080
|
||||
#define FUNCTION_IS_REL_OUT 0x0040
|
||||
#define FUNCTION_IS_REC_BUF 0x0020
|
||||
#define FUNCTION_IS_GOOSE 0x0010
|
||||
|
||||
// logman status
|
||||
#define LOGMAN_STATUS_STARTED 0x00000001
|
||||
#define LOGMAN_STATUS_SOFT_STARTED 0x00000002
|
||||
#define LOGMAN_STATUS_PROFILING 0x00000004
|
||||
#define LOGMAN_USING_IEC_SV 0x02000000
|
||||
#define LOGMAN_USING_AN_GEN 0x04000000
|
||||
#define LOGMAN_USING_DDR 0x08000000
|
||||
#define LOGMAN_USING_DFR 0x10000000
|
||||
#define LOGMAN_USING_VIRT_IN 0x20000000
|
||||
#define LOGMAN_USING_EVENTS 0x40000000
|
||||
#define LOGMAN_USING_LEDS 0x80000000
|
||||
|
||||
// logman requests
|
||||
#define LOGMAN_REQUEST_START 0x00000001
|
||||
#define LOGMAN_REQUEST_STOP 0x00000002
|
||||
|
||||
#define LOGMAN_BUFSIZE 65536-8192+1792+2560 //98304 +2048 dodano 26.08.2024 dla TZL-8
|
||||
#define LOGMAN_NETSDATA_SIZE 1536//32768
|
||||
|
||||
#define LOGMAN_SOFT_START_TIME 200
|
||||
|
||||
extern u32 debug_size[8];
|
||||
|
||||
struct logman_profiler
|
||||
{
|
||||
u16 t_cur;
|
||||
u16 t_max;
|
||||
};
|
||||
|
||||
extern struct logman_profiler log_profile[MAX_LOG_ELEMENTS];
|
||||
|
||||
struct logic_element
|
||||
{
|
||||
u16 flags;
|
||||
u8 el_num;
|
||||
// void (*fun_main_ptr)(void*,void*);
|
||||
// void (*fun_100hz_ptr)(void*,void*);
|
||||
// void (*fun_20hz_ptr)(void*,void*);
|
||||
void (*fun_args_ptr);
|
||||
void (*fun_log_ptr);
|
||||
};
|
||||
|
||||
struct logic_manager
|
||||
{
|
||||
u32 status;
|
||||
u32 requests;
|
||||
u16 cur_element_num;
|
||||
u8 *cur_buf_ptr;
|
||||
struct logic_element log_element[MAX_LOG_ELEMENTS];
|
||||
u8 buf[LOGMAN_BUFSIZE];
|
||||
u8 nets_data[LOGMAN_NETSDATA_SIZE];
|
||||
u8 soft_start_cnt;
|
||||
};
|
||||
|
||||
extern struct logic_manager log_manager;
|
||||
|
||||
extern void logman_xkhz();
|
||||
extern void logman_100hz();
|
||||
extern void logman_20hz();
|
||||
extern void logman_init();
|
||||
extern void logman_reset();
|
||||
extern void logman_stop();
|
||||
extern int logman_start();
|
||||
extern int logman_pushfunc(u16 fun_id,void *args, u32 args_size);
|
||||
|
||||
#endif /* LOGMAN_H_ */
|
||||
533
src/main.c
Normal file
533
src/main.c
Normal file
@@ -0,0 +1,533 @@
|
||||
/*
|
||||
* main.c
|
||||
*
|
||||
* Created on: 01-06-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#include <xdc/std.h>
|
||||
|
||||
#include <xdc/runtime/Error.h>
|
||||
#include <xdc/runtime/System.h>
|
||||
|
||||
#include <ti/sysbios/BIOS.h>
|
||||
#include <ti/sysbios/hal/Hwi.h>
|
||||
#include <ti/sysbios/knl/Swi.h>
|
||||
#include <ti/sysbios/knl/Semaphore.h>
|
||||
#include <ti/sysbios/knl/Task.h>
|
||||
#include <ti/sysbios/hal/Timer.h>
|
||||
#include <ti/sysbios/knl/Clock.h>
|
||||
#include <ti/ipc/Notify.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "misc.h"
|
||||
#include "comm.h"
|
||||
#include "tdefs.h"
|
||||
#include "logman.h"
|
||||
#include "spi.h"
|
||||
#include "logic_elements/dev_ctrl.h"
|
||||
#include "logic_elements/an_gen.h"
|
||||
#include "logic_elements/events_reg.h"
|
||||
//pwm
|
||||
#include "psc.h"
|
||||
#include "soc_OMAPL138.h"
|
||||
#include "hw_syscfg0_OMAPL138.h"
|
||||
#include "hw_types.h"
|
||||
//
|
||||
/// ethernet
|
||||
#include "ethernet/ports/am1808/include/lwiplib.h"
|
||||
///
|
||||
#include "config.h"
|
||||
|
||||
volatile unsigned short last_sample_no;
|
||||
volatile unsigned short samples_dropped = 0;
|
||||
volatile unsigned short last_sample_sync_no;
|
||||
volatile unsigned short samples_sync_dropped = 0;
|
||||
volatile int is_first_sample = 1;
|
||||
volatile int irqs = 0;
|
||||
u16 bus_an_cur_timestamp = 0;
|
||||
|
||||
#pragma LOCATION(shared_buf,0xc5500000) // @ non-cached memory above 128MB
|
||||
volatile int shared_buf[1024];
|
||||
|
||||
#pragma DATA_ALIGN(analog_buf, 128) // place @ cache line boundary
|
||||
volatile short analog_buf[127];
|
||||
|
||||
//volatile int analog_buf_ready = 0;
|
||||
//volatile int analog_buf_cnt = 0;
|
||||
unsigned int analog_buf_card = 0;
|
||||
unsigned int analog_buf_channel = 0;
|
||||
|
||||
struct device_config dev_cfg;
|
||||
|
||||
u8 mwd_states_cur[MAX_BIN_CARDS];
|
||||
u8 mwd_states_prev[MAX_BIN_CARDS];
|
||||
|
||||
Swi_Handle swi_notify;
|
||||
Swi_Params swi_notify_params;
|
||||
|
||||
Swi_Handle swi_ms;
|
||||
Swi_Params swi_ms_params;
|
||||
|
||||
Swi_Handle swi_10ms;
|
||||
Swi_Params swi_10ms_params;
|
||||
|
||||
Swi_Handle swi_50ms;
|
||||
Swi_Params swi_50ms_params;
|
||||
|
||||
extern Timer_Handle timer0;
|
||||
|
||||
u8 loops_synced=0;
|
||||
|
||||
u8 khz_trigger=LOOP_CYCLE_MS * SAMPLES_PER_MS;
|
||||
|
||||
volatile u32 cycle_pwm=0;
|
||||
volatile struct timeval cur_time = { 1388563200, 0 }; // default 2014-01-01
|
||||
volatile struct timeval cur_time_sw = { 1577836800, 0 }; // default 2020-01-01
|
||||
u8 bus_an_cur_sample_num_prev=0;
|
||||
u8 sample_watch_init=0;
|
||||
u8 cur_sample_diff=0;
|
||||
|
||||
void pwm_init()
|
||||
{
|
||||
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_EHRPWM, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
|
||||
PWM1_SET(PWM1_TBCTL, 0x8D03); //FREE RUN, CLKDIV /8, HSPCLKDIV /4, STOP
|
||||
PWM1_SET(PWM1_TBPRD, 0xFFFF);
|
||||
PWM1_SET(PWM1_TBCNT, 0x0000);
|
||||
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP1) |= SYSCFG_CFGCHIP1_TBCLKSYNC;
|
||||
}
|
||||
|
||||
void pwm_start_cnt()
|
||||
{
|
||||
PWM1_SET(PWM1_TBCNT, 0x0000); //COUNTER = 0
|
||||
PWM1_SET(PWM1_TBCTL, 0x8D00); //START
|
||||
}
|
||||
|
||||
u32 pwm_stop_cnt()
|
||||
{
|
||||
PWM1_SET(PWM1_TBCTL, 0x8D03);//STOP
|
||||
return PWM1_GET(PWM1_TBCNT);
|
||||
}
|
||||
|
||||
Void notify_swi(UArg a0, UArg a1)
|
||||
{
|
||||
u32 requests = logman_notify;
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_NEW_EVENTS)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_EVENTS | ((u32)ev_db.pos<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_NEW_EVENTS;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_NEW_DFR)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_DFR_REG, TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_NEW_DFR;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_NEW_DDR)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_NEW_DDR_REG, TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_NEW_DDR;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_BANK0)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK0|(service_mode<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_BANK0;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_BANK1)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK1|(service_mode<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_BANK1;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_BANK2)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK2|(service_mode<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_BANK2;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_BANK3)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK3|(service_mode<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_BANK3;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_BANK4)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK4|(service_mode<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_BANK4;
|
||||
}
|
||||
|
||||
if(requests & LOGMAN_NOTIFY_BANK5)
|
||||
{
|
||||
Notify_sendEvent(notify.remoteProcId,notify.lineId,notify.eventId, NOTIFY_SEL_BANK5|(service_mode<<8), TRUE);
|
||||
logman_notify&=~LOGMAN_NOTIFY_BANK5;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
volatile u16 pps_low_cnt=0;
|
||||
volatile u16 pps3_timeout_cnt=0xFFFF;
|
||||
|
||||
Void ms_hook(UArg a0, UArg a1)
|
||||
{
|
||||
u32 t_pre,t_post,sync_reg;
|
||||
u8 pps=0;
|
||||
|
||||
t_pre=PWM1_GET(PWM1_TBCNT);
|
||||
|
||||
bus_an_cur_sample_num=bus_an_cur_sample_num_xkhz;//bus_an_cur_sample_num_3khz;
|
||||
|
||||
// gdy IEC SV to cofamy czas/pozycje bufora o obiegi pêtli w celu synchronizacji próbek
|
||||
if(log_manager.status & LOGMAN_USING_IEC_SV)
|
||||
{
|
||||
if(bus_an_cur_sample_num<(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES))
|
||||
bus_an_cur_sample_num=SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2-((SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES)-bus_an_cur_sample_num);
|
||||
else
|
||||
bus_an_cur_sample_num-=(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES);
|
||||
}
|
||||
|
||||
sync_reg = ic->sync_reg;
|
||||
if(sync_reg & (PPS_SYNCED|IRIGB_SYNCED))
|
||||
ext_sync=1;
|
||||
|
||||
|
||||
if(timesync_method==SYNC_METHOD_IEC103||timesync_method==SYNC_METHOD_ZP6||timesync_method==SYNC_METHOD_MLB || (timesync_method==SYNC_METHOD_CUSTOM & !(timesync_bits & CFG_TSYNC_USE_PPS)))
|
||||
ext_sync=0;
|
||||
|
||||
bus_an_cur_timestamp=tstamp_khz;
|
||||
if(log_manager.status & LOGMAN_USING_IEC_SV)
|
||||
{
|
||||
if(bus_an_cur_timestamp<(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES))
|
||||
bus_an_cur_timestamp=SAMPLES_PER_MS*1000-((SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES)-bus_an_cur_timestamp);
|
||||
else
|
||||
bus_an_cur_timestamp-=(SAMPLES_PER_MS*LOOP_CYCLE_MS*SV_WAIT_LOOP_CYCLES);
|
||||
}
|
||||
|
||||
if(!ext_sync)
|
||||
{
|
||||
cur_time.tv_usec+=LOOP_CYCLE_MS;
|
||||
|
||||
if(cur_time.tv_usec>=1000)
|
||||
{
|
||||
cur_time.tv_usec=0;
|
||||
cur_time.tv_sec++;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
u32 usec_prev;
|
||||
usec_prev=cur_time.tv_usec;
|
||||
cur_time.tv_usec=bus_an_cur_timestamp/SAMPLES_PER_MS;
|
||||
if(!cur_time.tv_usec && usec_prev)
|
||||
cur_time.tv_sec++;
|
||||
|
||||
}
|
||||
|
||||
if(pps3_timeout_cnt!=0xFFFF)
|
||||
pps3_timeout_cnt++;
|
||||
|
||||
if(!(IN_DATA01 & (1<<4)))
|
||||
{
|
||||
if(pps_low_cnt<(1000/LOOP_CYCLE_MS))
|
||||
pps_low_cnt++;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(pps_low_cnt>(600/LOOP_CYCLE_MS) && pps_low_cnt<(900/LOOP_CYCLE_MS))
|
||||
{
|
||||
pps=1;
|
||||
pps3_timeout_cnt=0;
|
||||
}
|
||||
|
||||
pps_low_cnt=0;
|
||||
}
|
||||
|
||||
if(((sync_reg & 0x80) && (timesync_method==SYNC_METHOD_IRIG_B || timesync_method==SYNC_METHOD_IRIG_B_ZPRAE || (timesync_method==SYNC_METHOD_CUSTOM && (timesync_bits & CFG_TSYNC_FROM_DSP))))
|
||||
|| (pps && (timesync_method==SYNC_METHOD_CUSTOM && (timesync_bits & CFG_TSYNC_USE_SWPPS)))
|
||||
)
|
||||
{
|
||||
if(cur_time_sw.tv_usec>900)
|
||||
cur_time_sw.tv_sec++;
|
||||
|
||||
//if(pps)
|
||||
// zprae_event_add(1,97);
|
||||
cur_time_sw.tv_usec=0;
|
||||
}
|
||||
else
|
||||
{
|
||||
cur_time_sw.tv_usec+=LOOP_CYCLE_MS;
|
||||
|
||||
if(cur_time_sw.tv_usec>=1000)
|
||||
{
|
||||
cur_time_sw.tv_usec=0;
|
||||
cur_time_sw.tv_sec++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(bus_an_cur_sample_num_prev<=bus_an_cur_sample_num)
|
||||
cur_sample_diff=bus_an_cur_sample_num-bus_an_cur_sample_num_prev;
|
||||
else
|
||||
cur_sample_diff=(u16)bus_an_cur_sample_num+(SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2)-bus_an_cur_sample_num_prev;
|
||||
|
||||
if(cur_sample_diff!=(SAMPLES_PER_MS*LOOP_CYCLE_MS) && sample_watch_init) // debug lost x kHz loops
|
||||
{
|
||||
// if(cur_sample_diff>dbg.delta_period)
|
||||
// dbg.delta_period=cur_sample_diff;
|
||||
dbg.temp_dbg++;
|
||||
}
|
||||
|
||||
bus_an_cur_sample_num_prev = bus_an_cur_sample_num;
|
||||
sample_watch_init=1;
|
||||
|
||||
logman_xkhz();
|
||||
|
||||
t_post=PWM1_GET(PWM1_TBCNT);
|
||||
|
||||
if(t_post>=t_pre)
|
||||
dbg.logman_cycle_time = t_post-t_pre;
|
||||
else
|
||||
dbg.logman_cycle_time = t_post+65536-t_pre;
|
||||
|
||||
if(dbg.logman_cycle_time>dbg.logman_cycle_time_max)
|
||||
dbg.logman_cycle_time_max=dbg.logman_cycle_time;
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
Void ms10_hook(UArg a0, UArg a1)
|
||||
{
|
||||
logman_100hz();
|
||||
}
|
||||
|
||||
Void ms50_hook(UArg a0, UArg a1)
|
||||
{
|
||||
logman_20hz();
|
||||
}
|
||||
|
||||
Void spi_irq(UArg arg)
|
||||
{
|
||||
Hwi_clearInterrupt(14);
|
||||
}
|
||||
|
||||
UInt IntGlobalDisable()
|
||||
{
|
||||
return Hwi_disable();
|
||||
}
|
||||
|
||||
UInt IntGlobalRestore(UInt hwi_key)
|
||||
{
|
||||
Hwi_restore(hwi_key);
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 spi_frame[32];
|
||||
u8 spi_processed=1;
|
||||
|
||||
Void comm_irq(UArg arg)
|
||||
{
|
||||
int i;
|
||||
u32 t_pre,t_post;
|
||||
|
||||
t_pre=PWM1_GET(PWM1_TBCNT);
|
||||
|
||||
bus_an_cur_sample_num_3khz++;
|
||||
bus_an_cur_sample_num_3khz%=(SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2);
|
||||
|
||||
/* Nie potrzebne przy PPS
|
||||
if(!ext_sync && timesync_method!=SYNC_METHOD_IRIG_B && timesync_method!=SYNC_METHOD_IRIG_B_ZPRAE && !(timesync_bits & CFG_TSYNC_FROM_DSP) && ic->spi_reg & 0x01)
|
||||
{
|
||||
if(ic->spi_frame[7]==0x01 && ic->spi_frame[0]==0x68 && ic->spi_frame[31]==0x16 && ic->spi_frame[1]==0x1a && spi_processed)
|
||||
{
|
||||
memcpy(spi_frame,(char *)&ic->spi_frame[0],32);
|
||||
if(mod256_cksum(spi_frame+4,26)==spi_frame[30] && spi_frame[1]==0x1a && spi_frame[7]==0x01 && spi_frame[9]!=0xD5) // time sync req
|
||||
{
|
||||
u16 ms;
|
||||
ms = (u16)spi_frame[9] | ((u16)spi_frame[10]<<8);
|
||||
ms%=1000;
|
||||
|
||||
if(!ext_sync)
|
||||
cur_time.tv_usec = ms;
|
||||
|
||||
cur_time_sw.tv_usec = ms;
|
||||
|
||||
//dbg.temp_dbg++;
|
||||
spi_processed=0;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
spi_processed=1;
|
||||
*/
|
||||
|
||||
for(i=0;i<MAX_AN_CARDS/2;i++)
|
||||
{
|
||||
if((dev_ctrl_state & DEV_CTRL_STATE_TEST_AN) && an_gen_buf_ready && (i<MAX_AN_CARDS/2))
|
||||
{
|
||||
if(!(genpar.an_force_mask & (1<< ((i<<2)+(0)))))
|
||||
bus_an_samples_buf[i][0][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][0]?(65534-((u16)ic->an_in[i].l1 + 32767)):((u16)ic->an_in[i].l1 + 32767);
|
||||
|
||||
if(!(genpar.an_force_mask & (1<< ((i<<2)+(1)))))
|
||||
bus_an_samples_buf[i][1][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][1]?(65534-((u16)ic->an_in[i].l2 + 32767)):((u16)ic->an_in[i].l2 + 32767);
|
||||
|
||||
if(!(genpar.an_force_mask & (1<< ((i<<2)+(2)))))
|
||||
bus_an_samples_buf[i][2][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][2]?(65534-((u16)ic->an_in[i].l3 + 32767)):((u16)ic->an_in[i].l3 + 32767);
|
||||
|
||||
if(!(genpar.an_force_mask & (1<< ((i<<2)+(3)))))
|
||||
bus_an_samples_buf[i][3][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][3]?(65534-((u16)ic->an_in[i].l4 + 32767)):((u16)ic->an_in[i].l4 + 32767);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
bus_an_samples_buf[i][0][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][0]?(65534-((u16)ic->an_in[i].l1 + 32767)):((u16)ic->an_in[i].l1 + 32767);
|
||||
bus_an_samples_buf[i][1][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][1]?(65534-((u16)ic->an_in[i].l2 + 32767)):((u16)ic->an_in[i].l2 + 32767);
|
||||
bus_an_samples_buf[i][2][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][2]?(65534-((u16)ic->an_in[i].l3 + 32767)):((u16)ic->an_in[i].l3 + 32767);
|
||||
bus_an_samples_buf[i][3][bus_an_cur_sample_num_3khz]=bus_an_samples_neg[i][3]?(65534-((u16)ic->an_in[i].l4 + 32767)):((u16)ic->an_in[i].l4 + 32767);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(loops_synced)
|
||||
{
|
||||
if(!--khz_trigger)
|
||||
{
|
||||
bus_an_cur_sample_num_xkhz=bus_an_cur_sample_num_3khz;
|
||||
tstamp_khz=ic->sample_sync_no;
|
||||
Swi_post(swi_ms);
|
||||
khz_trigger=SAMPLES_PER_MS*LOOP_CYCLE_MS;
|
||||
}
|
||||
//Swi_dec(swi_1ms);
|
||||
Swi_dec(swi_10ms);
|
||||
Swi_dec(swi_50ms);
|
||||
}
|
||||
|
||||
if(!loops_synced && (ic->sample_sync_no==0))
|
||||
{
|
||||
loops_synced=1;
|
||||
bus_an_cur_sample_num_3khz=0; //dodano przy okazji SV
|
||||
}
|
||||
|
||||
//dodano na wszelki wypadek, bo czasem pêtle siê nie synchronizowa³y, dlaczego? FPGA?
|
||||
//trzeba to sprawdzic bo moze byc skutek uboczny || zakomentowano jednak po poprawie sync na 2ms w fpga
|
||||
//if(ic->sample_sync_no==0)
|
||||
// khz_trigger=LOOP_CYCLE_MS * SAMPLES_PER_MS;
|
||||
//
|
||||
|
||||
i=ic->sample_no;
|
||||
|
||||
if(is_first_sample)
|
||||
is_first_sample=0;
|
||||
else
|
||||
samples_dropped+=(i - last_sample_no)-1;
|
||||
|
||||
last_sample_no=i;
|
||||
|
||||
t_post=PWM1_GET(PWM1_TBCNT);
|
||||
|
||||
if(t_post>=t_pre)
|
||||
dbg.irq_time = t_post-t_pre;
|
||||
else
|
||||
dbg.irq_time = t_post+65536-t_pre;
|
||||
}
|
||||
|
||||
void configure_pwr_ok_gpio()
|
||||
{
|
||||
KICK0R=KICK0R_VAL;
|
||||
KICK1R=KICK1R_VAL;
|
||||
|
||||
PINMUX0=(PINMUX0 & ~(PINMUX3_15_12)) | (0x08 << 12); // pwr1_ok GP0[12] as GPIO
|
||||
PINMUX1=(PINMUX1 & ~(PINMUX3_11_8)) | (0x08 << 8); // pwr2_ok GP0[5] as GPIO
|
||||
PINMUX1=(PINMUX1 & ~(PINMUX3_15_12)) | (0x08 << 12); // pps3 GP0[4] as GPIO
|
||||
PINMUX2=(PINMUX2 & ~(PINMUX3_19_16)) | (0x04 << 16); // gp1[11] (PPS from GPS) as GPIO
|
||||
|
||||
DIR01|=((1<<4)|(1<<5)|(1<<12)|(1<<27)); // gp0.4, gp0.5, gp0.12 and gp1 .11 as input
|
||||
PUPD_ENA|=((1<<0)|(1<<2)); // enable pull up/down control 1<<5 == GP1[11]
|
||||
PUPD_ENA&=~(1<<5); // disable pull up/down for gp1[11]
|
||||
PUPD_SEL|=((1<<0)|(1<<2)); // set pull up
|
||||
}
|
||||
|
||||
/*
|
||||
** Interrupt Handler for Core 0 Receive interrupt
|
||||
*/
|
||||
void EMACCore0RxIsr(void)
|
||||
{
|
||||
lwIPRxIntHandler(0);
|
||||
}
|
||||
|
||||
/*
|
||||
** Interrupt Handler for Core 0 Transmit interrupt
|
||||
*/
|
||||
void EMACCore0TxIsr(void)
|
||||
{
|
||||
lwIPTxIntHandler(0);
|
||||
}
|
||||
|
||||
Void main()
|
||||
{
|
||||
Task_Handle task,task2;
|
||||
|
||||
memset((u8*)&dbg,0,sizeof(dbg));
|
||||
ic->sync_reg|=NEG_PPS_IN;
|
||||
|
||||
task = Task_create(commFxn, NULL, NULL);
|
||||
Task_setPri(task,3);
|
||||
|
||||
if (task == NULL) {
|
||||
BIOS_exit(0);
|
||||
}
|
||||
|
||||
task2 = Task_create(spiFxn, NULL, NULL);
|
||||
Task_setPri(task2,2);
|
||||
|
||||
if (task2 == NULL) {
|
||||
BIOS_exit(0);
|
||||
}
|
||||
|
||||
analog_inputs_init();
|
||||
|
||||
logman_init();
|
||||
|
||||
Swi_Params_init(&swi_ms_params);
|
||||
swi_ms_params.priority = 15;
|
||||
|
||||
swi_ms_params.trigger = SAMPLES_PER_MS * LOOP_CYCLE_MS; // every x samples
|
||||
swi_ms = Swi_create(&ms_hook,&swi_ms_params,NULL);
|
||||
|
||||
Swi_Params_init(&swi_10ms_params);
|
||||
swi_10ms_params.priority = 10;
|
||||
swi_10ms_params.trigger = SAMPLES_PER_MS * 10; // (10 ms)
|
||||
swi_10ms = Swi_create(&ms10_hook,&swi_10ms_params,NULL);
|
||||
|
||||
Swi_Params_init(&swi_50ms_params);
|
||||
swi_50ms_params.priority = 8;
|
||||
swi_50ms_params.trigger = SAMPLES_PER_MS * 50; // (50 ms)
|
||||
swi_50ms = Swi_create(&ms50_hook,&swi_50ms_params,NULL);
|
||||
|
||||
Swi_Params_init(&swi_notify_params);
|
||||
swi_notify_params.priority = 1;
|
||||
swi_notify_params.trigger = 1;
|
||||
swi_notify = Swi_create(¬ify_swi,&swi_notify_params,NULL);
|
||||
|
||||
SET_RIS_TRIG8 = (1<<15); // rising edge trig from GP8.15
|
||||
|
||||
configure_pwr_ok_gpio();
|
||||
pwm_init();
|
||||
pwm_start_cnt();
|
||||
|
||||
// eth.hwaddr[0]=0xC4;
|
||||
// eth.hwaddr[1]=0xff;
|
||||
// eth.hwaddr[2]=0xBC;
|
||||
// eth.hwaddr[3]=0x70;
|
||||
// eth.hwaddr[4]=0x14;
|
||||
// eth.hwaddr[5]=0x3f;
|
||||
//lwIPInit(0, eth.hwaddr, eth.ip, eth.netmask, eth.gateway, IPADDR_USE_STATIC);
|
||||
//Hwi_enableInterrupt(10);
|
||||
//Hwi_enableInterrupt(11);
|
||||
|
||||
BIOS_start(); /* enable interrupts and start SYS/BIOS */
|
||||
}
|
||||
349
src/misc.c
Normal file
349
src/misc.c
Normal file
@@ -0,0 +1,349 @@
|
||||
/*
|
||||
* misc.c
|
||||
*
|
||||
* Created on: 10-09-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#include "misc.h"
|
||||
#include <time.h>
|
||||
#include "tdefs.h"
|
||||
#include <string.h>
|
||||
#include "config.h"
|
||||
|
||||
volatile u16 kob_bin_ench=0;
|
||||
volatile u16 mwd32_mask=0;
|
||||
|
||||
u16 bus_out_data[MAX_OUT_CARDS];
|
||||
u16 bus_out_data_test[MAX_OUT_CARDS];
|
||||
u16 force_bus_out_data[MAX_OUT_CARDS];
|
||||
|
||||
u8 bus_bin_data[MAX_BIN_CARDS];
|
||||
u8 force_bus_bin_data[MAX_BIN_CARDS];
|
||||
u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
|
||||
u8 bus_bin_data_ench[MAX_BIN_CARDS];
|
||||
u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
|
||||
|
||||
u8 bus_an_samples_neg[MAX_AN_CARDS][4];
|
||||
u16 bus_an_samples_buf[MAX_AN_CARDS][4][SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2];
|
||||
u8 bus_an_cur_sample_num_3khz = 0;
|
||||
u8 bus_an_cur_sample_num_xkhz = 0;
|
||||
|
||||
u16 tstamp_khz = 0;
|
||||
|
||||
u8 bus_an_cur_sample_num = 0;
|
||||
u32 logman_notify = 0;
|
||||
volatile u8 ext_sync=0;
|
||||
volatile u32 timesync_method=0;
|
||||
volatile u32 timesync_bits=0;
|
||||
volatile struct in_cards *ic = (struct in_cards *)IN_CARDS_BASE_ADDR;
|
||||
struct debug_info dbg;
|
||||
|
||||
const uint8_t _ytab[2][12] ={ { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } ,
|
||||
{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 } };
|
||||
|
||||
|
||||
static int is_leap(unsigned y)
|
||||
{
|
||||
y += 1900;
|
||||
return (y % 4) == 0 && ((y % 100) != 0 || (y % 400) == 0);
|
||||
}
|
||||
|
||||
|
||||
uint32_t timegm (const struct tm *tm)
|
||||
{
|
||||
uint32_t res = 0;
|
||||
uint16_t i;
|
||||
|
||||
for (i = 70; i < tm->tm_year; ++i)
|
||||
res += is_leap(i) ? 366 : 365;
|
||||
|
||||
for (i = 0; i < tm->tm_mon; ++i)
|
||||
res += _ytab[is_leap(tm->tm_year)][i];
|
||||
|
||||
res += tm->tm_mday - 1;
|
||||
res *= 24;
|
||||
res += tm->tm_hour;
|
||||
res *= 60;
|
||||
res += tm->tm_min;
|
||||
res *= 60;
|
||||
res += tm->tm_sec;
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
void my_gmtime(const uint32_t *timer, struct tm *timep)
|
||||
{
|
||||
uint32_t time = *timer;
|
||||
|
||||
u32 dayclock, dayno;
|
||||
int16_t year = EPOCH_YR;
|
||||
|
||||
dayclock = time % SECS_DAY;
|
||||
dayno = time / SECS_DAY;
|
||||
|
||||
timep->tm_sec = dayclock % 60;
|
||||
timep->tm_min = (dayclock % 3600) / 60;
|
||||
timep->tm_hour = dayclock / 3600;
|
||||
timep->tm_wday = (dayno + 4) % 7; /* day 0 was a thursday */
|
||||
while (dayno >= YEARSIZE(year)) {
|
||||
dayno -= YEARSIZE(year);
|
||||
year++;
|
||||
}
|
||||
timep->tm_year = year - YEAR0;
|
||||
timep->tm_yday = dayno;
|
||||
timep->tm_mon = 0;
|
||||
while (dayno >= _ytab[LEAPYEAR(year)][timep->tm_mon]) {
|
||||
dayno -= _ytab[LEAPYEAR(year)][timep->tm_mon];
|
||||
timep->tm_mon++;
|
||||
}
|
||||
timep->tm_mday = dayno + 1;
|
||||
|
||||
timep->tm_isdst = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
isindst() - check if date is in daylight save time
|
||||
|
||||
cest_cet_n - 1 when source tm is a summer time, 0 - winter
|
||||
*/
|
||||
|
||||
uint8_t isindst(struct tm *tb, uint8_t cest_cet_n)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
if (tb->tm_mon < 2 || tb->tm_mon > 9)
|
||||
return 0;
|
||||
|
||||
if (tb->tm_mon > 2 && tb->tm_mon < 9)
|
||||
return 1;
|
||||
|
||||
tmp=7 - tb->tm_wday + tb->tm_mday;
|
||||
|
||||
if(tb->tm_mon==2) /* march */
|
||||
{
|
||||
if(tmp>31)
|
||||
{
|
||||
if(tb->tm_wday==0)
|
||||
{
|
||||
if ((!cest_cet_n && tb->tm_hour>=2)||(cest_cet_n && tb->tm_hour>=3)) /* it's the last sunday */
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
if(tb->tm_mon==9) /* october */
|
||||
{
|
||||
if(tmp>31)
|
||||
{
|
||||
if(tb->tm_wday==0)
|
||||
{
|
||||
if ((!cest_cet_n && tb->tm_hour>=2)||(cest_cet_n && tb->tm_hour>=3)) /* it's the last sunday */
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
struct time_data irigb_process_frame()
|
||||
{
|
||||
u8 i;
|
||||
u8 tmp_secs;
|
||||
u8 tmp_mins;
|
||||
u8 tmp_hour;
|
||||
u8 tmp_month;
|
||||
u8 tmp_mday;
|
||||
u16 tmp_year;
|
||||
u16 tmp_yearday;
|
||||
u16 tmp;
|
||||
u16 tmp2;
|
||||
uint32_t secs;
|
||||
struct tm tim;
|
||||
struct time_data irigb_time;
|
||||
|
||||
if(ic->sync_reg & 0x4000) // IRIG-B sync
|
||||
{
|
||||
tmp = ic->irigb_p[0] & 0x01FF;
|
||||
tmp_secs = (((tmp & 0x1C0) >> 6)*10) + ((tmp>>1) & 0x00F);
|
||||
|
||||
tmp = ic->irigb_p[1] & 0x01FF;
|
||||
tmp_mins = (((tmp & 0xE0) >> 5)*10) + (tmp & 0x00F);
|
||||
|
||||
tmp = ic->irigb_p[2] & 0x01FF;
|
||||
tmp_hour = (((tmp & 0x60) >> 5)*10) + (tmp & 0x00F);
|
||||
|
||||
tmp = ic->irigb_p[3] & 0x01FF;
|
||||
tmp_yearday = (((tmp & 0x01E0) >> 5)*10) + (tmp & 0x00F);
|
||||
tmp = ic->irigb_p[4] & 0x01FF;
|
||||
tmp_yearday+=((tmp & 0x03)*100);
|
||||
|
||||
tmp = ic->irigb_p[5] & 0x01FF;
|
||||
tmp_year = (((tmp & 0x1E0) >> 5)*10) + (tmp & 0x00F);
|
||||
tmp_year+=2000;
|
||||
|
||||
tmp2=0;
|
||||
|
||||
if(LEAPYEAR(tmp_year))
|
||||
{
|
||||
for(i=0;i<12;i++)
|
||||
{
|
||||
tmp2+=_ytab[1][i];
|
||||
if(tmp_yearday<=tmp2)
|
||||
break;
|
||||
}
|
||||
tmp_mday=tmp_yearday-(tmp2-_ytab[1][i]);
|
||||
}
|
||||
else
|
||||
{
|
||||
for(i=0;i<12;i++)
|
||||
{
|
||||
tmp2+=_ytab[0][i];
|
||||
if(tmp_yearday<=tmp2)
|
||||
break;
|
||||
}
|
||||
tmp_mday=tmp_yearday-(tmp2-_ytab[0][i]);
|
||||
}
|
||||
|
||||
tmp_month=i+1;
|
||||
tmp_year-=1900;
|
||||
|
||||
tmp = (ic->irigb_p[6]) & 0x0000001F;
|
||||
irigb_time.fix_sat=tmp;
|
||||
irigb_time.day=tmp_mday;
|
||||
irigb_time.month=tmp_month-1;
|
||||
irigb_time.year=tmp_year;
|
||||
irigb_time.hour=tmp_hour;
|
||||
irigb_time.min=tmp_mins;
|
||||
irigb_time.sec=tmp_secs;
|
||||
|
||||
tim.tm_hour = irigb_time.hour;
|
||||
tim.tm_min = irigb_time.min;
|
||||
tim.tm_sec = irigb_time.sec;
|
||||
|
||||
tim.tm_mday = irigb_time.day;
|
||||
tim.tm_mon = irigb_time.month;
|
||||
tim.tm_year = irigb_time.year;
|
||||
|
||||
secs=timegm(&tim);
|
||||
my_gmtime(&secs,&tim);
|
||||
|
||||
if(isindst(&tim,0))
|
||||
{
|
||||
tim.tm_hour-=2; /* DST adjust is done by the GPS-Synchro IRIG-B modified protocol */
|
||||
tim.tm_isdst=1;
|
||||
}
|
||||
else
|
||||
tim.tm_hour-=1;
|
||||
|
||||
irigb_time.secs=timegm(&tim)+1;
|
||||
|
||||
// if(!validate_time(&irigb_time))
|
||||
{
|
||||
/* ctime.tv_sec=irigb_time.secs;
|
||||
|
||||
time_flags&=~TIME_INVALID;
|
||||
|
||||
if(tim.tm_isdst)
|
||||
time_flags|=TIME_SUMMER;
|
||||
else
|
||||
time_flags&=~TIME_SUMMER;*/
|
||||
}
|
||||
}
|
||||
else
|
||||
memset((u8 *)&irigb_time,0,sizeof(irigb_time));
|
||||
|
||||
return irigb_time;
|
||||
}
|
||||
|
||||
void reload_ic_cfg()
|
||||
{
|
||||
memcpy((void*)ic->bin_ac_mask,(void*)dev_cfg.mwd_ac_mask,sizeof(ic->bin_ac_mask));
|
||||
}
|
||||
|
||||
u8 mod256_cksum(uint8_t *buf, u32 len)
|
||||
{
|
||||
uint8_t cksum;
|
||||
u32 i;
|
||||
|
||||
cksum=0;
|
||||
|
||||
for(i=0;i<len;i++)
|
||||
cksum+=*(buf++);
|
||||
|
||||
return cksum;
|
||||
}
|
||||
|
||||
int asn_parse(u8 **buf,int *bytes_left, u8 *tag)
|
||||
{
|
||||
int len = 0;
|
||||
u8 oct;
|
||||
|
||||
*tag=**buf;
|
||||
(*buf)++;
|
||||
(*bytes_left)--;
|
||||
|
||||
|
||||
if(**buf & 0x80)
|
||||
{
|
||||
oct = **buf&0x7f;
|
||||
if(oct>2 || oct==0) // too long for us
|
||||
return -1;
|
||||
|
||||
(*buf)++;
|
||||
(*bytes_left)--;
|
||||
|
||||
while(oct && *bytes_left)
|
||||
{
|
||||
len|=**buf;
|
||||
oct--;
|
||||
(*bytes_left)--;
|
||||
(*buf)++;
|
||||
if(oct)
|
||||
len<<=8;
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
len = **buf;
|
||||
(*bytes_left)--;
|
||||
(*buf)++;
|
||||
}
|
||||
|
||||
if (*bytes_left<len)
|
||||
return -1;
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
void analog_inputs_init()
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=0;i<MAX_AN_CARDS;i++)
|
||||
{
|
||||
ic->an_offset[i].l1=32767;
|
||||
ic->an_offset[i].l2=32767;
|
||||
ic->an_offset[i].l3=32767;
|
||||
ic->an_offset[i].l4=32767;
|
||||
}
|
||||
|
||||
bus_an_cur_sample_num_3khz = 0;
|
||||
bus_an_cur_sample_num = 0;
|
||||
memset(bus_an_samples_buf,0,sizeof(bus_an_samples_buf));
|
||||
}
|
||||
351
src/misc.h
Normal file
351
src/misc.h
Normal file
@@ -0,0 +1,351 @@
|
||||
/*
|
||||
* misc.h
|
||||
*
|
||||
* Created on: 30-07-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#ifndef MISC_H_
|
||||
#define MISC_H_
|
||||
|
||||
#include "tdefs.h"
|
||||
#include "logman.h"
|
||||
#include "config.h"
|
||||
|
||||
#include <ti/sysbios/hal/Timer.h>
|
||||
#include <ti/sysbios/knl/Semaphore.h>
|
||||
#include <ti/sysbios/knl/Swi.h>
|
||||
|
||||
#define MAX_AN_CARDS 16
|
||||
#define MAX_BIN_CARDS 16
|
||||
#define MAX_OUT_CARDS 16
|
||||
|
||||
#define NEED_RELOAD_IC 0x01
|
||||
|
||||
#define IN_CARDS_BASE_ADDR 0x64000000
|
||||
|
||||
extern u32 logman_notify;
|
||||
|
||||
#define LOGMAN_NOTIFY_NEW_EVENTS 0x01
|
||||
#define LOGMAN_NOTIFY_NEW_DFR 0x02
|
||||
#define LOGMAN_NOTIFY_NEW_DDR 0x04
|
||||
#define LOGMAN_NOTIFY_BANK0 0x08
|
||||
#define LOGMAN_NOTIFY_BANK1 0x10
|
||||
#define LOGMAN_NOTIFY_BANK2 0x20
|
||||
#define LOGMAN_NOTIFY_BANK3 0x40
|
||||
#define LOGMAN_NOTIFY_BANK4 0x80
|
||||
#define LOGMAN_NOTIFY_BANK5 0x100
|
||||
|
||||
extern volatile short analog_buf[127];
|
||||
extern volatile int shared_buf[1024];
|
||||
extern volatile int analog_buf_ready;
|
||||
extern volatile int analog_buf_cnt;
|
||||
extern unsigned int analog_buf_card;
|
||||
extern unsigned int analog_buf_channel;
|
||||
extern volatile unsigned short samples_dropped;
|
||||
extern volatile struct timeval cur_time;
|
||||
extern volatile struct timeval cur_time_sw;
|
||||
extern volatile u8 ext_sync;
|
||||
extern volatile u8 have;
|
||||
extern u8 cur_sample_diff;
|
||||
extern int omapl138EthSendPacket(u8 *buf,u16 len);
|
||||
extern int asn_parse(u8 **buf,int *bytes_left, u8 *tag);
|
||||
|
||||
extern u8 bus_an_samples_neg[MAX_AN_CARDS][4];
|
||||
enum arg_type { ARG_TYPE_BOOL = 0, ARG_TYPE_TEXT = 1, ARG_TYPE_DOUBLE = 2, ARG_TYPE_LONG = 3 };
|
||||
|
||||
struct timeval
|
||||
{
|
||||
u32 tv_sec; /* seconds */
|
||||
u32 tv_usec; /* and microseconds */
|
||||
};
|
||||
|
||||
struct parsed_cfg_transport_line
|
||||
{
|
||||
char name[32];
|
||||
enum arg_type type;
|
||||
char text_val[256];
|
||||
double double_val;
|
||||
long int long_val;
|
||||
unsigned char bool_val;
|
||||
};
|
||||
|
||||
struct klapacz_config
|
||||
{
|
||||
unsigned int interval1;
|
||||
unsigned int interval2;
|
||||
};
|
||||
|
||||
struct device_config
|
||||
{
|
||||
unsigned char mwd_ac_mask[MAX_OUT_CARDS];
|
||||
unsigned int bits;
|
||||
};
|
||||
|
||||
extern struct device_config dev_cfg;
|
||||
|
||||
|
||||
struct config_lookup_table
|
||||
{
|
||||
char name[32];
|
||||
enum arg_type type;
|
||||
void *addr;
|
||||
unsigned char size;
|
||||
unsigned char bit_mask;
|
||||
unsigned char flags;
|
||||
};
|
||||
|
||||
#define CFG_BIT_KLAPACZ_ENABLED (1<<4)
|
||||
|
||||
extern struct klapacz_config klap_cfg;
|
||||
|
||||
/* CPU registers */
|
||||
#define SET_RIS_TRIG67 *((volatile int*)0x01E2609C)
|
||||
#define SET_RIS_TRIG8 *((volatile int*)0x01E260C4)
|
||||
#define INTSTAT67 *((volatile int*)0x01E260AC)
|
||||
|
||||
#define PINMUX0 *((volatile int*)0x01C14120)
|
||||
#define PINMUX1 *((volatile int*)0x01C14124)
|
||||
#define PINMUX2 *((volatile int*)0x01C14128)
|
||||
#define PINMUX3 *((volatile int*)0x01C1412C)
|
||||
#define PINMUX7 *((volatile int*)0x01C1413C)
|
||||
#define DIR8 *((volatile int*)0x01E260B0)
|
||||
#define SETDATA8 *((volatile int*)0x01E260B8)
|
||||
#define CLRDATA8 *((volatile int*)0x01E260BC)
|
||||
#define SPIGCR0 *((volatile int*)0x01C41000)
|
||||
#define SPIGCR1 *((volatile int*)0x01C41004)
|
||||
#define SPIPC0 *((volatile int*)0x01C41014)
|
||||
#define SPIDAT0 *((volatile int*)0x01C41038)
|
||||
#define SPIDAT1 *((volatile int*)0x01C4103C)
|
||||
#define SPIFMT0 *((volatile int*)0x01C41050)
|
||||
#define SPIGCR1 *((volatile int*)0x01C41004)
|
||||
#define SPIINT0 *((volatile int*)0x01C41008)
|
||||
#define SPILVL *((volatile int*)0x01C4100C)
|
||||
#define SPIBUF *((volatile int*)0x01C41040)
|
||||
#define SPIFLG *((volatile int*)0x01C41010)
|
||||
|
||||
#define DIR01 *((volatile int*)0x01E26010)
|
||||
#define IN_DATA01 *((volatile int*)0x01E26020)
|
||||
|
||||
#define PUPD_ENA *((volatile int*)0x01E2C00C)
|
||||
#define PUPD_SEL *((volatile int*)0x01E2C010)
|
||||
|
||||
#define KICK0R *((volatile int*)0x01C14038)
|
||||
#define KICK1R *((volatile int*)0x01C1403C)
|
||||
|
||||
#define KICK0R_VAL 0x83E70B13
|
||||
#define KICK1R_VAL 0x95A4F1E0
|
||||
|
||||
#define PINMUX3_3_0 0x0000000F
|
||||
#define PINMUX3_11_8 0x00000F00
|
||||
#define PINMUX3_15_12 0x0000F000
|
||||
#define PINMUX3_19_16 0x000F0000
|
||||
#define PINMUX3_31_28 0xF0000000
|
||||
|
||||
|
||||
// PSC
|
||||
#define PTCMD *((volatile int*)0x01C10120)
|
||||
#define PTSTAT *((volatile int*)0x01C10128)
|
||||
#define MDCTL4 *((volatile int*)0x01C10A10)
|
||||
#define MDSTAT4 *((volatile int*)0x01C10810)
|
||||
#define MDSTAT10 *((volatile int*)0x01E27828)
|
||||
|
||||
extern Semaphore_Handle spi_semaphore;
|
||||
|
||||
extern volatile int was_irq;
|
||||
extern u16 bus_an_cur_timestamp;
|
||||
extern u8 bus_an_cur_sample_num_xkhz;
|
||||
extern u16 tstamp_khz;
|
||||
|
||||
struct an_card
|
||||
{
|
||||
short l1;
|
||||
short l2;
|
||||
short l3;
|
||||
short l4;
|
||||
};
|
||||
|
||||
//mux
|
||||
#define C37_MUX_BUFSIZE 256
|
||||
|
||||
//mux bits
|
||||
#define MUX_REG_CHAN_NUM_OFFSET 12
|
||||
#define MUX_REG_EXT_CLK (1<<11)
|
||||
#define MUX_REG_WR (1<<10)
|
||||
#define MUX_REG_SKIP_FF (1<<9)
|
||||
#define MUX_REG_TX_BYTES_MASK 0x00FF
|
||||
|
||||
//
|
||||
#define MUX_STATE_ERR (1<<15)
|
||||
#define MUX_STATE_ERR_CNT_MASK 0x7E00
|
||||
#define MUX_STATE_ERR_CNT_OFFSET 9
|
||||
#define MUX_STATE_RX_BYTES_MASK 0x00FF
|
||||
#define MUX_STATE_YELLOW_BIT_IN (1<<14)
|
||||
|
||||
#define YEAR0 1900 /* the first year */
|
||||
#define EPOCH_YR 1970 /* EPOCH = Jan 1 1970 00:00:00 */
|
||||
#define SECS_DAY (24L * 60L * 60L)
|
||||
#define LEAPYEAR(year) (!((year) % 4) && (((year) % 100) || !((year) % 400)))
|
||||
#define YEARSIZE(year) (LEAPYEAR(year) ? 366 : 365)
|
||||
#define FIRSTSUNDAY(timp) (((timp)->tm_yday - (timp)->tm_wday + 420) % 7)
|
||||
#define FIRSTDAYOF(timp) (((timp)->tm_wday - (timp)->tm_yday + 420) % 7)
|
||||
#define TIME_MAX ULONG_MAX
|
||||
#define ABB_LEN 3
|
||||
|
||||
struct time_data
|
||||
{
|
||||
uint8_t hour;
|
||||
uint8_t min;
|
||||
uint8_t sec;
|
||||
uint8_t day;
|
||||
uint8_t month;
|
||||
uint8_t year;
|
||||
uint32_t secs;
|
||||
uint8_t fix_sat;
|
||||
};
|
||||
|
||||
struct in_cards
|
||||
{
|
||||
struct an_card an_in[MAX_AN_CARDS];
|
||||
unsigned char bin_in[MAX_BIN_CARDS];
|
||||
unsigned short out_set[MAX_OUT_CARDS];
|
||||
unsigned char bin_ac_mask[MAX_BIN_CARDS];
|
||||
unsigned short unused[32];
|
||||
struct an_card an_offset[MAX_AN_CARDS];
|
||||
unsigned short reverse_curr;
|
||||
unsigned short kob_an;
|
||||
unsigned short kob_bin;
|
||||
unsigned short kob_out;
|
||||
unsigned short an_errs;
|
||||
unsigned short bin_errs;
|
||||
unsigned short out_errs;
|
||||
unsigned short valid_an_samples;
|
||||
unsigned short sample_no;
|
||||
unsigned short spi_reg;
|
||||
signed short delta_period_50M; //202
|
||||
signed short phase_corr; //203
|
||||
unsigned short sync_reg; //204 // bit15-synced pps, 14-synced irig, 13-4kHz imp 0-neg out pps
|
||||
unsigned short fpga_verl;
|
||||
unsigned short fpga_verh;
|
||||
unsigned short sample_sync_no;
|
||||
unsigned short mux_reg;
|
||||
unsigned short mux_state;
|
||||
unsigned short mux2_reg;
|
||||
unsigned short mux2_state;
|
||||
unsigned char mux_shift;
|
||||
unsigned char mux2_shift;
|
||||
unsigned short irigb_p[10];
|
||||
unsigned short eof;
|
||||
unsigned char bin_in_ench[MAX_BIN_CARDS];
|
||||
unsigned char bin_ac_mask_ench[MAX_BIN_CARDS];
|
||||
unsigned short mwd32_present;
|
||||
unsigned short padding[800-512-16-1];
|
||||
unsigned char mux_indata[C37_MUX_BUFSIZE];
|
||||
unsigned char mux_outdata[C37_MUX_BUFSIZE];
|
||||
unsigned char mux2_indata[C37_MUX_BUFSIZE];
|
||||
unsigned char mux2_outdata[C37_MUX_BUFSIZE];
|
||||
unsigned char spi_frame[2048];
|
||||
};
|
||||
|
||||
// sync reg
|
||||
#define PPS_SYNCED 0x8000
|
||||
#define IRIGB_SYNCED 0x4000
|
||||
#define NEG_PPS_IN 0x0002
|
||||
#define NEG_PPS_OUT 0x0004
|
||||
#define MKI_PPS_IN 0x0008
|
||||
|
||||
struct time_data irigb_process_frame();
|
||||
|
||||
extern volatile u32 timesync_method;
|
||||
extern volatile u32 timesync_bits;
|
||||
extern volatile u16 pps3_timeout_cnt;
|
||||
|
||||
extern volatile u16 kob_bin_ench;
|
||||
extern volatile u16 mwd32_mask;
|
||||
|
||||
#define SYNC_METHOD_MGB 0x00 // standardowo czas z MGB + PPS
|
||||
#define SYNC_METHOD_MKI 0x01 // MGB + MKI4 + PPS
|
||||
#define SYNC_METHOD_MKI_PTP 0x02 // MKI7 + PPS
|
||||
#define SYNC_METHOD_IEC103 0x03 // IEC103
|
||||
#define SYNC_METHOD_IRIG_B_ZPRAE 0x04 // IRIG_B Proto ZPrAE
|
||||
#define SYNC_METHOD_IRIG_B 0x05 // IRIG_B
|
||||
#define SYNC_METHOD_ZP6 0x06 // ZP6 z uwzglednieniem milisekund
|
||||
#define SYNC_METHOD_MLB 0x07 // ZP6 z uwzglednieniem milisekund, nie przyjmowanie od MGB czasu
|
||||
#define SYNC_METHOD_CUSTOM 0xFF
|
||||
|
||||
|
||||
#define CFG_TSYNC_ACCEPT_FROM_MGB (1<<0)
|
||||
#define CFG_TSYNC_ACCEPT_FROM_ETH_AND_RS (1<<1)
|
||||
#define CFG_TSYNC_ACCEPT_IEC103 (1<<2)
|
||||
#define CFG_TSYNC_FROM_DSP (1<<3)
|
||||
#define CFG_TSYNC_USE_PPS (1<<4)
|
||||
#define CFG_TSYNC_USE_SWPPS (1<<6)
|
||||
#define CFG_TSYNC_USE_SWCLK (1<<7)
|
||||
|
||||
struct debug_info
|
||||
{
|
||||
u32 tick_period;
|
||||
u32 logman_cycle_time;
|
||||
u32 logman_cycle_time_max;
|
||||
u32 logman_buf_size_cur;
|
||||
u32 logman_buf_capacity;
|
||||
u32 irq_time;
|
||||
u32 logman_cycle_period;
|
||||
u32 logman_cycle_period_max;
|
||||
volatile u32 temp_dbg;
|
||||
short delta_period;
|
||||
short phase_corr;
|
||||
unsigned short sync_reg;
|
||||
unsigned short max_elements;
|
||||
unsigned short used_elements;
|
||||
unsigned short nets_bufsize;
|
||||
}__attribute__((__packed__));
|
||||
|
||||
extern struct debug_info dbg;
|
||||
|
||||
// spi reg
|
||||
#define SPI_GOT_FRAME 0x01
|
||||
#define SPI_ALLOW_FRAME_N 0x01
|
||||
#define SPI_ANSWER_READY 0x02
|
||||
#define SPI_NEW_EVENTS 0x04
|
||||
|
||||
extern volatile struct in_cards *ic;
|
||||
extern void reload_ic_cfg();
|
||||
extern void ms_hook();
|
||||
extern void analog_inputs_init();
|
||||
|
||||
#define PI 3.14159265
|
||||
|
||||
#define CKSUM_IV 0xAB /* config cksum init vector */
|
||||
extern u8 mod256_cksum(uint8_t *buf, u32 len);
|
||||
extern u8 bus_an_cur_sample_num_3khz;
|
||||
extern u8 bus_an_cur_sample_num;
|
||||
extern u16 bus_an_samples_buf[MAX_AN_CARDS][4][SAMPLES_PER_MS*MAIN_FREQ_PERIOD_MS*2];
|
||||
extern u16 bus_out_data[MAX_OUT_CARDS];
|
||||
extern u8 bus_bin_data[MAX_BIN_CARDS];
|
||||
extern u16 force_bus_out_data[MAX_OUT_CARDS];
|
||||
extern u8 force_bus_bin_data[MAX_BIN_CARDS];
|
||||
extern u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
|
||||
extern u16 bus_out_data_test[MAX_OUT_CARDS];
|
||||
|
||||
extern u8 bus_bin_data_ench[MAX_BIN_CARDS];
|
||||
extern u8 force_bus_bin_data_ench[MAX_BIN_CARDS];
|
||||
|
||||
extern Swi_Handle swi_notify;
|
||||
|
||||
#define PWM1_SET(x,y) *((volatile uint16_t*)x) = y
|
||||
#define PWM1_GET(x) *((volatile uint16_t*)x)
|
||||
|
||||
#define PWM1_BEG 0x01F02000
|
||||
#define PWM1_TBCTL 0x01F02000
|
||||
#define PWM1_TBCNT 0x01F02008
|
||||
#define PWM1_TBPRD 0x01F0200A
|
||||
#define PWM1_CMPA 0x01F02012
|
||||
#define PWM1_CMPB 0x01F02014
|
||||
#define PWM1_AQCTLA 0x01F02016
|
||||
#define PWM1_ETSEL 0x01F02032
|
||||
#define PWM1_ETPS 0x01F02034
|
||||
#define PWM1_ETCLR 0x01F02038
|
||||
#define PWM1_ETFRC 0x01F0203A
|
||||
|
||||
#endif /* MISC_H_ */
|
||||
353
src/omapl138_eth_driver.h
Normal file
353
src/omapl138_eth_driver.h
Normal file
@@ -0,0 +1,353 @@
|
||||
/**
|
||||
* @file omapl138_eth_driver.h
|
||||
* @brief OMAP-L138 Ethernet MAC controller
|
||||
*
|
||||
* @section License
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* Copyright (C) 2010-2019 Oryx Embedded SARL. All rights reserved.
|
||||
*
|
||||
* This file is part of CycloneTCP Open.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software Foundation,
|
||||
* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*
|
||||
* @author Oryx Embedded SARL (www.oryx-embedded.com)
|
||||
* @version 1.9.6
|
||||
**/
|
||||
|
||||
#ifndef _OMAPL138_ETH_DRIVER_H
|
||||
#define _OMAPL138_ETH_DRIVER_H
|
||||
|
||||
//Dependencies
|
||||
//#include "core/nic.h"
|
||||
#include "soc_OMAPL138.h"
|
||||
|
||||
//Number of TX buffers
|
||||
#ifndef OMAPL138_ETH_TX_BUFFER_COUNT
|
||||
#define OMAPL138_ETH_TX_BUFFER_COUNT 8
|
||||
#elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1)
|
||||
#error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid
|
||||
#endif
|
||||
|
||||
//TX buffer size
|
||||
#ifndef OMAPL138_ETH_TX_BUFFER_SIZE
|
||||
#define OMAPL138_ETH_TX_BUFFER_SIZE 1536
|
||||
#elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536)
|
||||
#error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid
|
||||
#endif
|
||||
|
||||
//Number of RX buffers
|
||||
#ifndef OMAPL138_ETH_RX_BUFFER_COUNT
|
||||
#define OMAPL138_ETH_RX_BUFFER_COUNT 8
|
||||
#elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1)
|
||||
#error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid
|
||||
#endif
|
||||
|
||||
//RX buffer size
|
||||
#ifndef OMAPL138_ETH_RX_BUFFER_SIZE
|
||||
#define OMAPL138_ETH_RX_BUFFER_SIZE 1536
|
||||
#elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536)
|
||||
#error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid
|
||||
#endif
|
||||
|
||||
//Channel number for the TX interrupt
|
||||
#ifndef OMAPL138_ETH_TX_IRQ_CHANNEL
|
||||
#define OMAPL138_ETH_TX_IRQ_CHANNEL 3
|
||||
#elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31)
|
||||
#error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid
|
||||
#endif
|
||||
|
||||
//Channel number for the RX interrupt
|
||||
#ifndef OMAPL138_ETH_RX_IRQ_CHANNEL
|
||||
#define OMAPL138_ETH_RX_IRQ_CHANNEL 3
|
||||
#elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31)
|
||||
#error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid
|
||||
#endif
|
||||
|
||||
//EMAC cores
|
||||
#define EMAC_CORE0 0
|
||||
#define EMAC_CORE1 1
|
||||
#define EMAC_CORE2 2
|
||||
|
||||
//EMAC channels
|
||||
#define EMAC_CH0 0
|
||||
#define EMAC_CH1 1
|
||||
#define EMAC_CH2 2
|
||||
#define EMAC_CH3 3
|
||||
#define EMAC_CH4 4
|
||||
#define EMAC_CH5 5
|
||||
#define EMAC_CH6 6
|
||||
#define EMAC_CH7 7
|
||||
|
||||
//SYSCFG0 registers
|
||||
#define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
|
||||
#define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
|
||||
|
||||
//EMAC registers
|
||||
#define EMAC_TXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID)
|
||||
#define EMAC_TXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL)
|
||||
#define EMAC_TXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN)
|
||||
#define EMAC_RXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID)
|
||||
#define EMAC_RXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL)
|
||||
#define EMAC_RXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN)
|
||||
#define EMAC_TXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW)
|
||||
#define EMAC_TXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED)
|
||||
#define EMAC_TXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET)
|
||||
#define EMAC_TXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR)
|
||||
#define EMAC_MACINVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR)
|
||||
#define EMAC_MACEOIVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR)
|
||||
#define EMAC_RXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW)
|
||||
#define EMAC_RXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED)
|
||||
#define EMAC_RXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET)
|
||||
#define EMAC_RXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR)
|
||||
#define EMAC_MACINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW)
|
||||
#define EMAC_MACINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED)
|
||||
#define EMAC_MACINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET)
|
||||
#define EMAC_MACINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR)
|
||||
#define EMAC_RXMBPENABLE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE)
|
||||
#define EMAC_RXUNICASTSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET)
|
||||
#define EMAC_RXUNICASTCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR)
|
||||
#define EMAC_RXMAXLEN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN)
|
||||
#define EMAC_RXBUFFEROFFSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET)
|
||||
#define EMAC_RXFILTERLOWTHRESH_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH)
|
||||
#define EMAC_RXFLOWTHRESH_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n))
|
||||
#define EMAC_RXFREEBUFFER_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n))
|
||||
#define EMAC_MACCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL)
|
||||
#define EMAC_MACSTATUS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS)
|
||||
#define EMAC_EMCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL)
|
||||
#define EMAC_FIFOCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL)
|
||||
#define EMAC_MACCONFIG_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG)
|
||||
#define EMAC_SOFTRESET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET)
|
||||
#define EMAC_MACSRCADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO)
|
||||
#define EMAC_MACSRCADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI)
|
||||
#define EMAC_MACHASH1_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1)
|
||||
#define EMAC_MACHASH2_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2)
|
||||
#define EMAC_BOFFTEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST)
|
||||
#define EMAC_TPACETEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST)
|
||||
#define EMAC_RXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE)
|
||||
#define EMAC_TXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE)
|
||||
#define EMAC_RXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES)
|
||||
#define EMAC_RXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES)
|
||||
#define EMAC_RXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES)
|
||||
#define EMAC_RXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES)
|
||||
#define EMAC_RXCRCERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS)
|
||||
#define EMAC_RXALIGNCODEERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED)
|
||||
#define EMAC_RXJABBER_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER)
|
||||
#define EMAC_RXUNDERSIZED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED)
|
||||
#define EMAC_RXFRAGMENTS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS)
|
||||
#define EMAC_RXFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED)
|
||||
#define EMAC_RXQOSFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED)
|
||||
#define EMAC_RXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS)
|
||||
#define EMAC_TXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES)
|
||||
#define EMAC_TXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES)
|
||||
#define EMAC_TXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES)
|
||||
#define EMAC_TXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES)
|
||||
#define EMAC_TXDEFERRED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED)
|
||||
#define EMAC_TXCOLLISION_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION)
|
||||
#define EMAC_TXSINGLECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL)
|
||||
#define EMAC_TXMULTICOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL)
|
||||
#define EMAC_TXEXCESSIVECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL)
|
||||
#define EMAC_TXLATECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL)
|
||||
#define EMAC_TXUNDERRUN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN)
|
||||
#define EMAC_TXCARRIERSENSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE)
|
||||
#define EMAC_TXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS)
|
||||
#define EMAC_FRAME64_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64)
|
||||
#define EMAC_FRAME65T127_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127)
|
||||
#define EMAC_FRAME128T255_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255)
|
||||
#define EMAC_FRAME256T511_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511)
|
||||
#define EMAC_FRAME512T1023_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023)
|
||||
#define EMAC_FRAME1024TUP_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP)
|
||||
#define EMAC_NETOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS)
|
||||
#define EMAC_RXSOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS)
|
||||
#define EMAC_RXMOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS)
|
||||
#define EMAC_RXDMAOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS)
|
||||
#define EMAC_MACADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO)
|
||||
#define EMAC_MACADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI)
|
||||
#define EMAC_MACINDEX_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX)
|
||||
#define EMAC_TXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n))
|
||||
#define EMAC_RXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n))
|
||||
#define EMAC_TXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n))
|
||||
#define EMAC_RXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n))
|
||||
|
||||
//EMAC control registers
|
||||
#define EMAC_CTRL_REVID_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID)
|
||||
#define EMAC_CTRL_SOFTRESET_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET)
|
||||
#define EMAC_CTRL_INTCONTRO_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL)
|
||||
#define EMAC_CTRL_C0RXTHRESHEN_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN)
|
||||
#define EMAC_CTRL_CnRXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n))
|
||||
#define EMAC_CTRL_CnTXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n))
|
||||
#define EMAC_CTRL_CnMISCEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n))
|
||||
#define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n))
|
||||
#define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT)
|
||||
#define EMAC_CTRL_C0RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT)
|
||||
#define EMAC_CTRL_C0TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT)
|
||||
#define EMAC_CTRL_C0MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT)
|
||||
#define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
|
||||
#define EMAC_CTRL_C1RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXSTAT)
|
||||
#define EMAC_CTRL_C1TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT)
|
||||
#define EMAC_CTRL_C1MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT)
|
||||
#define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT)
|
||||
#define EMAC_CTRL_C2RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT)
|
||||
#define EMAC_CTRL_C2TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT)
|
||||
#define EMAC_CTRL_C2MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT)
|
||||
#define EMAC_CTRL_C0RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX)
|
||||
#define EMAC_CTRL_C0TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX)
|
||||
#define EMAC_CTRL_C1RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX)
|
||||
#define EMAC_CTRL_C1TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX)
|
||||
#define EMAC_CTRL_C2RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX)
|
||||
#define EMAC_CTRL_C2TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX)
|
||||
|
||||
//MDIO registers
|
||||
#define MDIO_REVID_R HWREG(SOC_MDIO_0_REGS + MDIO_REVID)
|
||||
#define MDIO_CONTROL_R HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL)
|
||||
#define MDIO_ALIVE_R HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE)
|
||||
#define MDIO_LINK_R HWREG(SOC_MDIO_0_REGS + MDIO_LINK)
|
||||
#define MDIO_LINKINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW)
|
||||
#define MDIO_LINKINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED)
|
||||
#define MDIO_USERINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW)
|
||||
#define MDIO_USERINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED)
|
||||
#define MDIO_USERINTMASKSET_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET)
|
||||
#define MDIO_USERINTMASKCLEAR_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR)
|
||||
#define MDIO_USERACCESS0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0)
|
||||
#define MDIO_USERPHYSEL0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0)
|
||||
#define MDIO_USERACCESS1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1)
|
||||
#define MDIO_USERPHYSEL1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1)
|
||||
|
||||
//MACEOIVECTOR register
|
||||
#define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000
|
||||
#define EMAC_MACEOIVECTOR_C0RX 0x00000001
|
||||
#define EMAC_MACEOIVECTOR_C0TX 0x00000002
|
||||
#define EMAC_MACEOIVECTOR_C0MISC 0x00000003
|
||||
#define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004
|
||||
#define EMAC_MACEOIVECTOR_C1RX 0x00000005
|
||||
#define EMAC_MACEOIVECTOR_C1TX 0x00000006
|
||||
#define EMAC_MACEOIVECTOR_C1MISC 0x00000007
|
||||
#define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008
|
||||
#define EMAC_MACEOIVECTOR_C2RX 0x00000009
|
||||
#define EMAC_MACEOIVECTOR_C2TX 0x0000000A
|
||||
#define EMAC_MACEOIVECTOR_C2MISC 0x0000000B
|
||||
|
||||
//TX buffer descriptor flags
|
||||
#define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
|
||||
#define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
|
||||
#define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
|
||||
#define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
|
||||
#define EMAC_TX_WORD3_SOP 0x80000000
|
||||
#define EMAC_TX_WORD3_EOP 0x40000000
|
||||
#define EMAC_TX_WORD3_OWNER 0x20000000
|
||||
#define EMAC_TX_WORD3_EOQ 0x10000000
|
||||
#define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000
|
||||
#define EMAC_TX_WORD3_PASSCRC 0x04000000
|
||||
#define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF
|
||||
|
||||
//RX buffer descriptor flags
|
||||
#define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
|
||||
#define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
|
||||
#define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000
|
||||
#define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF
|
||||
#define EMAC_RX_WORD3_SOP 0x80000000
|
||||
#define EMAC_RX_WORD3_EOP 0x40000000
|
||||
#define EMAC_RX_WORD3_OWNER 0x20000000
|
||||
#define EMAC_RX_WORD3_EOQ 0x10000000
|
||||
#define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000
|
||||
#define EMAC_RX_WORD3_PASSCRC 0x04000000
|
||||
#define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000
|
||||
#define EMAC_RX_WORD3_JABBER 0x02000000
|
||||
#define EMAC_RX_WORD3_OVERSIZE 0x01000000
|
||||
#define EMAC_RX_WORD3_FRAGMENT 0x00800000
|
||||
#define EMAC_RX_WORD3_UNDERSIZED 0x00400000
|
||||
#define EMAC_RX_WORD3_CONTROL 0x00200000
|
||||
#define EMAC_RX_WORD3_OVERRUN 0x00100000
|
||||
#define EMAC_RX_WORD3_CODEERROR 0x00080000
|
||||
#define EMAC_RX_WORD3_ALIGNERROR 0x00040000
|
||||
#define EMAC_RX_WORD3_CRCERROR 0x00020000
|
||||
#define EMAC_RX_WORD3_NOMATCH 0x00010000
|
||||
#define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF
|
||||
|
||||
//C++ guard
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief TX buffer descriptor
|
||||
**/
|
||||
|
||||
typedef struct _Omapl138TxBufferDesc
|
||||
{
|
||||
uint32_t word0;
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
uint32_t word3;
|
||||
struct _Omapl138TxBufferDesc *next;
|
||||
struct _Omapl138TxBufferDesc *prev;
|
||||
} Omapl138TxBufferDesc;
|
||||
|
||||
|
||||
/**
|
||||
* @brief RX buffer descriptor
|
||||
**/
|
||||
|
||||
typedef struct _Omapl138RxBufferDesc
|
||||
{
|
||||
uint32_t word0;
|
||||
uint32_t word1;
|
||||
uint32_t word2;
|
||||
uint32_t word3;
|
||||
struct _Omapl138RxBufferDesc *next;
|
||||
struct _Omapl138RxBufferDesc *prev;
|
||||
} Omapl138RxBufferDesc;
|
||||
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
|
||||
//AM335x Ethernet MAC driver
|
||||
//extern const NicDriver omapl138EthDriver;
|
||||
|
||||
//AM335x Ethernet MAC related functions
|
||||
/*error_t omapl138EthInit(NetInterface *interface);
|
||||
void omapl138EthInitGpio(NetInterface *interface);
|
||||
void omapl138EthInitBufferDesc(NetInterface *interface);
|
||||
|
||||
void omapl138EthTick(NetInterface *interface);
|
||||
|
||||
void omapl138EthEnableIrq(NetInterface *interface);
|
||||
void omapl138EthDisableIrq(NetInterface *interface);
|
||||
void omapl138EthTxIrqHandler(void);
|
||||
void omapl138EthRxIrqHandler(void);
|
||||
void omapl138EthEventHandler(NetInterface *interface);
|
||||
|
||||
error_t omapl138EthSendPacket(NetInterface *interface,
|
||||
const NetBuffer *buffer, size_t offset);
|
||||
|
||||
error_t omapl138EthReceivePacket(NetInterface *interface);
|
||||
|
||||
error_t omapl138EthUpdateMacAddrFilter(NetInterface *interface);
|
||||
error_t omapl138EthUpdateMacConfig(NetInterface *interface);
|
||||
*/
|
||||
void omapl138EthWritePhyReg(uint8_t opcode, uint8_t phyAddr,
|
||||
uint8_t regAddr, uint16_t data);
|
||||
|
||||
uint16_t omapl138EthReadPhyReg(uint8_t opcode, uint8_t phyAddr,
|
||||
uint8_t regAddr);
|
||||
|
||||
//C++ guard
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
114
src/psc.c
Normal file
114
src/psc.c
Normal file
@@ -0,0 +1,114 @@
|
||||
/**
|
||||
* \file psc.c
|
||||
*
|
||||
* \brief This file contains the device abstraction layer APIs for the
|
||||
* PSC module. There are APIs here to enable power domain,
|
||||
* transitions for a particular module
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
/*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* HW Macros */
|
||||
#include "hw_types.h"
|
||||
|
||||
/* DSP System Defines */
|
||||
#include "hw_psc_OMAPL138.h"
|
||||
|
||||
/**************************************************************************
|
||||
API FUNCTION DEFINITIONS
|
||||
***************************************************************************/
|
||||
|
||||
/**
|
||||
*
|
||||
* \brief This function sets the requested module in the required state
|
||||
*
|
||||
* \param baseAdd Memory address of the PSC instance used.
|
||||
* \param moduleId The module number of the module to be commanded.
|
||||
* \param powerDomain The power domain of the module to be commanded.
|
||||
* \param flags This contains the flags that is a logical OR of
|
||||
* the commands that can be given to a module.
|
||||
*
|
||||
* \return 0 in case of successful transition, -1 otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
|
||||
unsigned int powerDomain, unsigned int flags)
|
||||
{
|
||||
volatile unsigned int timeout = 0xFFFFFF;
|
||||
int retVal = 0;
|
||||
unsigned int status = 0;
|
||||
|
||||
HWREG(baseAdd + PSC_MDCTL(moduleId)) = (flags & PSC_MDCTL_NEXT);
|
||||
|
||||
if (powerDomain == 0)
|
||||
{
|
||||
HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO0;
|
||||
}
|
||||
else
|
||||
{
|
||||
HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO1;
|
||||
}
|
||||
|
||||
if (powerDomain == 0)
|
||||
{
|
||||
do {
|
||||
status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT0;
|
||||
} while (status && timeout--);
|
||||
}
|
||||
else
|
||||
{
|
||||
do {
|
||||
status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
|
||||
} while (status && timeout--);
|
||||
}
|
||||
|
||||
if (timeout != 0)
|
||||
{
|
||||
timeout = 0xFFFFFF;
|
||||
status = flags & PSC_MDCTL_NEXT;
|
||||
do {
|
||||
timeout--;
|
||||
} while(timeout &&
|
||||
(HWREG(baseAdd + PSC_MDSTAT(moduleId)) & PSC_MDSTAT_STATE) != status);
|
||||
}
|
||||
|
||||
if (timeout == 0)
|
||||
{
|
||||
retVal = -1;
|
||||
}
|
||||
|
||||
return retVal;
|
||||
}
|
||||
69
src/psc.h
Normal file
69
src/psc.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/**
|
||||
* \file psc.h
|
||||
*
|
||||
* \brief This file contains the function prototypes for the device abstraction
|
||||
* layer for PSC. It also contains some related macro definitions and some
|
||||
* files to be included.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
/*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PSC_H
|
||||
#define _PSC_H
|
||||
|
||||
#if defined c6748
|
||||
#include "hw_psc_C6748.h"
|
||||
#elif defined omapl138
|
||||
#include "hw_psc_OMAPL138.h"
|
||||
#else
|
||||
#include "hw_psc_AM1808.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
|
||||
unsigned int powerDomain, unsigned int flags);
|
||||
|
||||
extern void USBModuleClkEnable(unsigned int ulIndex, unsigned int ulBase);
|
||||
extern void USBModuleClkDisable(unsigned int ulIndex, unsigned int ulBase);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
595
src/soc_OMAPL138.h
Normal file
595
src/soc_OMAPL138.h
Normal file
@@ -0,0 +1,595 @@
|
||||
/**
|
||||
* \file soc_OMAPL138.h
|
||||
*
|
||||
* \brief This file contains the peripheral information for OMAPL138 SOC
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
/*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SOC_OMAPL138_H_
|
||||
#define _SOC_OMAPL138_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
** PERIPHERAL INSTANCE COUNT
|
||||
******************************************************************************/
|
||||
|
||||
/** \brief Number of UPP instances */
|
||||
#define SOC_UPP_PER_CNT 1
|
||||
|
||||
/** \brief Number of UHPI instances */
|
||||
#define SOC_HPI_PER_CNT 1
|
||||
|
||||
/** \brief Number of McASP instances */
|
||||
#define SOC_MCASP_PER_CNT 1
|
||||
|
||||
/** \brief Number of TIMER instances */
|
||||
#define SOC_TMR_PER_CNT 4
|
||||
|
||||
/** \brief Number of PSC instances */
|
||||
#define SOC_PSC_PER_CNT 2
|
||||
|
||||
/** \brief Number of UART instances */
|
||||
#define SOC_UART_PER_CNT 3
|
||||
|
||||
/** \brief Number of SPI instances */
|
||||
#define SOC_SPI_PER_CNT 2
|
||||
|
||||
/** \brief Number of I2C instances */
|
||||
#define SOC_I2C_PER_CNT 2
|
||||
|
||||
/** \brief Number of PLL instances */
|
||||
#define SOC_PLLC_PER_CNT 2
|
||||
|
||||
/** \brief Number of MMCSD instances */
|
||||
#define SOC_MMCSD_PER_CNT 2
|
||||
|
||||
/** \brief Number of LCDC instances */
|
||||
#define SOC_LCDC_PER_CNT 1
|
||||
|
||||
/** \brief Number of Mcbsp instances */
|
||||
#define SOC_MCBSP_PER_CNT 2
|
||||
|
||||
/** \brief Number of EDMA3 CC instances */
|
||||
#define SOC_EDMA3CC_CNT 2
|
||||
|
||||
/** \brief Number of EDMA3 TC instances */
|
||||
#define SOC_EDMA3TC_CNT 3
|
||||
|
||||
/** \brief Number of EMIFA instances */
|
||||
#define SOC_EMIFA_PER_CNT 1
|
||||
|
||||
/** \brief Number of EMIFB instances */
|
||||
#define SOC_EMIFB_PER_CNT 1
|
||||
|
||||
/** \brief Number of EMAC instances */
|
||||
#define SOC_EMAC_PER_CNT 1
|
||||
|
||||
/** \brief Number of MDIO instances */
|
||||
#define SOC_MDIO_PER_CNT 1
|
||||
|
||||
/** \brief Number of EHRPWM instances */
|
||||
#define SOC_EHRPWM_PER_CNT 2
|
||||
|
||||
/** \brief Number of ECAP instances */
|
||||
#define SOC_ECAP_PER_CNT 3
|
||||
|
||||
/** \brief Number of CPGMAC instances */
|
||||
#define SOC_CPGMACSSR_PER_CNT 1
|
||||
|
||||
/** \brief Number of CPPI instances */
|
||||
#define SOC_CPPI_PER_CNT 1
|
||||
|
||||
/** \brief Number of USB instances */
|
||||
#define SOC_USB_PER_CNT 2
|
||||
|
||||
/** \brief Number of VPIF instances */
|
||||
#define SOC_VPIF_PER_CNT 1
|
||||
|
||||
/** \brief Number of INTC instances */
|
||||
#define SOC_INTC_PER_CNT 1
|
||||
|
||||
/** \brief Number of AINTC instances */
|
||||
#define SOC_AINTC_PER_CNT 1
|
||||
|
||||
/** \brief Number of SATA instances */
|
||||
#define SOC_SATA_PER_CNT 1
|
||||
|
||||
/** \brief Number of RTC instances */
|
||||
#define SOC_RTC_PER_CNT 1
|
||||
|
||||
/** \brief Number of GPIO instances */
|
||||
#define SOC_GPIO_PER_CNT 1
|
||||
|
||||
/** \brief Number of SYSCFG instances */
|
||||
#define SOC_SYSCFG_PER_CNT 2
|
||||
/******************************************************************************
|
||||
** PERIPHERAL INSTANCE DEFINITIONS
|
||||
******************************************************************************/
|
||||
|
||||
/** \brief Peripheral Instances of UHPI instances */
|
||||
#define SOC_HPI (0)
|
||||
|
||||
/** \brief Peripheral Instances of McASP instances */
|
||||
#define SOC_MCASP_0 (0)
|
||||
|
||||
/** \brief Peripheral Instance of EDMA CC instances */
|
||||
#define SOC_EDMA3CC_0 (0)
|
||||
#define SOC_EDMA3CC_1 (1)
|
||||
|
||||
/** \brief Peripheral Instance of EDMA TC instances */
|
||||
#define SOC_EDMA3TC_0 (0)
|
||||
#define SOC_EDMA3TC_1 (1)
|
||||
|
||||
/** \brief Peripheral Instance of Timer 64 instances */
|
||||
#define SOC_TMR_0 (0)
|
||||
#define SOC_TMR_1 (1)
|
||||
#define SOC_TMR_2 (2)
|
||||
#define SOC_TMR_3 (3)
|
||||
|
||||
/** \brief Peripheral Instances of PSC instances */
|
||||
#define SOC_PSC_0 (0)
|
||||
#define SOC_PSC_1 (1)
|
||||
|
||||
/** \brief Peripheral Instances of UART instances */
|
||||
#define SOC_UART_0 (0)
|
||||
#define SOC_UART_1 (1)
|
||||
#define SOC_UART_2 (2)
|
||||
|
||||
/** \brief Peripheral Instances of SPI instances */
|
||||
#define SOC_SPI_0 (0)
|
||||
#define SOC_SPI_1 (1)
|
||||
|
||||
/** \brief Peripheral Instances of I2C instances */
|
||||
#define SOC_I2C_0 (0)
|
||||
#define SOC_I2C_1 (1)
|
||||
|
||||
/** \brief Peripheral Instances of MMCSD instances */
|
||||
#define SOC_MMCSD_0 (0)
|
||||
#define SOC_MMCSD_1 (1)
|
||||
|
||||
/** \brief Peripheral Instances of LCDC instances */
|
||||
#define SOC_LCDC (0)
|
||||
|
||||
/** \brief Instance number of PLL controller */
|
||||
#define SOC_PLLC_0 (0)
|
||||
#define SOC_PLLC_1 (1)
|
||||
|
||||
/** \brief Peripheral Instance of EMIFA instances */
|
||||
#define SOC_EMIFA (0)
|
||||
|
||||
/** \brief Peripheral Instance of EMAC instances */
|
||||
#define SOC_EMAC (0)
|
||||
|
||||
/** \brief Peripheral Instance of MDIO instances */
|
||||
#define SOC_MDIO (0)
|
||||
|
||||
/** \brief Peripheral Instance of EHRPWM instances */
|
||||
#define SOC_EHRPWM_0 (0)
|
||||
#define SOC_EHRPWM_1 (1)
|
||||
|
||||
/** \brief Peripheral Instance of ECAP instances */
|
||||
#define SOC_ECAP_0 (0)
|
||||
#define SOC_ECAP_1 (1)
|
||||
#define SOC_ECAP_2 (2)
|
||||
|
||||
/** \brief Peripheral Instance of USB instances */
|
||||
#define SOC_USB_0 (0)
|
||||
#define SOC_USB_1 (1)
|
||||
|
||||
/** \brief Peripheral Instance of PRU CORE instances */
|
||||
#define SOC_PRUCORE_0 (0)
|
||||
#define SOC_PRUCORE_1 (1)
|
||||
|
||||
/** \brief Peripheral Instance of PRUINTC instances */
|
||||
#define SOC_PRUINTC (0)
|
||||
|
||||
/** \brief Peripheral Instances of VPIF instances */
|
||||
#define SOC_VPIF (0)
|
||||
|
||||
/** \brief Peripheral Instance of INTC instances */
|
||||
#define SOC_INTC (0)
|
||||
|
||||
/** \brief Peripheral Instance of AINTC instances */
|
||||
#define SOC_AINTC (0)
|
||||
|
||||
/** \brief Peripheral Instance of RTC instances */
|
||||
#define SOC_RTC (0)
|
||||
|
||||
/** \brief Peripheral Instance of GPIO instances */
|
||||
#define SOC_GPIO (0)
|
||||
/** \brief GPIO pin and bank information */
|
||||
#define SOC_GPIO_NUM_PINS (144)
|
||||
#define SOC_GPIO_NUM_BANKS ((SOC_GPIO_NUM_PINS + 15)/16)
|
||||
|
||||
/** \brief Peripheral Instance of ECTL instances */
|
||||
#define SOC_ECTL (0)
|
||||
|
||||
/** \brief Peripheral Instance of SYSCFG instances */
|
||||
#define SOC_SYSCFG (2)
|
||||
|
||||
/******************************************************************************
|
||||
** PERIPHERAL BASE ADDRESS
|
||||
******************************************************************************/
|
||||
|
||||
/** \brief Base address of INTC memory mapped registers */
|
||||
#define SOC_INTC_0_REGS (0x01800000)
|
||||
|
||||
/** \brief Base address of PDC memory mapped registers */
|
||||
#define SOC_PWRDWN_PDC_REGS (0x01810000)
|
||||
|
||||
/** \brief Base address of SYS - Security ID register */
|
||||
#define SOC_SYS_0_SECURITY_ID_REGS (0x01811000)
|
||||
|
||||
/** \brief Base address of SYS - Revision ID register */
|
||||
#define SOC_SYS_0_REV_ID_REGS (0x01812000)
|
||||
|
||||
/** \brief IDMA Module memory mapped address */
|
||||
#define SOC_IDMA_0_REGS (0x01820000)
|
||||
|
||||
/** \brief EMC Module memory mapped address */
|
||||
#define SOC_EMC_0_REGS (0x01820000)
|
||||
|
||||
/** \brief Cache Module memory mapped address */
|
||||
#define SOC_CACHE_0_REGS (0x01840000)
|
||||
|
||||
/** \brief Base address of Channel controller memory mapped registers */
|
||||
#define SOC_EDMA30CC_0_REGS (0x01C00000)
|
||||
|
||||
/** \brief Base address of Transfer controller memory mapped registers */
|
||||
#define SOC_EDMA30TC_0_REGS (0x01C08000)
|
||||
#define SOC_EDMA30TC_1_REGS (0x01C08400)
|
||||
|
||||
/** \brief Base address of PSC memory mapped registers */
|
||||
#define SOC_PSC_0_REGS (0x01C10000)
|
||||
|
||||
/** \brief PLL controller instance o module address */
|
||||
#define SOC_PLLC_0_REGS (0x01C11000)
|
||||
|
||||
/** \brief Base address of DEV memory mapped registers */
|
||||
#define SOC_SYSCFG_0_REGS (0x01C14000)
|
||||
|
||||
/** \brief Base address of TIMER memory mapped registers */
|
||||
#define SOC_TMR_0_REGS (0x01C20000)
|
||||
#define SOC_TMR_1_REGS (0x01C21000)
|
||||
|
||||
/** \brief Base address of I2C memory mapped registers */
|
||||
#define SOC_I2C_0_REGS (0x01C22000)
|
||||
|
||||
/** \brief Base address of RTC memory */
|
||||
#define SOC_RTC_0_REGS (0x01C23000)
|
||||
|
||||
/** \brief Base address of MMCSD memory mapped registers */
|
||||
#define SOC_MMCSD_0_REGS (0x01C40000)
|
||||
|
||||
/** \brief Base address of SPI memory mapped registers */
|
||||
#define SOC_SPI_0_REGS (0x01C41000)
|
||||
|
||||
/** \brief Base address of UART memory mapped registers */
|
||||
#define SOC_UART_0_REGS (0x01C42000)
|
||||
|
||||
/** \brief Base address of McASP memory mapped registers */
|
||||
#define SOC_MCASP_0_CTRL_REGS (0x01D00000)
|
||||
#define SOC_MCASP_0_FIFO_REGS (0x01D01000)
|
||||
#define SOC_MCASP_0_DATA_REGS (0x01D02000)
|
||||
|
||||
/** \brief Base address of UART memory mapped registers */
|
||||
#define SOC_UART_1_REGS (0x01D0C000)
|
||||
#define SOC_UART_2_REGS (0x01D0D000)
|
||||
|
||||
/** \brief Base address of McBSP memory mapped registers */
|
||||
#define SOC_MCBSP_0_CTRL_REGS (0x01D10000)
|
||||
#define SOC_MCBSP_0_FIFO_REGS (0x01D10800)
|
||||
#define SOC_MCBSP_0_DATA_REGS (0x01F10000)
|
||||
|
||||
/** \brief Base address of McASP memory mapped registers */
|
||||
#define SOC_MCBSP_1_CTRL_REGS (0x01D11000)
|
||||
#define SOC_MCBSP_1_FIFO_REGS (0x01D11800)
|
||||
#define SOC_MCBSP_1_DATA_REGS (0x01F11000)
|
||||
|
||||
#define SOC_MPU_0_REGS (0x01E14000)
|
||||
#define SOC_MPU_1_REGS (0x01E15000)
|
||||
|
||||
/** \brief Base address of USB memory */
|
||||
#define SOC_USB_0_REGS (0x01E00000)
|
||||
#define SOC_USB_1_REGS (0x01E25000)
|
||||
|
||||
/** \brief Base address of HPI memory mapped registers */
|
||||
#define SOC_HPI_0_REGS (0x01E10000)
|
||||
|
||||
/** \brief Base address of LCDC memory mapped registers */
|
||||
#define SOC_LCDC_0_REGS (0x01E13000)
|
||||
|
||||
/** \brief Base address of UPP memory mapped registers */
|
||||
#define SOC_UPP_0_REGS (0x01E16000)
|
||||
|
||||
/** \brief Base address of VPIF memory mapped registers */
|
||||
#define SOC_VPIF_0_REGS (0x01E17000)
|
||||
|
||||
/** \brief Base address of SATA memory mapped registers */
|
||||
#define SOC_SATA_0_REGS (0x01E18000)
|
||||
|
||||
/** \brief PLL controller instance 1 module address */
|
||||
#define SOC_PLLC_1_REGS (0X01E1A000)
|
||||
|
||||
/** \brief Base address of MMCSD memory mapped registers */
|
||||
#define SOC_MMCSD_1_REGS (0x01E1B000)
|
||||
|
||||
/** \brief Base address of EMAC memory */
|
||||
#define SOC_EMAC_DSC_CTRL_MOD_RAM (0x01E20000)
|
||||
#define SOC_EMAC_DSC_CTRL_MOD_REG (0x01E22000)
|
||||
#define SOC_EMAC_DSC_CONTROL_REG (0x01E23000)
|
||||
#define SOC_MDIO_0_REGS (0x01E24000)
|
||||
|
||||
/** \brief Base address of PRU Core Regsiters */
|
||||
#define SOC_PRUCORE_0_REGS (0x01C37000)
|
||||
#define SOC_PRUCORE_1_REGS (0x01C37800)
|
||||
|
||||
/** \brief Base address of PRU Interrupt Controller Registers */
|
||||
#define SOC_PRUINTC_0_REGS (0x01C34000)
|
||||
|
||||
/** \brief Base address of MUSB memmory mapped Registers */
|
||||
#define SOC_USB_0_BASE (0x01E00400)
|
||||
|
||||
/** \brief Base address of OTG memmory mapped Registers */
|
||||
#define SOC_USB_0_OTG_BASE (0x01E00000)
|
||||
|
||||
/** \brief USB 0 Phy regsister( CFGCHIP2 register) address */
|
||||
#define SOC_USB_0_PHY_REGS (0x01C14184)
|
||||
|
||||
/** \brief Base address of GPIO memory mapped registers */
|
||||
#define SOC_GPIO_0_REGS (0x01E26000)
|
||||
|
||||
/** \brief Base address of PSC memory mapped registers */
|
||||
#define SOC_PSC_1_REGS (0x01E27000)
|
||||
|
||||
/** \brief Base address of I2C memory mapped registers */
|
||||
#define SOC_I2C_1_REGS (0x01E28000)
|
||||
|
||||
/** \brief Base address of syscfg registers */
|
||||
#define SOC_SYSCFG_1_REGS (0x01E2C000)
|
||||
|
||||
/** \brief Base address of Channel controller memory mapped registers */
|
||||
#define SOC_EDMA31CC_0_REGS (0x01E30000)
|
||||
|
||||
/** \brief Base address of Transfer controller memory mapped registers */
|
||||
#define SOC_EDMA31TC_0_REGS (0x01E38000)
|
||||
|
||||
/** \brief Base address of EPWM memory mapped registers */
|
||||
#define SOC_EHRPWM_0_REGS (0x01F00000)
|
||||
#define SOC_EHRPWM_1_REGS (0x01F02000)
|
||||
|
||||
/** \brief Base address of EPWM memory mapped registers */
|
||||
#define SOC_HRPWM_0_REGS (0x01F01000)
|
||||
#define SOC_HRPWM_1_REGS (0x01F03000)
|
||||
|
||||
/** \brief Base address of ECAP memory mapped registers */
|
||||
#define SOC_ECAP_0_REGS (0x01F06000)
|
||||
#define SOC_ECAP_1_REGS (0x01F07000)
|
||||
#define SOC_ECAP_2_REGS (0x01F08000)
|
||||
|
||||
/** \brief Base address of TIMER memory mapped registers */
|
||||
#define SOC_TMR_2_REGS (0x01F0C000)
|
||||
#define SOC_TMR_3_REGS (0x01F0D000)
|
||||
|
||||
/** \brief Base address of SPI memory mapped registers */
|
||||
#define SOC_SPI_1_REGS (0x01F0E000)
|
||||
|
||||
/** \brief Base address of EMIFA memory mapped registers */
|
||||
#define SOC_EMIFA_0_REGS (0x68000000)
|
||||
|
||||
/** \brief Base address of EMIFA_CS0 memory */
|
||||
#define SOC_EMIFA_CS0_ADDR (0x40000000)
|
||||
|
||||
/** \brief Base address of EMIFA_CS2 memory */
|
||||
#define SOC_EMIFA_CS2_ADDR (0x60000000)
|
||||
|
||||
/** \brief Base address of EMIFA_CS3 memory */
|
||||
#define SOC_EMIFA_CS3_ADDR (0x62000000)
|
||||
|
||||
/** \brief Base address of EMIFA_CS4 memory */
|
||||
#define SOC_EMIFA_CS4_ADDR (0x64000000)
|
||||
|
||||
/** \brief Base address of EMIFA_CS5 memory */
|
||||
#define SOC_EMIFA_CS5_ADDR (0x66000000)
|
||||
|
||||
/** \brief Base address of DDR memory mapped registers */
|
||||
#define SOC_DDR2_0_CTRL_REGS (0xB0000000)
|
||||
#define SOC_DDR2_0_DATA_REGS (0xC0000000)
|
||||
|
||||
/** \brief Base address of AINTC memory mapped registers */
|
||||
#define SOC_AINTC_0_REGS (0xFFFEE000)
|
||||
|
||||
/** \brief Base address of UMC Memory protection registers */
|
||||
#define SOC_MEMPROT_L2_REGS (0x00800000)
|
||||
|
||||
/** \brief Base address of PMC memory Protection registers */
|
||||
#define SOC_MEMPROT_L1P_REGS (0x00E00000)
|
||||
|
||||
/** \brief Base address of DMC memory protection registers */
|
||||
#define SOC_MEMPROT_L1D_REGS (0x00F00000)
|
||||
|
||||
/******************************************************************************
|
||||
** EDMA RELATED DEFINITIONS
|
||||
******************************************************************************/
|
||||
|
||||
/* Parameterizable Configuration: These are fed directly from the RTL
|
||||
* parameters for the given SOC */
|
||||
|
||||
#define SOC_EDMA3_NUM_DMACH 32
|
||||
#define SOC_EDMA3_NUM_QDMACH 8
|
||||
#define SOC_EDMA3_NUM_PARAMSETS 128
|
||||
#define SOC_EDMA3_NUM_EVQUE 2
|
||||
#define SOC_EDMA3_CHMAPEXIST 0
|
||||
#define SOC_EDMA3_NUM_REGIONS 4
|
||||
#define SOC_EDMA3_MEMPROTECT 0
|
||||
|
||||
/******************************************************************************
|
||||
** CHANNEL INSTANCE COUNT
|
||||
******************************************************************************/
|
||||
#define SOC_EDMA3_CHA_CNT (SOC_EDMA3_NUM_DMACH + \
|
||||
SOC_EDMA3_NUM_QDMACH)
|
||||
|
||||
|
||||
/* QDMA channels */
|
||||
#define SOC_EDMA3_QCHA_BASE SOC_EDMA3_NUM_DMACH /* QDMA Channel Base */
|
||||
#define SOC_EDMA3_QCHA_0 (SOC_EDMA3_QCHA_BASE + 0) /* QDMA Channel 0 */
|
||||
#define SOC_EDMA3_QCHA_1 (SOC_EDMA3_QCHA_BASE + 1) /* QDMA Channel 1 */
|
||||
#define SOC_EDMA3_QCHA_2 (SOC_EDMA3_QCHA_BASE + 2) /* QDMA Channel 2 */
|
||||
#define SOC_EDMA3_QCHA_3 (SOC_EDMA3_QCHA_BASE + 3) /* QDMA Channel 3 */
|
||||
#define SOC_EDMA3_QCHA_4 (SOC_EDMA3_QCHA_BASE + 4) /* QDMA Channel 4 */
|
||||
#define SOC_EDMA3_QCHA_5 (SOC_EDMA3_QCHA_BASE + 5) /* QDMA Channel 5 */
|
||||
#define SOC_EDMA3_QCHA_6 (SOC_EDMA3_QCHA_BASE + 6) /* QDMA Channel 6 */
|
||||
#define SOC_EDMA3_QCHA_7 (SOC_EDMA3_QCHA_BASE + 7) /* QDMA Channel 7 */
|
||||
|
||||
|
||||
/* Enumerations for EDMA Controlleres */
|
||||
#define SOC_EDMACC_ANY -1 /* Any instance of EDMACC module*/
|
||||
#define SOC_EDMACC_0 0 /* EDMACC Instance 0 */
|
||||
|
||||
|
||||
/* Enumerations for EDMA Event Queues */
|
||||
#define SOC_EDMA3_QUE_0 0 /* Queue 0 */
|
||||
#define SOC_EDMA3_QUE_1 1 /* Queue 1 */
|
||||
|
||||
/* Enumerations for EDMA Transfer Controllers
|
||||
*
|
||||
* There are 2 Transfer Controllers. Typically a one to one mapping exists
|
||||
* between Event Queues and Transfer Controllers. */
|
||||
#define SOC_EDMATC_ANY -1 /* Any instance of EDMATC */
|
||||
#define SOC_EDMATC_0 0 /* EDMATC Instance 0 */
|
||||
#define SOC_EDMATC_1 1 /* EDMATC Instance 1 */
|
||||
|
||||
|
||||
#define SOC_EDMA3_REGION_GLOBAL (-1)
|
||||
#define SOC_EDMA3_REGION_0 0
|
||||
#define SOC_EDMA3_REGION_1 1
|
||||
#define SOC_EDMA3_REGION_2 2
|
||||
#define SOC_EDMA3_REGION_3 3
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
** DAT RELATED DEFINITIONS
|
||||
******************************************************************************/
|
||||
|
||||
/* Parameterizable Configuration:- These are fed directly from the RTL
|
||||
* parameters for the given SOC */
|
||||
|
||||
/******************************************************************************
|
||||
** CHANNEL INSTANCE COUNT
|
||||
******************************************************************************/
|
||||
/** \brief Number of Generic Channel instances */
|
||||
|
||||
|
||||
/** \brief Enumerations for EDMA channels
|
||||
*
|
||||
* There are 8 QDMA channels -
|
||||
*/
|
||||
|
||||
#define SOC_DAT_QCHA_0 0 /**< QDMA Channel 0 */
|
||||
#define SOC_DAT_QCHA_1 1 /**< QDMA Channel 1 */
|
||||
#define SOC_DAT_QCHA_2 2 /**< QDMA Channel 2 */
|
||||
#define SOC_DAT_QCHA_3 3 /**< QDMA Channel 3 */
|
||||
#define SOC_DAT_QCHA_4 4 /**< QDMA Channel 4 */
|
||||
#define SOC_DAT_QCHA_5 5 /**< QDMA Channel 5 */
|
||||
#define SOC_DAT_QCHA_6 6 /**< QDMA Channel 6 */
|
||||
#define SOC_DAT_QCHA_7 7 /**< QDMA Channel 7 */
|
||||
|
||||
/** \brief Enumerations for EDMA Event Queues
|
||||
*
|
||||
* There are two Event Queues. Q0 is the highest priority and Q1 is the least
|
||||
* priority
|
||||
*
|
||||
*/
|
||||
#define SOC_DAT_PRI_DEFAULT 0 /* Queue 0 is default */
|
||||
#define SOC_DAT_PRI_0 0 /* Queue 0 */
|
||||
#define SOC_DAT_PRI_1 1 /* Queue 1 */
|
||||
|
||||
/** \brief Enumeration for EDMA Regions
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#define SOC_DAT_REGION_GLOBAL (-1) /* Global Region */
|
||||
#define SOC_DAT_REGION_0 0 /* EDMA Region 0 */
|
||||
#define SOC_DAT_REGION_1 1 /* EDMA Region 1 */
|
||||
#define SOC_DAT_REGION_2 2 /* EDMA Region 2 */
|
||||
#define SOC_DAT_REGION_3 3 /* EDMA Region 3 */
|
||||
|
||||
/** \brief Enumeration for peripheral frequencies
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#define SOC_SYSCLK_1_FREQ (300000000)
|
||||
#define SOC_SYSCLK_2_FREQ (SOC_SYSCLK_1_FREQ/2)
|
||||
#define SOC_SYSCLK_3_FREQ (SOC_SYSCLK_1_FREQ/3)
|
||||
#define SOC_SYSCLK_4_FREQ (SOC_SYSCLK_1_FREQ/4)
|
||||
|
||||
#define SOC_ASYNC_2_FREQ (24000000)
|
||||
|
||||
/** I2C */
|
||||
#define SOC_I2C_0_MODULE_FREQ (SOC_ASYNC_2_FREQ)
|
||||
#define SOC_I2C_1_MODULE_FREQ (SOC_SYSCLK_4_FREQ)
|
||||
|
||||
/** MCBSP */
|
||||
#define SOC_MCBSP_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
#define SOC_MCBSP_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
|
||||
/** LCDC */
|
||||
#define SOC_LCDC_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
|
||||
/** SPI */
|
||||
#define SOC_SPI_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
#define SOC_SPI_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
|
||||
/** UART */
|
||||
#define SOC_UART_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
#define SOC_UART_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
#define SOC_UART_2_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
|
||||
/** EHRPWM */
|
||||
#define SOC_EHRPWM_0_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
#define SOC_EHRPWM_1_MODULE_FREQ (SOC_SYSCLK_2_FREQ)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_OMAPL138_H_ */
|
||||
198
src/spi.c
Normal file
198
src/spi.c
Normal file
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
* spi.c
|
||||
*
|
||||
* Created on: 19-12-2016
|
||||
* Author: K
|
||||
*/
|
||||
|
||||
#include <ti/sysbios/hal/Timer.h>
|
||||
#include <ti/sysbios/BIOS.h>
|
||||
#include <ti/sysbios/knl/Task.h>
|
||||
#include <ti/sysbios/knl/Clock.h>
|
||||
#include <ti/sysbios/knl/Semaphore.h>
|
||||
|
||||
#include <ti/ipc/Ipc.h>
|
||||
#include <ti/ipc/MultiProc.h>
|
||||
#include <ti/ipc/MessageQ.h>
|
||||
#include <ti/ipc/Notify.h>
|
||||
|
||||
#include "misc.h"
|
||||
#include "spi.h"
|
||||
#include "tdefs.h"
|
||||
#include "logic_elements/virt_in_drv.h"
|
||||
#include "logic_elements/leds_drv.h"
|
||||
#include "logic_elements/pkw.h"
|
||||
#include "logic_elements/cnt.h"
|
||||
#include "logic_elements/s_demux.h"
|
||||
#include "logic_elements/events_reg.h"
|
||||
#include "comm.h"
|
||||
|
||||
u8 spi_fram_restored = 0;
|
||||
|
||||
void spi_init()
|
||||
{
|
||||
u32 psc;
|
||||
|
||||
PINMUX3=(PINMUX3 & ~(PINMUX3_3_0|PINMUX3_15_12|PINMUX3_11_8|PINMUX3_31_28)) | (1<<0) | (1<<12) | (1<<8) | (4<<28); // spi0 clk, mosi, miso, gp8_1 cs
|
||||
DIR8&=~(1<<1); // GP8_1 as output
|
||||
|
||||
// enable psc
|
||||
while(PTSTAT & 0x00000001);
|
||||
MDCTL4=0x00000003;
|
||||
PTCMD=0x00000001;
|
||||
|
||||
while(PTSTAT & 0x00000001);
|
||||
while((MDSTAT4 & 0x0000003F) != 0x00000003);
|
||||
|
||||
SPI_DEASSERT();
|
||||
|
||||
SPIGCR0=0;
|
||||
SPIGCR0=1;
|
||||
SPIGCR1=0x00000003;
|
||||
SPIPC0=0x00000E00;
|
||||
SPIDAT1=0x04000000;
|
||||
|
||||
psc = 10;
|
||||
|
||||
SPIFMT0 = 0x00020008 | (psc << 8); //polarity 1
|
||||
SPIGCR1 = 0x01000003;
|
||||
// SPIINT0 = (1<<8); // RXINT
|
||||
// SPILVL = (1<<8); // RXINT
|
||||
|
||||
}
|
||||
|
||||
|
||||
void spi_putc_bl(u16 word)
|
||||
{
|
||||
SPIDAT0=word;
|
||||
while(!(SPIFLG & (1<<8)))
|
||||
Task_sleep(1);
|
||||
SPIFLG|=(1<<8);
|
||||
}
|
||||
|
||||
void spi_wr_en_bl()
|
||||
{
|
||||
SPI_ASSERT();
|
||||
Task_sleep(1);
|
||||
spi_putc_bl(0x06);
|
||||
Task_sleep(1);
|
||||
SPI_DEASSERT();
|
||||
Task_sleep(1);
|
||||
}
|
||||
|
||||
void spi_wr_buf_bl(u16 addr, u8 *buf, u16 len)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
spi_wr_en_bl();
|
||||
SPI_ASSERT();
|
||||
Task_sleep(1);
|
||||
spi_putc_bl(0x02);
|
||||
spi_putc_bl((addr & 0xFF00)>>8);
|
||||
spi_putc_bl((addr & 0x00FF)>>0);
|
||||
for(i=0;i<len;i++)
|
||||
spi_putc_bl(buf[i]);
|
||||
Task_sleep(1);
|
||||
SPI_DEASSERT();
|
||||
}
|
||||
|
||||
void spi_rd_buf_bl(u16 addr, u8 *buf, u16 len)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
SPI_ASSERT();
|
||||
Task_sleep(1);
|
||||
spi_putc_bl(0x03);
|
||||
spi_putc_bl((addr & 0xFF00)>>8);
|
||||
spi_putc_bl((addr & 0x00FF)>>0);
|
||||
for(i=0;i<len;i++)
|
||||
{
|
||||
spi_putc_bl(0xFF);
|
||||
buf[i]=SPIBUF&0xFF;
|
||||
}
|
||||
Task_sleep(1);
|
||||
SPI_DEASSERT();
|
||||
}
|
||||
|
||||
Void spiFxn(UArg a0, UArg a1)
|
||||
{
|
||||
u8 buf[49+32+6+16+1];
|
||||
u8 i;
|
||||
|
||||
spi_init();
|
||||
|
||||
spi_rd_buf_bl(0,buf,sizeof(buf));
|
||||
if(buf[48+32+6+16+1]==(u8)(mod256_cksum(buf,sizeof(buf)-1)+CKSUM_IV))
|
||||
{
|
||||
virt_in_states=((u32)buf[3]<<24)|((u32)buf[2]<<16)|((u32)buf[1]<<8)|((u32)buf[0]<<0);
|
||||
memcpy((char*)pkw_mem,(char*)&buf[4],sizeof(pkw_mem));
|
||||
led_states=((u32)buf[39]<<24)|((u32)buf[38]<<16)|((u32)buf[37]<<8)|((u32)buf[36]<<0);
|
||||
led_blink_states=((u32)buf[43]<<24)|((u32)buf[42]<<16)|((u32)buf[41]<<8)|((u32)buf[40]<<0);
|
||||
virt_in2_states=((u32)buf[47]<<24)|((u32)buf[46]<<16)|((u32)buf[45]<<8)|((u32)buf[44]<<0);
|
||||
memcpy((char*)cnt_mem,(char*)&buf[48],sizeof(cnt_mem));
|
||||
|
||||
comm_bits_act[0]=(u16)buf[48+32+0] | ((u16)buf[48+32+1]<<8);
|
||||
comm_bits_act[1]=(u16)buf[48+32+2] | ((u16)buf[48+32+3]<<8);
|
||||
comm_bits_act[2]=(u16)buf[48+32+4] | ((u16)buf[48+32+5]<<8);
|
||||
|
||||
memcpy((char*)saved_events,(char*)&buf[48+32+6],sizeof(saved_events));
|
||||
|
||||
saved_bank=buf[48+32+6+16];
|
||||
}
|
||||
else
|
||||
{
|
||||
saved_bank = 0;
|
||||
led_states = 0;
|
||||
led_blink_states = 0;
|
||||
virt_in_states=0;
|
||||
virt_in2_states=0;
|
||||
for(i=0;i<8;i++)
|
||||
{
|
||||
pkw_mem[i]=0.0;
|
||||
cnt_mem[i]=0.0;
|
||||
}
|
||||
}
|
||||
|
||||
spi_fram_restored=1;
|
||||
|
||||
for(;;)
|
||||
{
|
||||
if(Semaphore_pend(spi_semaphore,3000))
|
||||
{
|
||||
}
|
||||
else
|
||||
{
|
||||
if((log_manager.status & LOGMAN_STATUS_STARTED) && (log_manager.status & LOGMAN_STATUS_SOFT_STARTED))
|
||||
{
|
||||
buf[0]=(virt_in_states>>0)&0xFF;
|
||||
buf[1]=(virt_in_states>>8)&0xFF;
|
||||
buf[2]=(virt_in_states>>16)&0xFF;
|
||||
buf[3]=(virt_in_states>>24)&0xFF;
|
||||
memcpy((char*)&buf[4],(char*)pkw_mem,sizeof(pkw_mem));
|
||||
buf[36]=(led_states>>0)&0xFF;
|
||||
buf[37]=(led_states>>8)&0xFF;
|
||||
buf[38]=(led_states>>16)&0xFF;
|
||||
buf[39]=(led_states>>24)&0xFF;
|
||||
buf[40]=(led_blink_states>>0)&0xFF;
|
||||
buf[41]=(led_blink_states>>8)&0xFF;
|
||||
buf[42]=(led_blink_states>>16)&0xFF;
|
||||
buf[43]=(led_blink_states>>24)&0xFF;
|
||||
buf[44]=(virt_in2_states>>0)&0xFF;
|
||||
buf[45]=(virt_in2_states>>8)&0xFF;
|
||||
buf[46]=(virt_in2_states>>16)&0xFF;
|
||||
buf[47]=(virt_in2_states>>24)&0xFF;
|
||||
memcpy((char*)&buf[48],(char*)cnt_mem,sizeof(cnt_mem));
|
||||
buf[48+32+0]=(comm_bits_act[0]>>0)&0xFF;
|
||||
buf[48+32+1]=(comm_bits_act[0]>>8)&0xFF;
|
||||
buf[48+32+2]=(comm_bits_act[1]>>0)&0xFF;
|
||||
buf[48+32+3]=(comm_bits_act[1]>>8)&0xFF;
|
||||
buf[48+32+4]=(comm_bits_act[2]>>0)&0xFF;
|
||||
buf[48+32+5]=(comm_bits_act[2]>>8)&0xFF;
|
||||
memcpy((char*)&buf[48+32+6],(char*)saved_events,sizeof(saved_events));
|
||||
buf[48+32+6+16]=saved_bank;
|
||||
buf[48+32+6+16+1]=(u8)(mod256_cksum(buf,sizeof(buf)-1)+CKSUM_IV);
|
||||
spi_wr_buf_bl(0,buf,sizeof(buf));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
23
src/spi.h
Normal file
23
src/spi.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* spi.h
|
||||
*
|
||||
* Created on: 19-12-2016
|
||||
* Author: K
|
||||
*/
|
||||
|
||||
#ifndef SPI_H_
|
||||
#define SPI_H_
|
||||
|
||||
#include "misc.h"
|
||||
|
||||
#define SPI_DEASSERT() SETDATA8|=(1<<1);
|
||||
#define SPI_ASSERT() CLRDATA8|=(1<<1);
|
||||
|
||||
extern u8 spi_fram_restored;
|
||||
|
||||
extern void spi_init();
|
||||
extern void spi_putc(u16 word);
|
||||
|
||||
Void spiFxn(UArg a0, UArg a1);
|
||||
|
||||
#endif /* SPI_H_ */
|
||||
16
src/tdefs.h
Normal file
16
src/tdefs.h
Normal file
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* tdefs.h
|
||||
*
|
||||
* Created on: 06-12-2013
|
||||
* Author: Krzysztof Jakubczyk
|
||||
*/
|
||||
|
||||
#ifndef TDEFS_H_
|
||||
#define TDEFS_H_
|
||||
|
||||
typedef unsigned int u32;
|
||||
typedef short s16;
|
||||
typedef unsigned short u16;
|
||||
typedef unsigned char u8;
|
||||
|
||||
#endif /* TDEFS_H_ */
|
||||
16
src/version.h
Normal file
16
src/version.h
Normal file
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* version.h
|
||||
*
|
||||
* Created on: 06-02-2017
|
||||
* Author: K
|
||||
*/
|
||||
|
||||
#ifndef VERSION_H_
|
||||
#define VERSION_H_
|
||||
|
||||
#include "misc.h"
|
||||
|
||||
#define SW_VER_NO "DSP-3.0a " // 9 bytes
|
||||
#define SW_VER SW_VER_NO" "__DATE__
|
||||
|
||||
#endif /* VERSION_H_ */
|
||||
BIN
test_result.png
BIN
test_result.png
Binary file not shown.
|
Before Width: | Height: | Size: 312 KiB After Width: | Height: | Size: 317 KiB |
Reference in New Issue
Block a user